[people/ms/u-boot.git] / include / configs / alpr.h

/*
 * (C) Copyright 2006-2008
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*-----------------------------------------------------------------------
 * High Level Configuration Options
 *----------------------------------------------------------------------*/
#define CONFIG_ALPR		1	    /* Board is ebony		*/
#define CONFIG_440GX		1	    /* Specifc GX support	*/
#define CONFIG_440		1	    /* ... PPC440 family	*/
#define CONFIG_4xx		1	    /* ... PPC4xx family	*/
#define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_pre_init	*/
#define CONFIG_LAST_STAGE_INIT	1	    /* call last_stage_init()	*/

#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000

#define CONFIG_SYS_CLK_FREQ	33333333    /* external freq to pll	*/
#define CONFIG_4xx_DCACHE		/* Enable i- and d-cache	*/

/*-----------------------------------------------------------------------
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_SDRAM_BASE		0x00000000	/* _must_ be 0			*/
#define CONFIG_SYS_FLASH_BASE		0xffe00000	/* start of FLASH		*/
#define CONFIG_SYS_MONITOR_BASE	0xfffc0000	/* start of monitor		*/
#define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped pci memory		*/
#define	CONFIG_SYS_PCI_MEMSIZE		0x40000000	/* size of mapped pci memory	*/
#define CONFIG_SYS_ISRAM_BASE		0xc0000000	/* internal SRAM		*/
#define CONFIG_SYS_PCI_BASE		0xd0000000	/* internal PCI regs		*/
#define CONFIG_SYS_PCI_MEMBASE1	CONFIG_SYS_PCI_MEMBASE  + 0x10000000
#define CONFIG_SYS_PCI_MEMBASE2	CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
#define CONFIG_SYS_PCI_MEMBASE3	CONFIG_SYS_PCI_MEMBASE2 + 0x10000000


#define CONFIG_SYS_FPGA_BASE	    (CONFIG_SYS_PERIPHERAL_BASE + 0x08300000)
#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)

/*-----------------------------------------------------------------------
 * Initial RAM & stack pointer (placed in internal SRAM)
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_TEMP_STACK_OCM  1
#define CONFIG_SYS_OCM_DATA_ADDR   CONFIG_SYS_ISRAM_BASE
#define CONFIG_SYS_INIT_RAM_ADDR   CONFIG_SYS_ISRAM_BASE  /* Initial RAM address	*/
#define CONFIG_SYS_INIT_RAM_SIZE    0x2000	    /* Size of used area in RAM	*/

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)

#define CONFIG_SYS_MONITOR_LEN	    (256 * 1024)    /* Reserve 256 kB for Mon	*/
#define CONFIG_SYS_MALLOC_LEN	    (128 * 1024)    /* Reserve 128 kB for malloc*/

/*-----------------------------------------------------------------------
 * Serial Port
 *----------------------------------------------------------------------*/
#define CONFIG_CONS_INDEX	2	/* Use UART1			*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_serial_clock()

#undef	CONFIG_SYS_EXT_SERIAL_CLOCK
#define CONFIG_BAUDRATE		115200

#define CONFIG_SYS_BAUDRATE_TABLE  \
    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

/*-----------------------------------------------------------------------
 * FLASH related
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_FLASH_CFI		1	/* The flash is CFI compatible		*/
#define CONFIG_FLASH_CFI_DRIVER	1	/* Use common CFI driver		*/
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash	*/

#define CONFIG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/

#define CONFIG_ENV_SECT_SIZE	0x10000	/* size of one complete sector		*/
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)

/*-----------------------------------------------------------------------
 * DDR SDRAM
 *----------------------------------------------------------------------*/
#undef CONFIG_SPD_EEPROM		/* Don't use SPD EEPROM for setup	*/
#define CONFIG_SDRAM_BANK0	1	/* init onboard DDR SDRAM bank 0	*/
#undef CONFIG_SDRAM_ECC			/* enable ECC support			*/
#define CONFIG_SYS_SDRAM_TABLE	{ \
		{(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \
		{(64 << 20),  12, 0x00082001}} /* 64MB mode 2, 12x9(4)	*/

/*-----------------------------------------------------------------------
 * I2C
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_PPC4XX
#define CONFIG_SYS_I2C_PPC4XX_CH0
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		100000
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
#define CONFIG_SYS_I2C_NOPROBES	{ {0, 0x69} }	/* Don't probe these addrs */

/*-----------------------------------------------------------------------
 * I2C EEPROM (PCF8594C)
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x54	/* EEPROM PCF8594C		*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
/* mask of address bits that overflow into the "EEPROM chip address"	*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3	/* The Philips PCF8594C has	*/
					/* 8 byte page write mode using */
					/* last 3 bits of the address	*/
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	40   /* and takes up to 40 msec */

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \"run kernelx\" to boot the system;"			\
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth3\0"							\
	"hostname=alpr\0"						\
	"fdt_file=alpr/alpr.dtb\0"					\
	"fdt_addr=400000\0"						\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath} ${init}\0"		\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate} " \
		"mem=193M\0"						\
	"flash_nfs=run nfsargs addip addtty;"				\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip addtty;"				\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
		"bootm\0"						\
	"net_nfs_fdt=tftp 200000 ${bootfile};"				\
		"tftp ${fdt_addr} ${fdt_file};"				\
		"run nfsargs addip addtty;"				\
		"bootm 200000 - ${fdt_addr}\0"				\
	"rootpath=/opt/projects/alpr/nfs_root\0"			\
	"bootfile=/alpr/uImage\0"					\
	"kernel_addr=fff00000\0"					\
	"ramdisk_addr=fff10000\0"					\
	"load=tftp 100000 /alpr/u-boot/u-boot.bin\0"			\
	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"	\
		"cp.b 100000 fffc0000 40000;"			        \
		"setenv filesize;saveenv\0"				\
	"upd=run load update\0"						\
	"ethprime=ppc_4xx_eth3\0"					\
	"ethact=ppc_4xx_eth3\0"						\
	"autoload=no\0"							\
	"ipconfig=dhcp;setenv serverip 11.0.0.152\0"			\
	"load_fpga=fpga load 0 ffe00000 10dd9a\0"			\
	"mtdargs=setenv bootargs root=/dev/mtdblock6 rw "		\
		"rootfstype=jffs2 init=/sbin/init\0"			\
	"kernel1_mtd=nand read 200000 0 200000;run mtdargs addip addtty"\
		";bootm 200000\0"					\
	"kernel2_mtd=nand read 200000 200000 200000;run mtdargs addip "	\
		"addtty;bootm 200000\0"					\
	"kernel1=setenv actkernel 'kernel1';run load_fpga "		\
		"kernel1_mtd\0"						\
	"kernel2=setenv actkernel 'kernel2';run load_fpga "		\
		"kernel2_mtd\0"						\
	""

#define CONFIG_BOOTCOMMAND	"run kernel2"

#define CONFIG_BOOTDELAY	2	/* autoboot after 5 seconds	*/

#define CONFIG_BAUDRATE		115200

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_PHY_ADDR		0x02	/* dummy setting, no EMAC0 used	*/
#define CONFIG_PHY1_ADDR	0x03	/* dummy setting, no EMAC1 used	*/
#define CONFIG_PHY2_ADDR	0x01	/* PHY address for EMAC2	*/
#define CONFIG_PHY3_ADDR	0x02	/* PHY address for EMAC3	*/
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
#define CONFIG_HAS_ETH3
#define CONFIG_PHY_RESET	1	/* reset phy upon startup	*/
#define CONFIG_M88E1111_PHY	1	/* needed for PHY specific setup*/
#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
#define CONFIG_SYS_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */

#define CONFIG_NETCONSOLE		/* include NetConsole support	*/


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_FPGA
#define CONFIG_CMD_I2C
#undef CONFIG_CMD_LOADB
#undef CONFIG_CMD_LOADS
#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NET
#undef CONFIG_CMD_NFS
#define CONFIG_CMD_PCI

#undef CONFIG_WATCHDOG			/* watchdog disabled		*/

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_ALT_MEMTEST		1	/* Enable more extensive memtest*/
#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */

#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
#define CONFIG_LOOPW            1       /* enable loopw command         */
#define CONFIG_MX_CYCLIC	1       /* enable mdc/mwc commands      */
#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE	1	/* include version env variable */

#define CONFIG_SYS_4xx_RESET_TYPE	0x2	/* use chip reset on this board	*/

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
/* General PCI */
#define CONFIG_PCI			/* include pci support		*/
#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
#define CONFIG_SYS_PCI_TARGBASE    0x80000000	/* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
#define CONFIG_PCI_BOOTDELAY	1       /* enable pci bootdelay variable*/

/* Board-specific PCI */
#define CONFIG_SYS_PCI_TARGET_INIT		/* let board init pci target    */
#define CONFIG_SYS_PCI_MASTER_INIT

#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */

/*-----------------------------------------------------------------------
 * FPGA stuff
 *-----------------------------------------------------------------------*/
#define CONFIG_FPGA
#define CONFIG_FPGA_ALTERA
#define CONFIG_FPGA_CYCLON2
#define CONFIG_SYS_FPGA_CHECK_CTRLC
#define CONFIG_SYS_FPGA_PROG_FEEDBACK
#define CONFIG_FPGA_COUNT       1		/* Ich habe 2 ... aber in
					Reihe geschaltet -> sollte gehen,
					aufpassen mit Datasize ist jetzt
					halt doppelt so gross ... Seite 306
					ist das mit den multiple Device in PS
					Mode erklaert ...*/

/* FPGA program pin configuration */
#define CONFIG_SYS_GPIO_CLK		18	/* FPGA clk pin (cpu output)		*/
#define CONFIG_SYS_GPIO_DATA		19	/* FPGA data pin (cpu output)		*/
#define CONFIG_SYS_GPIO_STATUS		20	/* FPGA status pin (cpu input)		*/
#define CONFIG_SYS_GPIO_CONFIG		21	/* FPGA CONFIG pin (cpu output)		*/
#define CONFIG_SYS_GPIO_CON_DON	22	/* FPGA CONFIG_DONE pin (cpu input)	*/

#define CONFIG_SYS_GPIO_SEL_DPR	14	/* cpu output */
#define CONFIG_SYS_GPIO_SEL_AVR	15	/* cpu output */
#define CONFIG_SYS_GPIO_PROG_EN	23	/* cpu output */

/*-----------------------------------------------------------------------
 * Definitions for GPIO setup
 *-----------------------------------------------------------------------*/
#define CONFIG_SYS_GPIO_SHUTDOWN	(0x80000000 >> 6)
#define CONFIG_SYS_GPIO_SSD_EMPTY	(0x80000000 >> 9)
#define CONFIG_SYS_GPIO_EREADY		(0x80000000 >> 26)
#define CONFIG_SYS_GPIO_REV0		(0x80000000 >> 14)
#define CONFIG_SYS_GPIO_REV1		(0x80000000 >> 15)

/*-----------------------------------------------------------------------
 * NAND-FLASH stuff
 *-----------------------------------------------------------------------*/
#define CONFIG_SYS_MAX_NAND_DEVICE	4
#define CONFIG_SYS_NAND_BASE		0xF0000000	/* NAND FLASH Base Address	*/
#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE + 0, CONFIG_SYS_NAND_BASE + 2,	\
				  CONFIG_SYS_NAND_BASE + 4, CONFIG_SYS_NAND_BASE + 6 }
#define CONFIG_SYS_NAND_QUIET_TEST	1	/* don't warn upon unknown NAND flash	*/

/*-----------------------------------------------------------------------
 * External Bus Controller (EBC) Setup
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_FLASH		CONFIG_SYS_FLASH_BASE

/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
#define CONFIG_SYS_EBC_PB0AP		0x92015480
#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_FLASH | 0x3A000) /* BS=2MB,BU=R/W,BW=16bit */

/* Memory Bank 1 (NAND-FLASH) initialization					*/
#define CONFIG_SYS_EBC_PB1AP		0x01840380	/* TWT=3			*/
#define CONFIG_SYS_EBC_PB1CR		(CONFIG_SYS_NAND_BASE | 0x18000) /* BS=1MB,BU=R/W,BW=8bit */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif

/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT	1
#define CONFIG_OF_BOARD_SETUP	1

#endif	/* __CONFIG_H */
Commit	Line	Data
899620c2	1	/*
9462732a	2	* (C) Copyright 2006-2008
899620c2 SR	3	* Stefan Roese, DENX Software Engineering, sr@denx.de.
899620c2 SR	4	*
3765b3e7	5	* SPDX-License-Identifier: GPL-2.0+
899620c2 SR	6	*/
	7
	8	#ifndef __CONFIG_H
	9	#define __CONFIG_H
	10
	11	/*-----------------------------------------------------------------------
	12	* High Level Configuration Options
	13	----------------------------------------------------------------------/
	14	#define CONFIG_ALPR 1 /* Board is ebony */
	15	#define CONFIG_440GX 1 /* Specifc GX support */
efa35cf1	16	#define CONFIG_440 1 /* ... PPC440 family */
899620c2 SR	17	#define CONFIG_4xx 1 /* ... PPC4xx family */
899620c2 SR	18	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
1c2ce226	19	#define CONFIG_LAST_STAGE_INIT 1 /* call last_stage_init() */
2ae18241 WD	20
	21	#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
	22
1c2ce226	23	#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
511e4f9e	24	#define CONFIG_4xx_DCACHE /* Enable i- and d-cache */
899620c2 SR	25
	26	/*-----------------------------------------------------------------------
	27	* Base addresses -- Note these are effective addresses where the
	28	* actual resources get mapped (not physical addresses)
	29	----------------------------------------------------------------------/
6d0f6bcf JCPV	30	#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
	31	#define CONFIG_SYS_FLASH_BASE 0xffe00000 /* start of FLASH */
	32	#define CONFIG_SYS_MONITOR_BASE 0xfffc0000 /* start of monitor */
	33	#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
	34	#define CONFIG_SYS_PCI_MEMSIZE 0x40000000 /* size of mapped pci memory */
6d0f6bcf JCPV	35	#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */
	36	#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
	37	#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
	38	#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
	39	#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
	40
	41
	42	#define CONFIG_SYS_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08300000)
	43	#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
899620c2 SR	44
	45	/*-----------------------------------------------------------------------
	46	* Initial RAM & stack pointer (placed in internal SRAM)
	47	----------------------------------------------------------------------/
6d0f6bcf JCPV	48	#define CONFIG_SYS_TEMP_STACK_OCM 1
	49	#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
	50	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
553f0982	51	#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
899620c2	52
25ddd1fb	53	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
800eb096	54	#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
899620c2	55
6d0f6bcf JCPV	56	#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
6d0f6bcf JCPV	57	#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
899620c2 SR	58
	59	/*-----------------------------------------------------------------------
	60	* Serial Port
	61	----------------------------------------------------------------------/
550650dd SR	62	#define CONFIG_CONS_INDEX 2 /* Use UART1 */
	63	#define CONFIG_SYS_NS16550
	64	#define CONFIG_SYS_NS16550_SERIAL
	65	#define CONFIG_SYS_NS16550_REG_SIZE 1
	66	#define CONFIG_SYS_NS16550_CLK get_serial_clock()
	67
6d0f6bcf	68	#undef CONFIG_SYS_EXT_SERIAL_CLOCK
899620c2	69	#define CONFIG_BAUDRATE 115200
899620c2	70
6d0f6bcf	71	#define CONFIG_SYS_BAUDRATE_TABLE \
899620c2 SR	72	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
899620c2 SR	73
899620c2 SR	74	/*-----------------------------------------------------------------------
	75	* FLASH related
	76	----------------------------------------------------------------------/
6d0f6bcf	77	#define CONFIG_SYS_FLASH_CFI 1 /* The flash is CFI compatible */
00b1883a	78	#define CONFIG_FLASH_CFI_DRIVER 1 /* Use common CFI driver */
6d0f6bcf JCPV	79	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	80	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
	81	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
	82	#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
	83	#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
899620c2	84
5a1aceb0	85	#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
899620c2	86
0e8d1586	87	#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
6d0f6bcf	88	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
0e8d1586	89	#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
899620c2 SR	90
899620c2 SR	91	/* Address and size of Redundant Environment Sector */
0e8d1586 JCPV	92	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
0e8d1586 JCPV	93	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
899620c2 SR	94
	95	/*-----------------------------------------------------------------------
	96	* DDR SDRAM
	97	----------------------------------------------------------------------/
	98	#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */
	99	#define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0 */
	100	#undef CONFIG_SDRAM_ECC /* enable ECC support */
6d0f6bcf	101	#define CONFIG_SYS_SDRAM_TABLE { \
899620c2 SR	102	{(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \
	103	{(64 << 20), 12, 0x00082001}} /* 64MB mode 2, 12x9(4) */
	104
	105	/*-----------------------------------------------------------------------
	106	* I2C
	107	----------------------------------------------------------------------/
880540de DE	108	#define CONFIG_SYS_I2C
	109	#define CONFIG_SYS_I2C_PPC4XX
	110	#define CONFIG_SYS_I2C_PPC4XX_CH0
	111	#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
	112	#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
	113	#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */
899620c2 SR	114
	115	/*-----------------------------------------------------------------------
	116	* I2C EEPROM (PCF8594C)
	117	----------------------------------------------------------------------/
6d0f6bcf JCPV	118	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 /* EEPROM PCF8594C */
6d0f6bcf JCPV	119	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
899620c2	120	/* mask of address bits that overflow into the "EEPROM chip address" */
6d0f6bcf JCPV	121	#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
6d0f6bcf JCPV	122	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* The Philips PCF8594C has */
899620c2 SR	123	/* 8 byte page write mode using */
899620c2 SR	124	/* last 3 bits of the address */
6d0f6bcf	125	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 40 /* and takes up to 40 msec */
899620c2 SR	126
899620c2 SR	127	#define CONFIG_PREBOOT "echo;" \
6304430e	128	"echo Type \"run kernelx\" to boot the system;" \
899620c2 SR	129	"echo"
	130
	131	#undef CONFIG_BOOTARGS
	132
	133	#define CONFIG_EXTRA_ENV_SETTINGS \
1c2ce226	134	"netdev=eth3\0" \
899620c2	135	"hostname=alpr\0" \
9462732a SR	136	"fdt_file=alpr/alpr.dtb\0" \
9462732a SR	137	"fdt_addr=400000\0" \
899620c2	138	"nfsargs=setenv bootargs root=/dev/nfs rw " \
6304430e	139	"nfsroot=${serverip}:${rootpath} ${init}\0" \
899620c2 SR	140	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	141	"addip=setenv bootargs ${bootargs} " \
	142	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	143	":${hostname}:${netdev}:off panic=1\0" \
1c2ce226 SR	144	"addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate} " \
1c2ce226 SR	145	"mem=193M\0" \
899620c2 SR	146	"flash_nfs=run nfsargs addip addtty;" \
	147	"bootm ${kernel_addr}\0" \
	148	"flash_self=run ramargs addip addtty;" \
	149	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
	150	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
93e14596	151	"bootm\0" \
9462732a SR	152	"net_nfs_fdt=tftp 200000 ${bootfile};" \
	153	"tftp ${fdt_addr} ${fdt_file};" \
	154	"run nfsargs addip addtty;" \
	155	"bootm 200000 - ${fdt_addr}\0" \
1c2ce226 SR	156	"rootpath=/opt/projects/alpr/nfs_root\0" \
1c2ce226 SR	157	"bootfile=/alpr/uImage\0" \
899620c2 SR	158	"kernel_addr=fff00000\0" \
899620c2 SR	159	"ramdisk_addr=fff10000\0" \
1c2ce226	160	"load=tftp 100000 /alpr/u-boot/u-boot.bin\0" \
899620c2 SR	161	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
	162	"cp.b 100000 fffc0000 40000;" \
	163	"setenv filesize;saveenv\0" \
d8ab58b2	164	"upd=run load update\0" \
f16c1da9 SR	165	"ethprime=ppc_4xx_eth3\0" \
	166	"ethact=ppc_4xx_eth3\0" \
	167	"autoload=no\0" \
	168	"ipconfig=dhcp;setenv serverip 11.0.0.152\0" \
f16c1da9 SR	169	"load_fpga=fpga load 0 ffe00000 10dd9a\0" \
	170	"mtdargs=setenv bootargs root=/dev/mtdblock6 rw " \
	171	"rootfstype=jffs2 init=/sbin/init\0" \
	172	"kernel1_mtd=nand read 200000 0 200000;run mtdargs addip addtty"\
	173	";bootm 200000\0" \
	174	"kernel2_mtd=nand read 200000 200000 200000;run mtdargs addip " \
	175	"addtty;bootm 200000\0" \
6304430e SR	176	"kernel1=setenv actkernel 'kernel1';run load_fpga " \
	177	"kernel1_mtd\0" \
	178	"kernel2=setenv actkernel 'kernel2';run load_fpga " \
	179	"kernel2_mtd\0" \
899620c2	180	""
f16c1da9 SR	181
f16c1da9 SR	182	#define CONFIG_BOOTCOMMAND "run kernel2"
899620c2	183
1c2ce226	184	#define CONFIG_BOOTDELAY 2 /* autoboot after 5 seconds */
899620c2 SR	185
	186	#define CONFIG_BAUDRATE 115200
	187
	188	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	189	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
899620c2	190
96e21f86	191	#define CONFIG_PPC4xx_EMAC
899620c2	192	#define CONFIG_MII 1 /* MII PHY management */
899620c2 SR	193	#define CONFIG_PHY_ADDR 0x02 /* dummy setting, no EMAC0 used */
899620c2 SR	194	#define CONFIG_PHY1_ADDR 0x03 /* dummy setting, no EMAC1 used */
1c2ce226 SR	195	#define CONFIG_PHY2_ADDR 0x01 /* PHY address for EMAC2 */
1c2ce226 SR	196	#define CONFIG_PHY3_ADDR 0x02 /* PHY address for EMAC3 */
899620c2 SR	197	#define CONFIG_HAS_ETH0
	198	#define CONFIG_HAS_ETH1
	199	#define CONFIG_HAS_ETH2
	200	#define CONFIG_HAS_ETH3
	201	#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
ec0c2ec7	202	#define CONFIG_M88E1111_PHY 1 /* needed for PHY specific setup*/
899620c2	203	#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
6d0f6bcf	204	#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
5bc528fa SR	205
5bc528fa SR	206	#define CONFIG_NETCONSOLE /* include NetConsole support */
899620c2	207
0b361c91	208
80ff4f99 JL	209	/*
	210	* BOOTP options
	211	*/
	212	#define CONFIG_BOOTP_BOOTFILESIZE
	213	#define CONFIG_BOOTP_BOOTPATH
	214	#define CONFIG_BOOTP_GATEWAY
	215	#define CONFIG_BOOTP_HOSTNAME
	216
	217
0b361c91 JL	218	/*
	219	* Command line configuration.
	220	*/
	221	#include <config_cmd_default.h>
	222
0b361c91	223	#define CONFIG_CMD_DHCP
0b361c91	224	#define CONFIG_CMD_EEPROM
0b361c91 JL	225	#define CONFIG_CMD_FPGA
0b361c91 JL	226	#define CONFIG_CMD_I2C
288991c9 SR	227	#undef CONFIG_CMD_LOADB
288991c9 SR	228	#undef CONFIG_CMD_LOADS
0b361c91 JL	229	#define CONFIG_CMD_MII
	230	#define CONFIG_CMD_NAND
	231	#define CONFIG_CMD_NET
8c92af7b	232	#undef CONFIG_CMD_NFS
288991c9	233	#define CONFIG_CMD_PCI
899620c2 SR	234
	235	#undef CONFIG_WATCHDOG /* watchdog disabled */
	236
	237	/*
	238	* Miscellaneous configurable options
	239	*/
6d0f6bcf	240	#define CONFIG_SYS_LONGHELP /* undef to save memory */
0b361c91	241	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	242	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
899620c2	243	#else
6d0f6bcf	244	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
899620c2	245	#endif
6d0f6bcf JCPV	246	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	247	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	248	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
899620c2	249
6d0f6bcf JCPV	250	#define CONFIG_SYS_ALT_MEMTEST 1 /* Enable more extensive memtest*/
	251	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
	252	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
899620c2	253
6d0f6bcf JCPV	254	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
6d0f6bcf JCPV	255	#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
899620c2	256
5bc528fa	257	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
899620c2	258	#define CONFIG_LOOPW 1 /* enable loopw command */
1636d1c8	259	#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
899620c2	260	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
1c2ce226 SR	261	#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
1c2ce226 SR	262
6d0f6bcf	263	#define CONFIG_SYS_4xx_RESET_TYPE 0x2 /* use chip reset on this board */
899620c2	264
899620c2 SR	265	/*-----------------------------------------------------------------------
	266	* PCI stuff
	267	*-----------------------------------------------------------------------
	268	*/
	269	/* General PCI */
	270	#define CONFIG_PCI /* include pci support */
842033e6	271	#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
899620c2 SR	272	#define CONFIG_PCI_PNP /* do pci plug-and-play */
899620c2 SR	273	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
6d0f6bcf	274	#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
1c2ce226	275	#define CONFIG_PCI_BOOTDELAY 1 /* enable pci bootdelay variable*/
899620c2 SR	276
899620c2 SR	277	/* Board-specific PCI */
6d0f6bcf JCPV	278	#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
6d0f6bcf JCPV	279	#define CONFIG_SYS_PCI_MASTER_INIT
899620c2	280
6d0f6bcf JCPV	281	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
6d0f6bcf JCPV	282	#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
899620c2 SR	283
	284	/*-----------------------------------------------------------------------
	285	* FPGA stuff
1c2ce226	286	-----------------------------------------------------------------------/
0133502e MF	287	#define CONFIG_FPGA
	288	#define CONFIG_FPGA_ALTERA
	289	#define CONFIG_FPGA_CYCLON2
6d0f6bcf JCPV	290	#define CONFIG_SYS_FPGA_CHECK_CTRLC
6d0f6bcf JCPV	291	#define CONFIG_SYS_FPGA_PROG_FEEDBACK
899620c2 SR	292	#define CONFIG_FPGA_COUNT 1 /* Ich habe 2 ... aber in
	293	Reihe geschaltet -> sollte gehen,
	294	aufpassen mit Datasize ist jetzt
	295	halt doppelt so gross ... Seite 306
	296	ist das mit den multiple Device in PS
	297	Mode erklaert ...*/
	298
899620c2	299	/* FPGA program pin configuration */
6d0f6bcf JCPV	300	#define CONFIG_SYS_GPIO_CLK 18 /* FPGA clk pin (cpu output) */
	301	#define CONFIG_SYS_GPIO_DATA 19 /* FPGA data pin (cpu output) */
	302	#define CONFIG_SYS_GPIO_STATUS 20 /* FPGA status pin (cpu input) */
	303	#define CONFIG_SYS_GPIO_CONFIG 21 /* FPGA CONFIG pin (cpu output) */
	304	#define CONFIG_SYS_GPIO_CON_DON 22 /* FPGA CONFIG_DONE pin (cpu input) */
899620c2	305
6d0f6bcf JCPV	306	#define CONFIG_SYS_GPIO_SEL_DPR 14 /* cpu output */
	307	#define CONFIG_SYS_GPIO_SEL_AVR 15 /* cpu output */
	308	#define CONFIG_SYS_GPIO_PROG_EN 23 /* cpu output */
899620c2	309
1c2ce226 SR	310	/*-----------------------------------------------------------------------
	311	* Definitions for GPIO setup
	312	-----------------------------------------------------------------------/
6d0f6bcf JCPV	313	#define CONFIG_SYS_GPIO_SHUTDOWN (0x80000000 >> 6)
	314	#define CONFIG_SYS_GPIO_SSD_EMPTY (0x80000000 >> 9)
	315	#define CONFIG_SYS_GPIO_EREADY (0x80000000 >> 26)
	316	#define CONFIG_SYS_GPIO_REV0 (0x80000000 >> 14)
	317	#define CONFIG_SYS_GPIO_REV1 (0x80000000 >> 15)
1c2ce226 SR	318
1c2ce226 SR	319	/*-----------------------------------------------------------------------
899620c2	320	* NAND-FLASH stuff
1c2ce226	321	-----------------------------------------------------------------------/
6d0f6bcf	322	#define CONFIG_SYS_MAX_NAND_DEVICE 4
6d0f6bcf JCPV	323	#define CONFIG_SYS_NAND_BASE 0xF0000000 /* NAND FLASH Base Address */
	324	#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE + 0, CONFIG_SYS_NAND_BASE + 2, \
	325	CONFIG_SYS_NAND_BASE + 4, CONFIG_SYS_NAND_BASE + 6 }
	326	#define CONFIG_SYS_NAND_QUIET_TEST 1 /* don't warn upon unknown NAND flash */
899620c2 SR	327
	328	/*-----------------------------------------------------------------------
	329	* External Bus Controller (EBC) Setup
	330	----------------------------------------------------------------------/
6d0f6bcf	331	#define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE
899620c2 SR	332
899620c2 SR	333	/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
6d0f6bcf JCPV	334	#define CONFIG_SYS_EBC_PB0AP 0x92015480
6d0f6bcf JCPV	335	#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH \| 0x3A000) /* BS=2MB,BU=R/W,BW=16bit */
5bc528fa SR	336
5bc528fa SR	337	/* Memory Bank 1 (NAND-FLASH) initialization */
6d0f6bcf JCPV	338	#define CONFIG_SYS_EBC_PB1AP 0x01840380 /* TWT=3 */
6d0f6bcf JCPV	339	#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_NAND_BASE \| 0x18000) /* BS=1MB,BU=R/W,BW=8bit */
899620c2 SR	340
	341	/*
	342	* For booting Linux, the board info and command line data
	343	* have to be in the first 8 MB of memory, since this is
	344	* the maximum mapped by the Linux kernel during initialization.
	345	*/
6d0f6bcf	346	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
899620c2	347
0b361c91	348	#if defined(CONFIG_CMD_KGDB)
899620c2 SR	349	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
	350	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	351	#endif
9462732a SR	352
	353	/* pass open firmware flat tree */
	354	#define CONFIG_OF_LIBFDT 1
	355	#define CONFIG_OF_BOARD_SETUP 1
	356
899620c2	357	#endif /* __CONFIG_H */