[people/ms/u-boot.git] / include / configs / cm_fx6.h

/*
 * Config file for Compulab CM-FX6 board
 *
 * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
 *
 * Author: Nikita Kiryanov <nikita@compulab.co.il>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_CM_FX6_H
#define __CONFIG_CM_FX6_H

#include "mx6_common.h"

#ifndef CONFIG_SPL_BUILD
#include <config_distro_defaults.h>
#endif

/* Machine config */
#define CONFIG_SYS_LITTLE_ENDIAN
#define CONFIG_MACH_TYPE		4273

/* MMC */
#define CONFIG_SYS_FSL_USDHC_NUM	3
#define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC2_BASE_ADDR

/* RAM */
#define PHYS_SDRAM_1			MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_2			MMDC1_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_NR_DRAM_BANKS		2
#define CONFIG_SYS_MEMTEST_START	0x10000000
#define CONFIG_SYS_MEMTEST_END		0x10010000
#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
#define CONFIG_SYS_INIT_SP_OFFSET \
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

/* Serial console */
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE		UART4_BASE
#define CONFIG_SYS_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200}

/* SPI flash */
#define CONFIG_SF_DEFAULT_BUS		0
#define CONFIG_SF_DEFAULT_CS		0
#define CONFIG_SF_DEFAULT_SPEED		25000000
#define CONFIG_SF_DEFAULT_MODE		(SPI_MODE_0)

/* MTD support */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define CONFIG_SPI_FLASH_MTD
#endif

/* Environment */
#define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
#define CONFIG_ENV_SPI_MODE		CONFIG_SF_DEFAULT_MODE
#define CONFIG_ENV_SPI_BUS		CONFIG_SF_DEFAULT_BUS
#define CONFIG_ENV_SPI_CS		CONFIG_SF_DEFAULT_CS
#define CONFIG_ENV_SECT_SIZE		(64 * 1024)
#define CONFIG_ENV_SIZE			(8 * 1024)
#define CONFIG_ENV_OFFSET		(768 * 1024)

#ifndef CONFIG_SPL_BUILD
#define CONFIG_EXTRA_ENV_SETTINGS \
	"fdt_high=0xffffffff\0" \
	"initrd_high=0xffffffff\0" \
	"fdt_addr_r=0x18000000\0" \
	"ramdisk_addr_r=0x13000000\0" \
	"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
	"pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
	"scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
	"stdin=serial,usbkbd\0" \
	"stdout=serial,vga\0" \
	"stderr=serial,vga\0" \
	"panel=HDMI\0" \
	"autoload=no\0" \
	"uImage=uImage-cm-fx6\0" \
	"zImage=zImage-cm-fx6\0" \
	"kernel=uImage-cm-fx6\0" \
	"dtb=cm-fx6.dtb\0" \
	"console=ttymxc3,115200\0" \
	"ethprime=FEC0\0" \
	"video_hdmi=mxcfb0:dev=hdmi,1920x1080M-32@50,if=RGB32\0" \
	"video_dvi=mxcfb0:dev=dvi,1280x800M-32@50,if=RGB32\0" \
	"doboot=bootm ${kernel_addr_r}\0" \
	"doloadfdt=false\0" \
	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
	"setboottypez=setenv kernel ${zImage};" \
		"setenv doboot bootz ${kernel_addr_r} - ${fdt_addr_r};" \
		"setenv doloadfdt true;\0" \
	"setboottypem=setenv kernel ${uImage};" \
		"setenv doboot bootm ${kernel_addr_r};" \
		"setenv doloadfdt false;\0"\
	"mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
	"sataroot=/dev/sda2 rw rootwait\0" \
	"nandroot=/dev/mtdblock4 rw\0" \
	"nandrootfstype=ubifs\0" \
	"mmcargs=setenv bootargs console=${console} root=${mmcroot} " \
		"${video} ${extrabootargs}\0" \
	"sataargs=setenv bootargs console=${console} root=${sataroot} " \
		"${video} ${extrabootargs}\0" \
	"nandargs=setenv bootargs console=${console} " \
		"root=${nandroot} " \
		"rootfstype=${nandrootfstype} " \
		"${video} ${extrabootargs}\0" \
	"nandboot=if run nandloadkernel; then " \
			"run nandloadfdt;" \
			"run setboottypem;" \
			"run storagebootcmd;" \
			"run setboottypez;" \
			"run storagebootcmd;" \
		"fi;\0" \
	"run_eboot=echo Starting EBOOT ...; "\
		"mmc dev 2 && " \
		"mmc rescan && mmc read 10042000 a 400 && go 10042000\0" \
	"loadkernel=load ${storagetype} ${storagedev} ${kernel_addr_r} ${kernel};\0"\
	"loadfdt=load ${storagetype} ${storagedev} ${fdt_addr_r} ${dtb};\0" \
	"nandloadkernel=nand read ${kernel_addr_r} 0 780000;\0" \
	"nandloadfdt=nand read ${fdt_addr_r} 780000 80000;\0" \
	"setupmmcboot=setenv storagetype mmc; setenv storagedev 2;\0" \
	"setupsataboot=setenv storagetype sata; setenv storagedev 0;\0" \
	"setupnandboot=setenv storagetype nand;\0" \
	"storagebootcmd=echo Booting from ${storagetype} ...;" \
			"run ${storagetype}args; run doboot;\0" \
	"trybootk=if run loadkernel; then " \
		"if ${doloadfdt}; then " \
			"run loadfdt;" \
		"fi;" \
		"run storagebootcmd;" \
		"fi;\0" \
	"trybootsmz=" \
		"run setboottypem;" \
		"run trybootk;" \
		"run setboottypez;" \
		"run trybootk;\0" \
	"legacy_bootcmd=" \
		"run setupmmcboot;" \
		"mmc dev ${storagedev};" \
		"if mmc rescan; then " \
			"run trybootsmz;" \
		"fi;" \
		"run setupsataboot;" \
		"if sata init; then " \
			"run trybootsmz;" \
		"fi;" \
		"run setupnandboot;" \
		"run nandboot;\0" \
	BOOTENV

#define CONFIG_PREBOOT		"usb start;sf probe"

#define BOOT_TARGET_DEVICES(func) \
	func(USB, usb, 0) \
	func(MMC, mmc, 2) \
	func(SATA, sata, 0)

#include <config_distro_bootcmd.h>
#else
#define CONFIG_EXTRA_ENV_SETTINGS
#endif

/* SPI */
#define CONFIG_SPI
#define CONFIG_MXC_SPI

/* NAND */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SYS_NAND_BASE		0x40000000
#define CONFIG_SYS_NAND_MAX_CHIPS	1
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_NAND_MXS
#define CONFIG_SYS_NAND_ONFI_DETECTION
/* APBH DMA is required for NAND support */
#define CONFIG_APBH_DMA
#define CONFIG_APBH_DMA_BURST
#define CONFIG_APBH_DMA_BURST8
#endif

/* Ethernet */
#define CONFIG_FEC_MXC
#define CONFIG_FEC_MXC_PHYADDR		0
#define CONFIG_FEC_XCV_TYPE		RGMII
#define IMX_FEC_BASE			ENET_BASE_ADDR
#define CONFIG_PHY_ATHEROS
#define CONFIG_MII
#define CONFIG_ETHPRIME			"FEC0"
#define CONFIG_ARP_TIMEOUT		200UL
#define CONFIG_NET_RETRY_COUNT		5

/* USB */
#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS		0
#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET	/* For OTG port */

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
#define CONFIG_SYS_I2C_SPEED		100000
#define CONFIG_SYS_MXC_I2C3_SPEED	400000

#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
#define CONFIG_SYS_I2C_EEPROM_BUS	2

/* SATA */
#define CONFIG_SYS_SATA_MAX_DEVICE	1
#define CONFIG_LBA48
#define CONFIG_DWC_AHSATA_PORT_ID	0
#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR

/* Boot */
#define CONFIG_SYS_BOOTMAPSZ	        (8 << 20)
#define CONFIG_SERIAL_TAG

/* misc */
#define CONFIG_SYS_MALLOC_LEN			(10 * 1024 * 1024)
#define CONFIG_MISC_INIT_R

/* SPL */
#include "imx6_spl.h"
#define CONFIG_SYS_SPI_U_BOOT_OFFS	(64 * 1024)
#define CONFIG_SPL_SPI_LOAD

/* Display */
#define CONFIG_VIDEO_IPUV3
#define CONFIG_IMX_HDMI

#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_SOURCE
#define CONFIG_VIDEO_BMP_RLE8

#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO

/* EEPROM */
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
#define CONFIG_SYS_EEPROM_SIZE			256

#endif	/* __CONFIG_CM_FX6_H */
Commit	Line	Data
e32028a7 NK	1	/*
	2	* Config file for Compulab CM-FX6 board
	3	*
	4	* Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
	5	*
	6	* Author: Nikita Kiryanov <nikita@compulab.co.il>
	7	*
	8	* SPDX-License-Identifier: GPL-2.0+
	9	*/
	10
	11	#ifndef __CONFIG_CM_FX6_H
	12	#define __CONFIG_CM_FX6_H
	13
e32028a7 NK	14	#include "mx6_common.h"
e32028a7 NK	15
3ef5f671 CS	16	#ifndef CONFIG_SPL_BUILD
	17	#include <config_distro_defaults.h>
	18	#endif
	19
e32028a7	20	/* Machine config */
e32028a7 NK	21	#define CONFIG_SYS_LITTLE_ENDIAN
e32028a7 NK	22	#define CONFIG_MACH_TYPE 4273
e32028a7	23
e32028a7	24	/* MMC */
e32028a7 NK	25	#define CONFIG_SYS_FSL_USDHC_NUM 3
	26	#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
	27
	28	/* RAM */
	29	#define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR
	30	#define PHYS_SDRAM_2 MMDC1_ARB_BASE_ADDR
	31	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	32	#define CONFIG_NR_DRAM_BANKS 2
	33	#define CONFIG_SYS_MEMTEST_START 0x10000000
	34	#define CONFIG_SYS_MEMTEST_END 0x10010000
	35	#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
	36	#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
	37	#define CONFIG_SYS_INIT_SP_OFFSET \
	38	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	39	#define CONFIG_SYS_INIT_SP_ADDR \
	40	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
	41
	42	/* Serial console */
	43	#define CONFIG_MXC_UART
	44	#define CONFIG_MXC_UART_BASE UART4_BASE
e32028a7 NK	45	#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
e32028a7 NK	46
e32028a7	47	/* SPI flash */
e32028a7 NK	48	#define CONFIG_SF_DEFAULT_BUS 0
	49	#define CONFIG_SF_DEFAULT_CS 0
	50	#define CONFIG_SF_DEFAULT_SPEED 25000000
	51	#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
	52
63a93093 CS	53	/* MTD support */
63a93093 CS	54	#ifndef CONFIG_SPL_BUILD
63a93093 CS	55	#define CONFIG_MTD_DEVICE
	56	#define CONFIG_MTD_PARTITIONS
	57	#define CONFIG_SPI_FLASH_MTD
	58	#endif
	59
e32028a7	60	/* Environment */
e32028a7 NK	61	#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
	62	#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
	63	#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
	64	#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
	65	#define CONFIG_ENV_SECT_SIZE (64 * 1024)
	66	#define CONFIG_ENV_SIZE (8 * 1024)
	67	#define CONFIG_ENV_OFFSET (768 * 1024)
	68
3ef5f671	69	#ifndef CONFIG_SPL_BUILD
e32028a7	70	#define CONFIG_EXTRA_ENV_SETTINGS \
6b79f71c CS	71	"fdt_high=0xffffffff\0" \
	72	"initrd_high=0xffffffff\0" \
	73	"fdt_addr_r=0x18000000\0" \
	74	"ramdisk_addr_r=0x13000000\0" \
	75	"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
	76	"pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
	77	"scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
1c2e5292	78	"stdin=serial,usbkbd\0" \
deb94d61 NK	79	"stdout=serial,vga\0" \
	80	"stderr=serial,vga\0" \
	81	"panel=HDMI\0" \
e32028a7	82	"autoload=no\0" \
f0f6724f CS	83	"uImage=uImage-cm-fx6\0" \
f0f6724f CS	84	"zImage=zImage-cm-fx6\0" \
508a6ede	85	"kernel=uImage-cm-fx6\0" \
508a6ede	86	"dtb=cm-fx6.dtb\0" \
e32028a7 NK	87	"console=ttymxc3,115200\0" \
e32028a7 NK	88	"ethprime=FEC0\0" \
e32028a7 NK	89	"video_hdmi=mxcfb0:dev=hdmi,1920x1080M-32@50,if=RGB32\0" \
e32028a7 NK	90	"video_dvi=mxcfb0:dev=dvi,1280x800M-32@50,if=RGB32\0" \
6b79f71c	91	"doboot=bootm ${kernel_addr_r}\0" \
508a6ede	92	"doloadfdt=false\0" \
43ede0bc TR	93	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
43ede0bc TR	94	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
f0f6724f	95	"setboottypez=setenv kernel ${zImage};" \
6b79f71c	96	"setenv doboot bootz ${kernel_addr_r} - ${fdt_addr_r};" \
508a6ede	97	"setenv doloadfdt true;\0" \
f0f6724f	98	"setboottypem=setenv kernel ${uImage};" \
6b79f71c	99	"setenv doboot bootm ${kernel_addr_r};" \
508a6ede	100	"setenv doloadfdt false;\0"\
e32028a7	101	"mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
206f38f7	102	"sataroot=/dev/sda2 rw rootwait\0" \
a6b0652b NK	103	"nandroot=/dev/mtdblock4 rw\0" \
a6b0652b NK	104	"nandrootfstype=ubifs\0" \
508a6ede	105	"mmcargs=setenv bootargs console=${console} root=${mmcroot} " \
f0f6724f	106	"${video} ${extrabootargs}\0" \
508a6ede	107	"sataargs=setenv bootargs console=${console} root=${sataroot} " \
f0f6724f	108	"${video} ${extrabootargs}\0" \
a6b0652b NK	109	"nandargs=setenv bootargs console=${console} " \
	110	"root=${nandroot} " \
	111	"rootfstype=${nandrootfstype} " \
f0f6724f	112	"${video} ${extrabootargs}\0" \
508a6ede	113	"nandboot=if run nandloadkernel; then " \
a6b0652b	114	"run nandloadfdt;" \
508a6ede NK	115	"run setboottypem;" \
	116	"run storagebootcmd;" \
	117	"run setboottypez;" \
	118	"run storagebootcmd;" \
	119	"fi;\0" \
	120	"run_eboot=echo Starting EBOOT ...; "\
	121	"mmc dev 2 && " \
	122	"mmc rescan && mmc read 10042000 a 400 && go 10042000\0" \
6b79f71c CS	123	"loadkernel=load ${storagetype} ${storagedev} ${kernel_addr_r} ${kernel};\0"\
6b79f71c CS	124	"loadfdt=load ${storagetype} ${storagedev} ${fdt_addr_r} ${dtb};\0" \
6b79f71c CS	125	"nandloadkernel=nand read ${kernel_addr_r} 0 780000;\0" \
6b79f71c CS	126	"nandloadfdt=nand read ${fdt_addr_r} 780000 80000;\0" \
508a6ede NK	127	"setupmmcboot=setenv storagetype mmc; setenv storagedev 2;\0" \
	128	"setupsataboot=setenv storagetype sata; setenv storagedev 0;\0" \
	129	"setupnandboot=setenv storagetype nand;\0" \
508a6ede NK	130	"storagebootcmd=echo Booting from ${storagetype} ...;" \
	131	"run ${storagetype}args; run doboot;\0" \
	132	"trybootk=if run loadkernel; then " \
	133	"if ${doloadfdt}; then " \
	134	"run loadfdt;" \
a6b0652b	135	"fi;" \
508a6ede NK	136	"run storagebootcmd;" \
508a6ede NK	137	"fi;\0" \
5a6440ca	138	"trybootsmz=" \
508a6ede NK	139	"run setboottypem;" \
	140	"run trybootk;" \
	141	"run setboottypez;" \
3ef5f671 CS	142	"run trybootk;\0" \
	143	"legacy_bootcmd=" \
	144	"run setupmmcboot;" \
	145	"mmc dev ${storagedev};" \
	146	"if mmc rescan; then " \
	147	"run trybootsmz;" \
508a6ede	148	"fi;" \
3ef5f671 CS	149	"run setupsataboot;" \
	150	"if sata init; then " \
	151	"run trybootsmz;" \
	152	"fi;" \
	153	"run setupnandboot;" \
	154	"run nandboot;\0" \
	155	BOOTENV
e32028a7	156
63a93093	157	#define CONFIG_PREBOOT "usb start;sf probe"
1c2e5292	158
3ef5f671 CS	159	#define BOOT_TARGET_DEVICES(func) \
	160	func(USB, usb, 0) \
	161	func(MMC, mmc, 2) \
	162	func(SATA, sata, 0)
	163
	164	#include <config_distro_bootcmd.h>
	165	#else
	166	#define CONFIG_EXTRA_ENV_SETTINGS
	167	#endif
	168
e32028a7 NK	169	/* SPI */
	170	#define CONFIG_SPI
	171	#define CONFIG_MXC_SPI
e32028a7	172
a6b0652b NK	173	/* NAND */
a6b0652b NK	174	#ifndef CONFIG_SPL_BUILD
a6b0652b NK	175	#define CONFIG_SYS_NAND_BASE 0x40000000
	176	#define CONFIG_SYS_NAND_MAX_CHIPS 1
	177	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	178	#define CONFIG_NAND_MXS
	179	#define CONFIG_SYS_NAND_ONFI_DETECTION
	180	/* APBH DMA is required for NAND support */
	181	#define CONFIG_APBH_DMA
	182	#define CONFIG_APBH_DMA_BURST
	183	#define CONFIG_APBH_DMA_BURST8
	184	#endif
	185
02b1343e NK	186	/* Ethernet */
	187	#define CONFIG_FEC_MXC
	188	#define CONFIG_FEC_MXC_PHYADDR 0
	189	#define CONFIG_FEC_XCV_TYPE RGMII
	190	#define IMX_FEC_BASE ENET_BASE_ADDR
02b1343e NK	191	#define CONFIG_PHY_ATHEROS
	192	#define CONFIG_MII
	193	#define CONFIG_ETHPRIME "FEC0"
	194	#define CONFIG_ARP_TIMEOUT 200UL
02b1343e NK	195	#define CONFIG_NET_RETRY_COUNT 5
02b1343e NK	196
0f3effb9	197	/* USB */
0f3effb9 NK	198	#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI \| PORT_PTS_PTW)
	199	#define CONFIG_MXC_USB_FLAGS 0
	200	#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
	201	#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
	202
f42b2f60	203	/* I2C */
f42b2f60 NK	204	#define CONFIG_SYS_I2C
f42b2f60 NK	205	#define CONFIG_SYS_I2C_MXC
03544c66 AA	206	#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
03544c66 AA	207	#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
f8cb101e	208	#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
f42b2f60 NK	209	#define CONFIG_SYS_I2C_SPEED 100000
	210	#define CONFIG_SYS_MXC_I2C3_SPEED 400000
	211
	212	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
	213	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	214	#define CONFIG_SYS_I2C_EEPROM_BUS 2
	215
206f38f7	216	/* SATA */
206f38f7	217	#define CONFIG_SYS_SATA_MAX_DEVICE 1
206f38f7	218	#define CONFIG_LBA48
206f38f7 NK	219	#define CONFIG_DWC_AHSATA_PORT_ID 0
	220	#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
	221
e32028a7	222	/* Boot */
e32028a7	223	#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
f66113c0	224	#define CONFIG_SERIAL_TAG
e32028a7 NK	225
e32028a7 NK	226	/* misc */
9fbdcf01	227	#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
7d1abb7d	228	#define CONFIG_MISC_INIT_R
e32028a7 NK	229
	230	/* SPL */
	231	#include "imx6_spl.h"
e32028a7 NK	232	#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024)
	233	#define CONFIG_SPL_SPI_LOAD
	234
deb94d61	235	/* Display */
deb94d61	236	#define CONFIG_VIDEO_IPUV3
deb94d61	237	#define CONFIG_IMX_HDMI
deb94d61	238
3a236a35	239	#define CONFIG_SPLASH_SCREEN
f82eb2fa	240	#define CONFIG_SPLASH_SOURCE
3a236a35 NK	241	#define CONFIG_VIDEO_BMP_RLE8
3a236a35 NK	242
8015dde8 NK	243	#define CONFIG_VIDEO_LOGO
	244	#define CONFIG_VIDEO_BMP_LOGO
	245
12616531	246	/* EEPROM */
12616531 NK	247	#define CONFIG_ENV_EEPROM_IS_ON_I2C
	248	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	249	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
	250	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
	251	#define CONFIG_SYS_EEPROM_SIZE 256
	252
e32028a7	253	#endif /* __CONFIG_CM_FX6_H */