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36b4e2dd | 1 | /* |
9fc376be | 2 | * (C) Copyright 2011 CompuLab, Ltd. |
36b4e2dd | 3 | * Mike Rapoport <mike@compulab.co.il> |
dccd9a0b | 4 | * Igor Grinberg <grinberg@compulab.co.il> |
36b4e2dd MR |
5 | * |
6 | * Based on omap3_beagle.h | |
7 | * (C) Copyright 2006-2008 | |
8 | * Texas Instruments. | |
9 | * Richard Woodruff <r-woodruff2@ti.com> | |
10 | * Syed Mohammed Khasim <x0khasim@ti.com> | |
11 | * | |
b65a77a8 | 12 | * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards |
36b4e2dd | 13 | * |
1a459660 | 14 | * SPDX-License-Identifier: GPL-2.0+ |
36b4e2dd MR |
15 | */ |
16 | ||
17 | #ifndef __CONFIG_H | |
18 | #define __CONFIG_H | |
19 | ||
3709844f AA |
20 | #define CONFIG_SYS_CACHELINE_SIZE 64 |
21 | ||
36b4e2dd MR |
22 | /* |
23 | * High Level Configuration Options | |
24 | */ | |
9fc376be | 25 | #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */ |
36b4e2dd | 26 | |
36b4e2dd MR |
27 | #define CONFIG_SDRC /* The chip has SDRC controller */ |
28 | ||
29 | #include <asm/arch/cpu.h> /* get chip and board defs */ | |
987ec585 | 30 | #include <asm/arch/omap.h> |
36b4e2dd | 31 | |
36b4e2dd MR |
32 | /* Clock Defines */ |
33 | #define V_OSCK 26000000 /* Clock output from T2 */ | |
34 | #define V_SCLK (V_OSCK >> 1) | |
35 | ||
36b4e2dd MR |
36 | #define CONFIG_MISC_INIT_R |
37 | ||
9fc376be NK |
38 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
39 | #define CONFIG_SETUP_MEMORY_TAGS | |
40 | #define CONFIG_INITRD_TAG | |
41 | #define CONFIG_REVISION_TAG | |
82309250 | 42 | #define CONFIG_SERIAL_TAG |
36b4e2dd MR |
43 | |
44 | /* | |
45 | * Size of malloc() pool | |
46 | */ | |
390cdcda | 47 | #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ |
9fc376be NK |
48 | /* Sector */ |
49 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) | |
36b4e2dd MR |
50 | |
51 | /* | |
52 | * Hardware drivers | |
53 | */ | |
54 | ||
55 | /* | |
56 | * NS16550 Configuration | |
57 | */ | |
58 | #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ | |
59 | ||
36b4e2dd MR |
60 | #define CONFIG_SYS_NS16550_SERIAL |
61 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) | |
62 | #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK | |
63 | ||
64 | /* | |
65 | * select serial console configuration | |
66 | */ | |
67 | #define CONFIG_CONS_INDEX 3 | |
68 | #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 | |
69 | #define CONFIG_SERIAL3 3 /* UART3 */ | |
70 | ||
71 | /* allow to overwrite serial and ethaddr */ | |
72 | #define CONFIG_ENV_OVERWRITE | |
36b4e2dd MR |
73 | #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ |
74 | 115200} | |
9fc376be | 75 | |
36b4e2dd | 76 | /* USB */ |
9fc376be | 77 | #define CONFIG_USB_OMAP3 |
95de1e2f | 78 | #define CONFIG_USB_MUSB_UDC |
9fc376be | 79 | #define CONFIG_TWL4030_USB |
36b4e2dd MR |
80 | |
81 | /* USB device configuration */ | |
9fc376be NK |
82 | #define CONFIG_USB_DEVICE |
83 | #define CONFIG_USB_TTY | |
36b4e2dd MR |
84 | |
85 | /* commands to include */ | |
36b4e2dd MR |
86 | #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ |
87 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ | |
0b800a6b | 88 | #define CONFIG_MTD_PARTITIONS |
9fc376be NK |
89 | #define MTDIDS_DEFAULT "nand0=nand" |
90 | #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ | |
0b800a6b | 91 | "1920k(u-boot),256k(u-boot-env),"\ |
9fc376be | 92 | "4m(kernel),-(fs)" |
36b4e2dd | 93 | |
36b4e2dd | 94 | #define CONFIG_CMD_NAND /* NAND support */ |
36b4e2dd | 95 | |
6789e84e HS |
96 | #define CONFIG_SYS_I2C |
97 | #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 | |
98 | #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 | |
99 | #define CONFIG_SYS_I2C_OMAP34XX | |
82309250 NK |
100 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 |
101 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
52658fda | 102 | #define CONFIG_SYS_I2C_EEPROM_BUS 0 |
79874ae9 | 103 | #define CONFIG_I2C_MULTI_BUS |
36b4e2dd MR |
104 | |
105 | /* | |
106 | * TWL4030 | |
107 | */ | |
9fc376be | 108 | #define CONFIG_TWL4030_LED |
36b4e2dd MR |
109 | |
110 | /* | |
111 | * Board NAND Info. | |
112 | */ | |
36b4e2dd MR |
113 | #define CONFIG_NAND_OMAP_GPMC |
114 | #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ | |
115 | /* to access nand */ | |
116 | #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ | |
117 | /* to access nand at */ | |
118 | /* CS0 */ | |
36b4e2dd MR |
119 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ |
120 | /* devices */ | |
7bb6e29b | 121 | |
36b4e2dd | 122 | /* Environment information */ |
36b4e2dd MR |
123 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
124 | "loadaddr=0x82000000\0" \ | |
125 | "usbtty=cdc_acm\0" \ | |
f3ef3609 | 126 | "console=ttyO2,115200n8\0" \ |
36b4e2dd MR |
127 | "mpurate=500\0" \ |
128 | "vram=12M\0" \ | |
129 | "dvimode=1024x768MR-16@60\0" \ | |
130 | "defaultdisplay=dvi\0" \ | |
131 | "mmcdev=0\0" \ | |
132 | "mmcroot=/dev/mmcblk0p2 rw\0" \ | |
0b800a6b | 133 | "mmcrootfstype=ext4 rootwait\0" \ |
36b4e2dd | 134 | "nandroot=/dev/mtdblock4 rw\0" \ |
0b800a6b | 135 | "nandrootfstype=ubifs\0" \ |
36b4e2dd MR |
136 | "mmcargs=setenv bootargs console=${console} " \ |
137 | "mpurate=${mpurate} " \ | |
138 | "vram=${vram} " \ | |
139 | "omapfb.mode=dvi:${dvimode} " \ | |
36b4e2dd MR |
140 | "omapdss.def_disp=${defaultdisplay} " \ |
141 | "root=${mmcroot} " \ | |
142 | "rootfstype=${mmcrootfstype}\0" \ | |
143 | "nandargs=setenv bootargs console=${console} " \ | |
144 | "mpurate=${mpurate} " \ | |
145 | "vram=${vram} " \ | |
146 | "omapfb.mode=dvi:${dvimode} " \ | |
36b4e2dd MR |
147 | "omapdss.def_disp=${defaultdisplay} " \ |
148 | "root=${nandroot} " \ | |
149 | "rootfstype=${nandrootfstype}\0" \ | |
150 | "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ | |
151 | "bootscript=echo Running bootscript from mmc ...; " \ | |
152 | "source ${loadaddr}\0" \ | |
153 | "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ | |
154 | "mmcboot=echo Booting from mmc ...; " \ | |
155 | "run mmcargs; " \ | |
156 | "bootm ${loadaddr}\0" \ | |
157 | "nandboot=echo Booting from nand ...; " \ | |
158 | "run nandargs; " \ | |
0b800a6b | 159 | "nand read ${loadaddr} 2a0000 400000; " \ |
36b4e2dd MR |
160 | "bootm ${loadaddr}\0" \ |
161 | ||
162 | #define CONFIG_BOOTCOMMAND \ | |
66968110 | 163 | "mmc dev ${mmcdev}; if mmc rescan; then " \ |
36b4e2dd MR |
164 | "if run loadbootscript; then " \ |
165 | "run bootscript; " \ | |
166 | "else " \ | |
167 | "if run loaduimage; then " \ | |
168 | "run mmcboot; " \ | |
169 | "else run nandboot; " \ | |
170 | "fi; " \ | |
171 | "fi; " \ | |
172 | "else run nandboot; fi" | |
173 | ||
36b4e2dd MR |
174 | /* |
175 | * Miscellaneous configurable options | |
176 | */ | |
41d7e702 IG |
177 | #define CONFIG_AUTO_COMPLETE |
178 | #define CONFIG_CMDLINE_EDITING | |
179 | #define CONFIG_TIMESTAMP | |
9fc376be | 180 | #define CONFIG_SYS_AUTOLOAD "no" |
36b4e2dd | 181 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
36b4e2dd MR |
182 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
183 | /* Print Buffer Size */ | |
184 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
185 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
186 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
187 | /* Boot Argument Buffer Size */ | |
188 | #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) | |
189 | ||
190 | #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ | |
191 | /* works on */ | |
192 | #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ | |
193 | 0x01F00000) /* 31MB */ | |
194 | ||
195 | #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ | |
196 | /* load address */ | |
197 | ||
198 | /* | |
199 | * OMAP3 has 12 GP timers, they can be driven by the system clock | |
200 | * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). | |
201 | * This rate is divided by a local divisor. | |
202 | */ | |
203 | #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) | |
204 | #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ | |
36b4e2dd | 205 | |
36b4e2dd MR |
206 | /*----------------------------------------------------------------------- |
207 | * Physical Memory Map | |
208 | */ | |
209 | #define CONFIG_NR_DRAM_BANKS 1 /* CS1 is never populated */ | |
210 | #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 | |
36b4e2dd | 211 | |
36b4e2dd MR |
212 | /*----------------------------------------------------------------------- |
213 | * FLASH and environment organization | |
214 | */ | |
215 | ||
216 | /* **** PISMO SUPPORT *** */ | |
36b4e2dd MR |
217 | /* Monitor at start of flash */ |
218 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
3530a35d | 219 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ |
36b4e2dd | 220 | |
9fc376be | 221 | #define CONFIG_ENV_IS_IN_NAND |
36b4e2dd | 222 | #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ |
6cbec7b3 | 223 | #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET |
36b4e2dd MR |
224 | #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET |
225 | ||
36b4e2dd | 226 | #if defined(CONFIG_CMD_NET) |
36b4e2dd MR |
227 | #define CONFIG_SMC911X |
228 | #define CONFIG_SMC911X_32_BIT | |
b65a77a8 IG |
229 | #define CM_T3X_SMC911X_BASE 0x2C000000 |
230 | #define SB_T35_SMC911X_BASE (CM_T3X_SMC911X_BASE + (16 << 20)) | |
231 | #define CONFIG_SMC911X_BASE CM_T3X_SMC911X_BASE | |
36b4e2dd MR |
232 | #endif /* (CONFIG_CMD_NET) */ |
233 | ||
234 | /* additions for new relocation code, must be added to all boards */ | |
235 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 | |
236 | #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 | |
237 | #define CONFIG_SYS_INIT_RAM_SIZE 0x800 | |
238 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ | |
239 | CONFIG_SYS_INIT_RAM_SIZE - \ | |
240 | GENERATED_GBL_DATA_SIZE) | |
241 | ||
2b8754b2 | 242 | /* Status LED */ |
ebc18afd | 243 | #define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */ |
2b8754b2 | 244 | |
60e6bdcc NK |
245 | #define CONFIG_SPLASHIMAGE_GUARD |
246 | ||
7878ca51 | 247 | /* Display Configuration */ |
7878ca51 NK |
248 | #define CONFIG_VIDEO_OMAP3 |
249 | #define LCD_BPP LCD_COLOR16 | |
250 | ||
f35034fe | 251 | #define CONFIG_SPLASH_SCREEN |
f82eb2fa | 252 | #define CONFIG_SPLASH_SOURCE |
f35034fe | 253 | #define CONFIG_BMP_16BPP |
63c4f17b NK |
254 | #define CONFIG_SCF0403_LCD |
255 | ||
256 | #define CONFIG_OMAP3_SPI | |
7878ca51 | 257 | |
3e51b7c8 | 258 | /* Defines for SPL */ |
3e51b7c8 SR |
259 | #define CONFIG_SPL_FRAMEWORK |
260 | #define CONFIG_SPL_NAND_SIMPLE | |
261 | ||
e2ccdf89 | 262 | #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 |
205b4f33 | 263 | #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" |
3e51b7c8 | 264 | |
3e51b7c8 SR |
265 | #define CONFIG_SPL_NAND_BASE |
266 | #define CONFIG_SPL_NAND_DRIVERS | |
267 | #define CONFIG_SPL_NAND_ECC | |
3e51b7c8 | 268 | #define CONFIG_SPL_OMAP3_ID_NAND |
983e3700 | 269 | #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" |
3e51b7c8 SR |
270 | |
271 | /* NAND boot config */ | |
272 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE | |
273 | #define CONFIG_SYS_NAND_PAGE_COUNT 64 | |
274 | #define CONFIG_SYS_NAND_PAGE_SIZE 2048 | |
275 | #define CONFIG_SYS_NAND_OOBSIZE 64 | |
276 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
277 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS | |
278 | /* | |
279 | * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: | |
280 | * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT | |
281 | */ | |
282 | #define CONFIG_SYS_NAND_ECCPOS { 1, 2, 3, 4, 5, 6, 7, 8, 9, \ | |
283 | 10, 11, 12 } | |
284 | #define CONFIG_SYS_NAND_ECCSIZE 512 | |
285 | #define CONFIG_SYS_NAND_ECCBYTES 3 | |
286 | #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW | |
287 | ||
288 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE | |
289 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 | |
290 | ||
291 | #define CONFIG_SPL_TEXT_BASE 0x40200800 | |
fa2f81b0 TR |
292 | #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ |
293 | CONFIG_SPL_TEXT_BASE) | |
3e51b7c8 SR |
294 | |
295 | /* | |
296 | * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the | |
297 | * older x-loader implementations. And move the BSS area so that it | |
298 | * doesn't overlap with TEXT_BASE. | |
299 | */ | |
300 | #define CONFIG_SYS_TEXT_BASE 0x80008000 | |
301 | #define CONFIG_SPL_BSS_START_ADDR 0x80100000 | |
302 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ | |
303 | ||
304 | #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 | |
305 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 | |
306 | ||
bcb447e1 NK |
307 | /* EEPROM */ |
308 | #define CONFIG_CMD_EEPROM | |
309 | #define CONFIG_ENV_EEPROM_IS_ON_I2C | |
310 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
311 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 | |
312 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 | |
313 | #define CONFIG_SYS_EEPROM_SIZE 256 | |
314 | ||
315 | #define CONFIG_CMD_EEPROM_LAYOUT | |
316 | #define CONFIG_EEPROM_LAYOUT_HELP_STRING "legacy, v1, v2, v3" | |
317 | ||
36b4e2dd | 318 | #endif /* __CONFIG_H */ |