[people/ms/u-boot.git] / include / configs / cm_t35.h

/*
 * (C) Copyright 2011 CompuLab, Ltd.
 * Mike Rapoport <mike@compulab.co.il>
 * Igor Grinberg <grinberg@compulab.co.il>
 *
 * Based on omap3_beagle.h
 * (C) Copyright 2006-2008
 * Texas Instruments.
 * Richard Woodruff <r-woodruff2@ti.com>
 * Syed Mohammed Khasim <x0khasim@ti.com>
 *
 * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_SYS_CACHELINE_SIZE	64

/*
 * High Level Configuration Options
 */
#define CONFIG_OMAP	/* in a TI OMAP core */
#define CONFIG_OMAP_GPIO
#define CONFIG_CM_T3X	/* working with CM-T35 and CM-T3730 */
#define CONFIG_OMAP_COMMON
/* Common ARM Erratas */
#define CONFIG_ARM_ERRATA_454179
#define CONFIG_ARM_ERRATA_430973
#define CONFIG_ARM_ERRATA_621766

#define CONFIG_SDRC	/* The chip has SDRC controller */

#include <asm/arch/cpu.h>		/* get chip and board defs */
#include <asm/arch/omap.h>

/* Clock Defines */
#define V_OSCK			26000000	/* Clock output from T2 */
#define V_SCLK			(V_OSCK >> 1)

#define CONFIG_MISC_INIT_R

#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
#define CONFIG_SERIAL_TAG

/*
 * Size of malloc() pool
 */
#define CONFIG_ENV_SIZE		(16 << 10)	/* 16 KiB */
					/* Sector */
#define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + (128 << 10))

/*
 * Hardware drivers
 */

/*
 * NS16550 Configuration
 */
#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */

#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK

/*
 * select serial console configuration
 */
#define CONFIG_CONS_INDEX		3
#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
#define CONFIG_SERIAL3			3	/* UART3 */

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
					115200}

#define CONFIG_GENERIC_MMC
#define CONFIG_MMC
#define CONFIG_OMAP_HSMMC
#define CONFIG_DOS_PARTITION

/* USB */
#define CONFIG_USB_OMAP3
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_OMAP
#define CONFIG_USB_MUSB_UDC
#define CONFIG_TWL4030_USB

/* USB device configuration */
#define CONFIG_USB_DEVICE
#define CONFIG_USB_TTY
#define CONFIG_SYS_CONSOLE_IS_IN_ENV

/* commands to include */
#define CONFIG_CMD_MTDPARTS	/* Enable MTD parts commands */
#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
#define CONFIG_MTD_PARTITIONS
#define MTDIDS_DEFAULT		"nand0=nand"
#define MTDPARTS_DEFAULT	"mtdparts=nand:512k(x-loader),"\
				"1920k(u-boot),256k(u-boot-env),"\
				"4m(kernel),-(fs)"

#define CONFIG_CMD_NAND		/* NAND support			*/

#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_I2C
#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
#define CONFIG_SYS_I2C_OMAP34XX
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
#define CONFIG_SYS_I2C_EEPROM_BUS	0
#define CONFIG_I2C_MULTI_BUS

/*
 * TWL4030
 */
#define CONFIG_TWL4030_POWER
#define CONFIG_TWL4030_LED

/*
 * Board NAND Info.
 */
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
							/* to access nand */
#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
							/* to access nand at */
							/* CS0 */
#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
							/* devices */

/* Environment information */
#define CONFIG_EXTRA_ENV_SETTINGS \
	"loadaddr=0x82000000\0" \
	"usbtty=cdc_acm\0" \
	"console=ttyO2,115200n8\0" \
	"mpurate=500\0" \
	"vram=12M\0" \
	"dvimode=1024x768MR-16@60\0" \
	"defaultdisplay=dvi\0" \
	"mmcdev=0\0" \
	"mmcroot=/dev/mmcblk0p2 rw\0" \
	"mmcrootfstype=ext4 rootwait\0" \
	"nandroot=/dev/mtdblock4 rw\0" \
	"nandrootfstype=ubifs\0" \
	"mmcargs=setenv bootargs console=${console} " \
		"mpurate=${mpurate} " \
		"vram=${vram} " \
		"omapfb.mode=dvi:${dvimode} " \
		"omapdss.def_disp=${defaultdisplay} " \
		"root=${mmcroot} " \
		"rootfstype=${mmcrootfstype}\0" \
	"nandargs=setenv bootargs console=${console} " \
		"mpurate=${mpurate} " \
		"vram=${vram} " \
		"omapfb.mode=dvi:${dvimode} " \
		"omapdss.def_disp=${defaultdisplay} " \
		"root=${nandroot} " \
		"rootfstype=${nandrootfstype}\0" \
	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
	"bootscript=echo Running bootscript from mmc ...; " \
		"source ${loadaddr}\0" \
	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
	"mmcboot=echo Booting from mmc ...; " \
		"run mmcargs; " \
		"bootm ${loadaddr}\0" \
	"nandboot=echo Booting from nand ...; " \
		"run nandargs; " \
		"nand read ${loadaddr} 2a0000 400000; " \
		"bootm ${loadaddr}\0" \

#define CONFIG_BOOTCOMMAND \
	"mmc dev ${mmcdev}; if mmc rescan; then " \
		"if run loadbootscript; then " \
			"run bootscript; " \
		"else " \
			"if run loaduimage; then " \
				"run mmcboot; " \
			"else run nandboot; " \
			"fi; " \
		"fi; " \
	"else run nandboot; fi"

/*
 * Miscellaneous configurable options
 */
#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
#define CONFIG_TIMESTAMP
#define CONFIG_SYS_AUTOLOAD		"no"
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)

#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)	/* memtest */
								/* works on */
#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
					0x01F00000) /* 31MB */

#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)	/* default */
							/* load address */

/*
 * OMAP3 has 12 GP timers, they can be driven by the system clock
 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 * This rate is divided by a local divisor.
 */
#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
#define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	1	/* CS1 is never populated */
#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */

/* **** PISMO SUPPORT *** */
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */

#define CONFIG_ENV_IS_IN_NAND
#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET

#if defined(CONFIG_CMD_NET)
#define CONFIG_SMC911X
#define CONFIG_SMC911X_32_BIT
#define CM_T3X_SMC911X_BASE	0x2C000000
#define SB_T35_SMC911X_BASE	(CM_T3X_SMC911X_BASE + (16 << 20))
#define CONFIG_SMC911X_BASE	CM_T3X_SMC911X_BASE
#endif /* (CONFIG_CMD_NET) */

/* additions for new relocation code, must be added to all boards */
#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE	0x800
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR +	\
					 CONFIG_SYS_INIT_RAM_SIZE -	\
					 GENERATED_GBL_DATA_SIZE)

/* Status LED */
#define CONFIG_STATUS_LED		/* Status LED enabled */
#define CONFIG_BOARD_SPECIFIC_LED
#define CONFIG_GPIO_LED
#define GREEN_LED_GPIO			186 /* CM-T35 Green LED is GPIO186 */
#define GREEN_LED_DEV			0
#define STATUS_LED_BIT			GREEN_LED_GPIO
#define STATUS_LED_STATE		STATUS_LED_ON
#define STATUS_LED_PERIOD		(CONFIG_SYS_HZ / 2)
#define STATUS_LED_BOOT			GREEN_LED_DEV

#define CONFIG_SPLASHIMAGE_GUARD

/* GPIO banks */
#ifdef CONFIG_STATUS_LED
#define CONFIG_OMAP3_GPIO_6	/* GPIO186 is in GPIO bank 6  */
#endif

/* Display Configuration */
#define CONFIG_OMAP3_GPIO_2
#define CONFIG_OMAP3_GPIO_5
#define CONFIG_VIDEO_OMAP3
#define LCD_BPP		LCD_COLOR16

#define CONFIG_LCD
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_SOURCE
#define CONFIG_CMD_BMP
#define CONFIG_BMP_16BPP
#define CONFIG_SCF0403_LCD

#define CONFIG_OMAP3_SPI

/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_NAND_SIMPLE

#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"

#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
#define CONFIG_SPL_OMAP3_ID_NAND
#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"

/* NAND boot config */
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT	64
#define CONFIG_SYS_NAND_PAGE_SIZE	2048
#define CONFIG_SYS_NAND_OOBSIZE		64
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
/*
 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
 */
#define CONFIG_SYS_NAND_ECCPOS		{ 1, 2, 3, 4, 5, 6, 7, 8, 9, \
					 10, 11, 12 }
#define CONFIG_SYS_NAND_ECCSIZE		512
#define CONFIG_SYS_NAND_ECCBYTES	3
#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW

#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000

#define CONFIG_SPL_TEXT_BASE		0x40200800
#define CONFIG_SPL_MAX_SIZE		(SRAM_SCRATCH_SPACE_ADDR - \
					 CONFIG_SPL_TEXT_BASE)

/*
 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
 * older x-loader implementations. And move the BSS area so that it
 * doesn't overlap with TEXT_BASE.
 */
#define CONFIG_SYS_TEXT_BASE		0x80008000
#define CONFIG_SPL_BSS_START_ADDR	0x80100000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */

#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000

/* EEPROM */
#define CONFIG_CMD_EEPROM
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
#define CONFIG_SYS_EEPROM_SIZE			256

#define CONFIG_CMD_EEPROM_LAYOUT
#define CONFIG_EEPROM_LAYOUT_HELP_STRING "legacy, v1, v2, v3"

#endif /* __CONFIG_H */
Commit	Line	Data
36b4e2dd	1	/*
9fc376be	2	* (C) Copyright 2011 CompuLab, Ltd.
36b4e2dd	3	* Mike Rapoport <mike@compulab.co.il>
dccd9a0b	4	* Igor Grinberg <grinberg@compulab.co.il>
36b4e2dd MR	5	*
	6	* Based on omap3_beagle.h
	7	* (C) Copyright 2006-2008
	8	* Texas Instruments.
	9	* Richard Woodruff <r-woodruff2@ti.com>
	10	* Syed Mohammed Khasim <x0khasim@ti.com>
	11	*
b65a77a8	12	* Configuration settings for the CompuLab CM-T35 and CM-T3730 boards
36b4e2dd	13	*
1a459660	14	* SPDX-License-Identifier: GPL-2.0+
36b4e2dd MR	15	*/
	16
	17	#ifndef __CONFIG_H
	18	#define __CONFIG_H
	19
3709844f AA	20	#define CONFIG_SYS_CACHELINE_SIZE 64
3709844f AA	21
36b4e2dd MR	22	/*
	23	* High Level Configuration Options
	24	*/
9fc376be	25	#define CONFIG_OMAP /* in a TI OMAP core */
308252ad	26	#define CONFIG_OMAP_GPIO
9fc376be	27	#define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */
806d2792	28	#define CONFIG_OMAP_COMMON
c6f90e14 NM	29	/* Common ARM Erratas */
	30	#define CONFIG_ARM_ERRATA_454179
	31	#define CONFIG_ARM_ERRATA_430973
	32	#define CONFIG_ARM_ERRATA_621766
36b4e2dd	33
36b4e2dd MR	34	#define CONFIG_SDRC /* The chip has SDRC controller */
	35
	36	#include <asm/arch/cpu.h> /* get chip and board defs */
987ec585	37	#include <asm/arch/omap.h>
36b4e2dd	38
36b4e2dd MR	39	/* Clock Defines */
	40	#define V_OSCK 26000000 /* Clock output from T2 */
	41	#define V_SCLK (V_OSCK >> 1)
	42
36b4e2dd MR	43	#define CONFIG_MISC_INIT_R
36b4e2dd MR	44
9fc376be NK	45	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	46	#define CONFIG_SETUP_MEMORY_TAGS
	47	#define CONFIG_INITRD_TAG
	48	#define CONFIG_REVISION_TAG
82309250	49	#define CONFIG_SERIAL_TAG
36b4e2dd MR	50
	51	/*
	52	* Size of malloc() pool
	53	*/
390cdcda	54	#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
9fc376be NK	55	/* Sector */
9fc376be NK	56	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
36b4e2dd MR	57
	58	/*
	59	* Hardware drivers
	60	*/
	61
	62	/*
	63	* NS16550 Configuration
	64	*/
	65	#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
	66
36b4e2dd MR	67	#define CONFIG_SYS_NS16550_SERIAL
	68	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	69	#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
	70
	71	/*
	72	* select serial console configuration
	73	*/
	74	#define CONFIG_CONS_INDEX 3
	75	#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
	76	#define CONFIG_SERIAL3 3 /* UART3 */
	77
	78	/* allow to overwrite serial and ethaddr */
	79	#define CONFIG_ENV_OVERWRITE
	80	#define CONFIG_BAUDRATE 115200
	81	#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
	82	115200}
9fc376be NK	83
	84	#define CONFIG_GENERIC_MMC
	85	#define CONFIG_MMC
	86	#define CONFIG_OMAP_HSMMC
	87	#define CONFIG_DOS_PARTITION
36b4e2dd	88
36b4e2dd	89	/* USB */
9fc376be	90	#define CONFIG_USB_OMAP3
854a7836 NK	91	#define CONFIG_USB_EHCI
854a7836 NK	92	#define CONFIG_USB_EHCI_OMAP
95de1e2f	93	#define CONFIG_USB_MUSB_UDC
9fc376be	94	#define CONFIG_TWL4030_USB
36b4e2dd MR	95
36b4e2dd MR	96	/* USB device configuration */
9fc376be NK	97	#define CONFIG_USB_DEVICE
	98	#define CONFIG_USB_TTY
	99	#define CONFIG_SYS_CONSOLE_IS_IN_ENV
36b4e2dd MR	100
36b4e2dd MR	101	/* commands to include */
36b4e2dd MR	102	#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
36b4e2dd MR	103	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
0b800a6b	104	#define CONFIG_MTD_PARTITIONS
9fc376be NK	105	#define MTDIDS_DEFAULT "nand0=nand"
9fc376be NK	106	#define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\
0b800a6b	107	"1920k(u-boot),256k(u-boot-env),"\
9fc376be	108	"4m(kernel),-(fs)"
36b4e2dd	109
36b4e2dd	110	#define CONFIG_CMD_NAND /* NAND support */
36b4e2dd	111
36b4e2dd	112	#define CONFIG_SYS_NO_FLASH
6789e84e HS	113	#define CONFIG_SYS_I2C
	114	#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
	115	#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
	116	#define CONFIG_SYS_I2C_OMAP34XX
82309250 NK	117	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
82309250 NK	118	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
52658fda	119	#define CONFIG_SYS_I2C_EEPROM_BUS 0
79874ae9	120	#define CONFIG_I2C_MULTI_BUS
36b4e2dd MR	121
	122	/*
	123	* TWL4030
	124	*/
9fc376be NK	125	#define CONFIG_TWL4030_POWER
9fc376be NK	126	#define CONFIG_TWL4030_LED
36b4e2dd MR	127
	128	/*
	129	* Board NAND Info.
	130	*/
36b4e2dd MR	131	#define CONFIG_NAND_OMAP_GPMC
	132	#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
	133	/* to access nand */
	134	#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
	135	/* to access nand at */
	136	/* CS0 */
36b4e2dd MR	137	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
36b4e2dd MR	138	/* devices */
7bb6e29b	139
36b4e2dd	140	/* Environment information */
36b4e2dd MR	141	#define CONFIG_EXTRA_ENV_SETTINGS \
	142	"loadaddr=0x82000000\0" \
	143	"usbtty=cdc_acm\0" \
f3ef3609	144	"console=ttyO2,115200n8\0" \
36b4e2dd MR	145	"mpurate=500\0" \
	146	"vram=12M\0" \
	147	"dvimode=1024x768MR-16@60\0" \
	148	"defaultdisplay=dvi\0" \
	149	"mmcdev=0\0" \
	150	"mmcroot=/dev/mmcblk0p2 rw\0" \
0b800a6b	151	"mmcrootfstype=ext4 rootwait\0" \
36b4e2dd	152	"nandroot=/dev/mtdblock4 rw\0" \
0b800a6b	153	"nandrootfstype=ubifs\0" \
36b4e2dd MR	154	"mmcargs=setenv bootargs console=${console} " \
	155	"mpurate=${mpurate} " \
	156	"vram=${vram} " \
	157	"omapfb.mode=dvi:${dvimode} " \
36b4e2dd MR	158	"omapdss.def_disp=${defaultdisplay} " \
	159	"root=${mmcroot} " \
	160	"rootfstype=${mmcrootfstype}\0" \
	161	"nandargs=setenv bootargs console=${console} " \
	162	"mpurate=${mpurate} " \
	163	"vram=${vram} " \
	164	"omapfb.mode=dvi:${dvimode} " \
36b4e2dd MR	165	"omapdss.def_disp=${defaultdisplay} " \
	166	"root=${nandroot} " \
	167	"rootfstype=${nandrootfstype}\0" \
	168	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
	169	"bootscript=echo Running bootscript from mmc ...; " \
	170	"source ${loadaddr}\0" \
	171	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
	172	"mmcboot=echo Booting from mmc ...; " \
	173	"run mmcargs; " \
	174	"bootm ${loadaddr}\0" \
	175	"nandboot=echo Booting from nand ...; " \
	176	"run nandargs; " \
0b800a6b	177	"nand read ${loadaddr} 2a0000 400000; " \
36b4e2dd MR	178	"bootm ${loadaddr}\0" \
	179
	180	#define CONFIG_BOOTCOMMAND \
66968110	181	"mmc dev ${mmcdev}; if mmc rescan; then " \
36b4e2dd MR	182	"if run loadbootscript; then " \
	183	"run bootscript; " \
	184	"else " \
	185	"if run loaduimage; then " \
	186	"run mmcboot; " \
	187	"else run nandboot; " \
	188	"fi; " \
	189	"fi; " \
	190	"else run nandboot; fi"
	191
36b4e2dd MR	192	/*
	193	* Miscellaneous configurable options
	194	*/
41d7e702 IG	195	#define CONFIG_AUTO_COMPLETE
	196	#define CONFIG_CMDLINE_EDITING
	197	#define CONFIG_TIMESTAMP
9fc376be	198	#define CONFIG_SYS_AUTOLOAD "no"
36b4e2dd	199	#define CONFIG_SYS_LONGHELP /* undef to save memory */
36b4e2dd MR	200	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	201	/* Print Buffer Size */
	202	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	203	sizeof(CONFIG_SYS_PROMPT) + 16)
	204	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	205	/* Boot Argument Buffer Size */
	206	#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
	207
	208	#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
	209	/* works on */
	210	#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
	211	0x01F00000) /* 31MB */
	212
	213	#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
	214	/* load address */
	215
	216	/*
	217	* OMAP3 has 12 GP timers, they can be driven by the system clock
	218	* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
	219	* This rate is divided by a local divisor.
	220	*/
	221	#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
	222	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
36b4e2dd	223
36b4e2dd MR	224	/*-----------------------------------------------------------------------
	225	* Physical Memory Map
	226	*/
	227	#define CONFIG_NR_DRAM_BANKS 1 /* CS1 is never populated */
	228	#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
36b4e2dd	229
36b4e2dd MR	230	/*-----------------------------------------------------------------------
	231	* FLASH and environment organization
	232	*/
	233
	234	/* ** PISMO SUPPORT * */
36b4e2dd MR	235	/* Monitor at start of flash */
36b4e2dd MR	236	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
3530a35d	237	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
36b4e2dd	238
9fc376be	239	#define CONFIG_ENV_IS_IN_NAND
36b4e2dd	240	#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
6cbec7b3	241	#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
36b4e2dd MR	242	#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
36b4e2dd MR	243
36b4e2dd	244	#if defined(CONFIG_CMD_NET)
36b4e2dd MR	245	#define CONFIG_SMC911X
36b4e2dd MR	246	#define CONFIG_SMC911X_32_BIT
b65a77a8 IG	247	#define CM_T3X_SMC911X_BASE 0x2C000000
	248	#define SB_T35_SMC911X_BASE (CM_T3X_SMC911X_BASE + (16 << 20))
	249	#define CONFIG_SMC911X_BASE CM_T3X_SMC911X_BASE
36b4e2dd MR	250	#endif /* (CONFIG_CMD_NET) */
	251
	252	/* additions for new relocation code, must be added to all boards */
	253	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	254	#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
	255	#define CONFIG_SYS_INIT_RAM_SIZE 0x800
	256	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	257	CONFIG_SYS_INIT_RAM_SIZE - \
	258	GENERATED_GBL_DATA_SIZE)
	259
2b8754b2	260	/* Status LED */
9fc376be NK	261	#define CONFIG_STATUS_LED /* Status LED enabled */
9fc376be NK	262	#define CONFIG_BOARD_SPECIFIC_LED
ebc18afd IG	263	#define CONFIG_GPIO_LED
	264	#define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */
	265	#define GREEN_LED_DEV 0
	266	#define STATUS_LED_BIT GREEN_LED_GPIO
2b8754b2 IG	267	#define STATUS_LED_STATE STATUS_LED_ON
2b8754b2 IG	268	#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
ebc18afd	269	#define STATUS_LED_BOOT GREEN_LED_DEV
2b8754b2	270
60e6bdcc NK	271	#define CONFIG_SPLASHIMAGE_GUARD
60e6bdcc NK	272
2b8754b2 IG	273	/* GPIO banks */
2b8754b2 IG	274	#ifdef CONFIG_STATUS_LED
9fc376be	275	#define CONFIG_OMAP3_GPIO_6 /* GPIO186 is in GPIO bank 6 */
2b8754b2 IG	276	#endif
2b8754b2 IG	277
7878ca51 NK	278	/* Display Configuration */
7878ca51 NK	279	#define CONFIG_OMAP3_GPIO_2
6f72892a	280	#define CONFIG_OMAP3_GPIO_5
7878ca51 NK	281	#define CONFIG_VIDEO_OMAP3
	282	#define LCD_BPP LCD_COLOR16
	283
	284	#define CONFIG_LCD
f35034fe	285	#define CONFIG_SPLASH_SCREEN
f82eb2fa	286	#define CONFIG_SPLASH_SOURCE
f35034fe NK	287	#define CONFIG_CMD_BMP
f35034fe NK	288	#define CONFIG_BMP_16BPP
63c4f17b NK	289	#define CONFIG_SCF0403_LCD
	290
	291	#define CONFIG_OMAP3_SPI
7878ca51	292
3e51b7c8	293	/* Defines for SPL */
3e51b7c8 SR	294	#define CONFIG_SPL_FRAMEWORK
	295	#define CONFIG_SPL_NAND_SIMPLE
	296
	297	#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
	298	#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
e2ccdf89	299	#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
205b4f33	300	#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
3e51b7c8 SR	301
3e51b7c8 SR	302	#define CONFIG_SPL_BOARD_INIT
3e51b7c8 SR	303	#define CONFIG_SPL_NAND_BASE
	304	#define CONFIG_SPL_NAND_DRIVERS
	305	#define CONFIG_SPL_NAND_ECC
3e51b7c8 SR	306	#define CONFIG_SPL_OMAP3_ID_NAND
	307	#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
	308
	309	/* NAND boot config */
	310	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	311	#define CONFIG_SYS_NAND_PAGE_COUNT 64
	312	#define CONFIG_SYS_NAND_PAGE_SIZE 2048
	313	#define CONFIG_SYS_NAND_OOBSIZE 64
	314	#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
	315	#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
	316	/*
	317	* Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
	318	* SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
	319	*/
	320	#define CONFIG_SYS_NAND_ECCPOS { 1, 2, 3, 4, 5, 6, 7, 8, 9, \
	321	10, 11, 12 }
	322	#define CONFIG_SYS_NAND_ECCSIZE 512
	323	#define CONFIG_SYS_NAND_ECCBYTES 3
	324	#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
	325
	326	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
	327	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
	328
	329	#define CONFIG_SPL_TEXT_BASE 0x40200800
fa2f81b0 TR	330	#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
fa2f81b0 TR	331	CONFIG_SPL_TEXT_BASE)
3e51b7c8 SR	332
	333	/*
	334	* Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
	335	* older x-loader implementations. And move the BSS area so that it
	336	* doesn't overlap with TEXT_BASE.
	337	*/
	338	#define CONFIG_SYS_TEXT_BASE 0x80008000
	339	#define CONFIG_SPL_BSS_START_ADDR 0x80100000
	340	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
	341
	342	#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
	343	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
	344
bcb447e1 NK	345	/* EEPROM */
	346	#define CONFIG_CMD_EEPROM
	347	#define CONFIG_ENV_EEPROM_IS_ON_I2C
	348	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	349	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
	350	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
	351	#define CONFIG_SYS_EEPROM_SIZE 256
	352
	353	#define CONFIG_CMD_EEPROM_LAYOUT
	354	#define CONFIG_EEPROM_LAYOUT_HELP_STRING "legacy, v1, v2, v3"
	355
36b4e2dd	356	#endif /* __CONFIG_H */