[people/ms/u-boot.git] / include / configs / cm_t35.h

/*
 * (C) Copyright 2011 CompuLab, Ltd.
 * Mike Rapoport <mike@compulab.co.il>
 * Igor Grinberg <grinberg@compulab.co.il>
 *
 * Based on omap3_beagle.h
 * (C) Copyright 2006-2008
 * Texas Instruments.
 * Richard Woodruff <r-woodruff2@ti.com>
 * Syed Mohammed Khasim <x0khasim@ti.com>
 *
 * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_SYS_CACHELINE_SIZE	64

/*
 * High Level Configuration Options
 */
#define CONFIG_CM_T3X	/* working with CM-T35 and CM-T3730 */

#define CONFIG_SDRC	/* The chip has SDRC controller */

#include <asm/arch/cpu.h>		/* get chip and board defs */
#include <asm/arch/omap.h>

/* Clock Defines */
#define V_OSCK			26000000	/* Clock output from T2 */
#define V_SCLK			(V_OSCK >> 1)

#define CONFIG_MISC_INIT_R

#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
#define CONFIG_SERIAL_TAG

/*
 * Size of malloc() pool
 */
#define CONFIG_ENV_SIZE		(16 << 10)	/* 16 KiB */
					/* Sector */
#define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + (128 << 10))

/*
 * Hardware drivers
 */

/*
 * NS16550 Configuration
 */
#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */

#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK

/*
 * select serial console configuration
 */
#define CONFIG_CONS_INDEX		3
#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
#define CONFIG_SERIAL3			3	/* UART3 */

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
					115200}

/* USB */
#define CONFIG_USB_OMAP3
#define CONFIG_USB_MUSB_UDC
#define CONFIG_TWL4030_USB

/* USB device configuration */
#define CONFIG_USB_DEVICE
#define CONFIG_USB_TTY

/* commands to include */
#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
#define CONFIG_MTD_PARTITIONS
#define MTDIDS_DEFAULT		"nand0=nand"
#define MTDPARTS_DEFAULT	"mtdparts=nand:512k(x-loader),"\
				"1920k(u-boot),256k(u-boot-env),"\
				"4m(kernel),-(fs)"

#define CONFIG_SYS_I2C
#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
#define CONFIG_SYS_I2C_EEPROM_BUS	0
#define CONFIG_I2C_MULTI_BUS

/*
 * TWL4030
 */
#define CONFIG_TWL4030_LED

/*
 * Board NAND Info.
 */
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
							/* to access nand */
#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
							/* to access nand at */
							/* CS0 */
#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
							/* devices */

/* Environment information */
#define CONFIG_EXTRA_ENV_SETTINGS \
	"loadaddr=0x82000000\0" \
	"usbtty=cdc_acm\0" \
	"console=ttyO2,115200n8\0" \
	"mpurate=500\0" \
	"vram=12M\0" \
	"dvimode=1024x768MR-16@60\0" \
	"defaultdisplay=dvi\0" \
	"mmcdev=0\0" \
	"mmcroot=/dev/mmcblk0p2 rw\0" \
	"mmcrootfstype=ext4 rootwait\0" \
	"nandroot=/dev/mtdblock4 rw\0" \
	"nandrootfstype=ubifs\0" \
	"mmcargs=setenv bootargs console=${console} " \
		"mpurate=${mpurate} " \
		"vram=${vram} " \
		"omapfb.mode=dvi:${dvimode} " \
		"omapdss.def_disp=${defaultdisplay} " \
		"root=${mmcroot} " \
		"rootfstype=${mmcrootfstype}\0" \
	"nandargs=setenv bootargs console=${console} " \
		"mpurate=${mpurate} " \
		"vram=${vram} " \
		"omapfb.mode=dvi:${dvimode} " \
		"omapdss.def_disp=${defaultdisplay} " \
		"root=${nandroot} " \
		"rootfstype=${nandrootfstype}\0" \
	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
	"bootscript=echo Running bootscript from mmc ...; " \
		"source ${loadaddr}\0" \
	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
	"mmcboot=echo Booting from mmc ...; " \
		"run mmcargs; " \
		"bootm ${loadaddr}\0" \
	"nandboot=echo Booting from nand ...; " \
		"run nandargs; " \
		"nand read ${loadaddr} 2a0000 400000; " \
		"bootm ${loadaddr}\0" \

#define CONFIG_BOOTCOMMAND \
	"mmc dev ${mmcdev}; if mmc rescan; then " \
		"if run loadbootscript; then " \
			"run bootscript; " \
		"else " \
			"if run loaduimage; then " \
				"run mmcboot; " \
			"else run nandboot; " \
			"fi; " \
		"fi; " \
	"else run nandboot; fi"

/*
 * Miscellaneous configurable options
 */
#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
#define CONFIG_TIMESTAMP
#define CONFIG_SYS_AUTOLOAD		"no"
#define CONFIG_SYS_LONGHELP		/* undef to save memory */

#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)	/* memtest */
								/* works on */
#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
					0x01F00000) /* 31MB */

#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)	/* default */
							/* load address */

/*
 * OMAP3 has 12 GP timers, they can be driven by the system clock
 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 * This rate is divided by a local divisor.
 */
#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
#define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	1	/* CS1 is never populated */
#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */

/* **** PISMO SUPPORT *** */
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */

#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET

#if defined(CONFIG_CMD_NET)
#define CONFIG_SMC911X
#define CONFIG_SMC911X_32_BIT
#define CM_T3X_SMC911X_BASE	0x2C000000
#define SB_T35_SMC911X_BASE	(CM_T3X_SMC911X_BASE + (16 << 20))
#define CONFIG_SMC911X_BASE	CM_T3X_SMC911X_BASE
#endif /* (CONFIG_CMD_NET) */

/* additions for new relocation code, must be added to all boards */
#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE	0x800
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR +	\
					 CONFIG_SYS_INIT_RAM_SIZE -	\
					 GENERATED_GBL_DATA_SIZE)

/* Status LED */
#define GREEN_LED_GPIO			186 /* CM-T35 Green LED is GPIO186 */

#define CONFIG_SPLASHIMAGE_GUARD

/* Display Configuration */
#define CONFIG_VIDEO_OMAP3
#define LCD_BPP		LCD_COLOR16

#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_SOURCE
#define CONFIG_BMP_16BPP
#define CONFIG_SCF0403_LCD

/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_NAND_SIMPLE

#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"

#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC

/* NAND boot config */
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT	64
#define CONFIG_SYS_NAND_PAGE_SIZE	2048
#define CONFIG_SYS_NAND_OOBSIZE		64
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
/*
 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
 */
#define CONFIG_SYS_NAND_ECCPOS		{ 1, 2, 3, 4, 5, 6, 7, 8, 9, \
					 10, 11, 12 }
#define CONFIG_SYS_NAND_ECCSIZE		512
#define CONFIG_SYS_NAND_ECCBYTES	3
#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW

#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000

#define CONFIG_SPL_TEXT_BASE		0x40200800
#define CONFIG_SPL_MAX_SIZE		(SRAM_SCRATCH_SPACE_ADDR - \
					 CONFIG_SPL_TEXT_BASE)

/*
 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
 * older x-loader implementations. And move the BSS area so that it
 * doesn't overlap with TEXT_BASE.
 */
#define CONFIG_SYS_TEXT_BASE		0x80008000
#define CONFIG_SPL_BSS_START_ADDR	0x80100000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */

#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000

/* EEPROM */
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
#define CONFIG_SYS_EEPROM_SIZE			256

#endif /* __CONFIG_H */
Commit	Line	Data
36b4e2dd	1	/*
9fc376be	2	* (C) Copyright 2011 CompuLab, Ltd.
36b4e2dd	3	* Mike Rapoport <mike@compulab.co.il>
dccd9a0b	4	* Igor Grinberg <grinberg@compulab.co.il>
36b4e2dd MR	5	*
	6	* Based on omap3_beagle.h
	7	* (C) Copyright 2006-2008
	8	* Texas Instruments.
	9	* Richard Woodruff <r-woodruff2@ti.com>
	10	* Syed Mohammed Khasim <x0khasim@ti.com>
	11	*
b65a77a8	12	* Configuration settings for the CompuLab CM-T35 and CM-T3730 boards
36b4e2dd	13	*
1a459660	14	* SPDX-License-Identifier: GPL-2.0+
36b4e2dd MR	15	*/
	16
	17	#ifndef __CONFIG_H
	18	#define __CONFIG_H
	19
3709844f AA	20	#define CONFIG_SYS_CACHELINE_SIZE 64
3709844f AA	21
36b4e2dd MR	22	/*
	23	* High Level Configuration Options
	24	*/
9fc376be	25	#define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */
36b4e2dd	26
36b4e2dd MR	27	#define CONFIG_SDRC /* The chip has SDRC controller */
	28
	29	#include <asm/arch/cpu.h> /* get chip and board defs */
987ec585	30	#include <asm/arch/omap.h>
36b4e2dd	31
36b4e2dd MR	32	/* Clock Defines */
	33	#define V_OSCK 26000000 /* Clock output from T2 */
	34	#define V_SCLK (V_OSCK >> 1)
	35
36b4e2dd MR	36	#define CONFIG_MISC_INIT_R
36b4e2dd MR	37
9fc376be NK	38	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	39	#define CONFIG_SETUP_MEMORY_TAGS
	40	#define CONFIG_INITRD_TAG
	41	#define CONFIG_REVISION_TAG
82309250	42	#define CONFIG_SERIAL_TAG
36b4e2dd MR	43
	44	/*
	45	* Size of malloc() pool
	46	*/
390cdcda	47	#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
9fc376be NK	48	/* Sector */
9fc376be NK	49	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
36b4e2dd MR	50
	51	/*
	52	* Hardware drivers
	53	*/
	54
	55	/*
	56	* NS16550 Configuration
	57	*/
	58	#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
	59
36b4e2dd MR	60	#define CONFIG_SYS_NS16550_SERIAL
	61	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	62	#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
	63
	64	/*
	65	* select serial console configuration
	66	*/
	67	#define CONFIG_CONS_INDEX 3
	68	#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
	69	#define CONFIG_SERIAL3 3 /* UART3 */
	70
	71	/* allow to overwrite serial and ethaddr */
	72	#define CONFIG_ENV_OVERWRITE
36b4e2dd MR	73	#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
36b4e2dd MR	74	115200}
9fc376be	75
36b4e2dd	76	/* USB */
9fc376be	77	#define CONFIG_USB_OMAP3
95de1e2f	78	#define CONFIG_USB_MUSB_UDC
9fc376be	79	#define CONFIG_TWL4030_USB
36b4e2dd MR	80
36b4e2dd MR	81	/* USB device configuration */
9fc376be NK	82	#define CONFIG_USB_DEVICE
9fc376be NK	83	#define CONFIG_USB_TTY
36b4e2dd MR	84
36b4e2dd MR	85	/* commands to include */
36b4e2dd	86	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
0b800a6b	87	#define CONFIG_MTD_PARTITIONS
9fc376be NK	88	#define MTDIDS_DEFAULT "nand0=nand"
9fc376be NK	89	#define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\
0b800a6b	90	"1920k(u-boot),256k(u-boot-env),"\
9fc376be	91	"4m(kernel),-(fs)"
36b4e2dd	92
6789e84e HS	93	#define CONFIG_SYS_I2C
	94	#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
	95	#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
82309250 NK	96	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
82309250 NK	97	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
52658fda	98	#define CONFIG_SYS_I2C_EEPROM_BUS 0
79874ae9	99	#define CONFIG_I2C_MULTI_BUS
36b4e2dd MR	100
	101	/*
	102	* TWL4030
	103	*/
9fc376be	104	#define CONFIG_TWL4030_LED
36b4e2dd MR	105
	106	/*
	107	* Board NAND Info.
	108	*/
36b4e2dd MR	109	#define CONFIG_NAND_OMAP_GPMC
	110	#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
	111	/* to access nand */
	112	#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
	113	/* to access nand at */
	114	/* CS0 */
36b4e2dd MR	115	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
36b4e2dd MR	116	/* devices */
7bb6e29b	117
36b4e2dd	118	/* Environment information */
36b4e2dd MR	119	#define CONFIG_EXTRA_ENV_SETTINGS \
	120	"loadaddr=0x82000000\0" \
	121	"usbtty=cdc_acm\0" \
f3ef3609	122	"console=ttyO2,115200n8\0" \
36b4e2dd MR	123	"mpurate=500\0" \
	124	"vram=12M\0" \
	125	"dvimode=1024x768MR-16@60\0" \
	126	"defaultdisplay=dvi\0" \
	127	"mmcdev=0\0" \
	128	"mmcroot=/dev/mmcblk0p2 rw\0" \
0b800a6b	129	"mmcrootfstype=ext4 rootwait\0" \
36b4e2dd	130	"nandroot=/dev/mtdblock4 rw\0" \
0b800a6b	131	"nandrootfstype=ubifs\0" \
36b4e2dd MR	132	"mmcargs=setenv bootargs console=${console} " \
	133	"mpurate=${mpurate} " \
	134	"vram=${vram} " \
	135	"omapfb.mode=dvi:${dvimode} " \
36b4e2dd MR	136	"omapdss.def_disp=${defaultdisplay} " \
	137	"root=${mmcroot} " \
	138	"rootfstype=${mmcrootfstype}\0" \
	139	"nandargs=setenv bootargs console=${console} " \
	140	"mpurate=${mpurate} " \
	141	"vram=${vram} " \
	142	"omapfb.mode=dvi:${dvimode} " \
36b4e2dd MR	143	"omapdss.def_disp=${defaultdisplay} " \
	144	"root=${nandroot} " \
	145	"rootfstype=${nandrootfstype}\0" \
	146	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
	147	"bootscript=echo Running bootscript from mmc ...; " \
	148	"source ${loadaddr}\0" \
	149	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
	150	"mmcboot=echo Booting from mmc ...; " \
	151	"run mmcargs; " \
	152	"bootm ${loadaddr}\0" \
	153	"nandboot=echo Booting from nand ...; " \
	154	"run nandargs; " \
0b800a6b	155	"nand read ${loadaddr} 2a0000 400000; " \
36b4e2dd MR	156	"bootm ${loadaddr}\0" \
	157
	158	#define CONFIG_BOOTCOMMAND \
66968110	159	"mmc dev ${mmcdev}; if mmc rescan; then " \
36b4e2dd MR	160	"if run loadbootscript; then " \
	161	"run bootscript; " \
	162	"else " \
	163	"if run loaduimage; then " \
	164	"run mmcboot; " \
	165	"else run nandboot; " \
	166	"fi; " \
	167	"fi; " \
	168	"else run nandboot; fi"
	169
36b4e2dd MR	170	/*
	171	* Miscellaneous configurable options
	172	*/
41d7e702 IG	173	#define CONFIG_AUTO_COMPLETE
	174	#define CONFIG_CMDLINE_EDITING
	175	#define CONFIG_TIMESTAMP
9fc376be	176	#define CONFIG_SYS_AUTOLOAD "no"
36b4e2dd	177	#define CONFIG_SYS_LONGHELP /* undef to save memory */
36b4e2dd MR	178
	179	#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
	180	/* works on */
	181	#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
	182	0x01F00000) /* 31MB */
	183
	184	#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
	185	/* load address */
	186
	187	/*
	188	* OMAP3 has 12 GP timers, they can be driven by the system clock
	189	* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
	190	* This rate is divided by a local divisor.
	191	*/
	192	#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
	193	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
36b4e2dd	194
36b4e2dd MR	195	/*-----------------------------------------------------------------------
	196	* Physical Memory Map
	197	*/
	198	#define CONFIG_NR_DRAM_BANKS 1 /* CS1 is never populated */
	199	#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
36b4e2dd	200
36b4e2dd MR	201	/*-----------------------------------------------------------------------
	202	* FLASH and environment organization
	203	*/
	204
	205	/* ** PISMO SUPPORT * */
36b4e2dd MR	206	/* Monitor at start of flash */
36b4e2dd MR	207	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
3530a35d	208	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
36b4e2dd	209
36b4e2dd	210	#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
6cbec7b3	211	#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
36b4e2dd MR	212	#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
36b4e2dd MR	213
36b4e2dd	214	#if defined(CONFIG_CMD_NET)
36b4e2dd MR	215	#define CONFIG_SMC911X
36b4e2dd MR	216	#define CONFIG_SMC911X_32_BIT
b65a77a8 IG	217	#define CM_T3X_SMC911X_BASE 0x2C000000
	218	#define SB_T35_SMC911X_BASE (CM_T3X_SMC911X_BASE + (16 << 20))
	219	#define CONFIG_SMC911X_BASE CM_T3X_SMC911X_BASE
36b4e2dd MR	220	#endif /* (CONFIG_CMD_NET) */
	221
	222	/* additions for new relocation code, must be added to all boards */
	223	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	224	#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
	225	#define CONFIG_SYS_INIT_RAM_SIZE 0x800
	226	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	227	CONFIG_SYS_INIT_RAM_SIZE - \
	228	GENERATED_GBL_DATA_SIZE)
	229
2b8754b2	230	/* Status LED */
ebc18afd	231	#define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */
2b8754b2	232
60e6bdcc NK	233	#define CONFIG_SPLASHIMAGE_GUARD
60e6bdcc NK	234
7878ca51	235	/* Display Configuration */
7878ca51 NK	236	#define CONFIG_VIDEO_OMAP3
	237	#define LCD_BPP LCD_COLOR16
	238
f35034fe	239	#define CONFIG_SPLASH_SCREEN
f82eb2fa	240	#define CONFIG_SPLASH_SOURCE
f35034fe	241	#define CONFIG_BMP_16BPP
63c4f17b NK	242	#define CONFIG_SCF0403_LCD
63c4f17b NK	243
3e51b7c8	244	/* Defines for SPL */
3e51b7c8 SR	245	#define CONFIG_SPL_FRAMEWORK
	246	#define CONFIG_SPL_NAND_SIMPLE
	247
e2ccdf89	248	#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
205b4f33	249	#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
3e51b7c8	250
3e51b7c8 SR	251	#define CONFIG_SPL_NAND_BASE
	252	#define CONFIG_SPL_NAND_DRIVERS
	253	#define CONFIG_SPL_NAND_ECC
3e51b7c8 SR	254
	255	/* NAND boot config */
	256	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	257	#define CONFIG_SYS_NAND_PAGE_COUNT 64
	258	#define CONFIG_SYS_NAND_PAGE_SIZE 2048
	259	#define CONFIG_SYS_NAND_OOBSIZE 64
	260	#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
	261	#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
	262	/*
	263	* Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
	264	* SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
	265	*/
	266	#define CONFIG_SYS_NAND_ECCPOS { 1, 2, 3, 4, 5, 6, 7, 8, 9, \
	267	10, 11, 12 }
	268	#define CONFIG_SYS_NAND_ECCSIZE 512
	269	#define CONFIG_SYS_NAND_ECCBYTES 3
	270	#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
	271
	272	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
	273	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
	274
	275	#define CONFIG_SPL_TEXT_BASE 0x40200800
fa2f81b0 TR	276	#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
fa2f81b0 TR	277	CONFIG_SPL_TEXT_BASE)
3e51b7c8 SR	278
	279	/*
	280	* Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
	281	* older x-loader implementations. And move the BSS area so that it
	282	* doesn't overlap with TEXT_BASE.
	283	*/
	284	#define CONFIG_SYS_TEXT_BASE 0x80008000
	285	#define CONFIG_SPL_BSS_START_ADDR 0x80100000
	286	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
	287
	288	#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
	289	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
	290
bcb447e1	291	/* EEPROM */
bcb447e1 NK	292	#define CONFIG_ENV_EEPROM_IS_ON_I2C
	293	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	294	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
	295	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
	296	#define CONFIG_SYS_EEPROM_SIZE 256
	297
36b4e2dd	298	#endif /* __CONFIG_H */