[people/ms/u-boot.git] / include / configs / cpu9260.h

/*
 * (C) Copyright 2007-2008
 * Stelian Pop <stelian@popies.net>
 * Lead Tech Design <www.leadtechdesign.com>
 * Ilko Iliev <www.ronetix.at>
 *
 * (C) Copyright 2009
 * Eric Benard <eric@eukrea.com>
 *
 * Configuration settings for the Eukrea CPU9260 board.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* to be removed once maemory-map.h is fixed */
#define AT91_BASE_SYS	0xffffe800
#define AT91_DBGU	(0xfffff200 - AT91_BASE_SYS)

#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000
#define CONFIG_SYS_AT91_SLOW_CLOCK	32768

#if defined(CONFIG_CPU9G20)
#define CONFIG_AT91SAM9G20
#elif defined(CONFIG_CPU9260)
#define CONFIG_AT91SAM9260
#else
#error "Unknown board"
#endif

#include <asm/arch/hardware.h>

#define CONFIG_AT91FAMILY
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_BOARD_EARLY_INIT_F

#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG

#if defined(CONFIG_NANDBOOT)
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_TEXT_BASE           0x23f00000
#else
#define CONFIG_SYS_TEXT_BASE           0x00000000
#endif

/* clocks */
#if defined(CONFIG_CPU9G20)
#define MASTER_PLL_DIV		0x01
#define MASTER_PLL_MUL		0x2B
#elif defined(CONFIG_CPU9260)
#define MASTER_PLL_DIV		0x09
#define MASTER_PLL_MUL		0x61
#endif

/* CKGR_MOR - enable main osc. */
#define CONFIG_SYS_MOR_VAL						\
		(AT91_PMC_MOSCEN |					\
		 (255 << 8))		/* Main Oscillator Start-up Time */
#if defined(CONFIG_CPU9G20)
#define CONFIG_SYS_PLLAR_VAL						\
		(AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
		 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
#elif defined(CONFIG_CPU9260)
#define CONFIG_SYS_PLLAR_VAL						\
		(AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
		 AT91_PMC_OUT |						\
		 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
#endif

#if defined(CONFIG_CPU9G20)
#define	CONFIG_SYS_MCKR1_VAL		\
		(AT91_PMC_CSS_PLLA |	\
		 AT91_PMC_PRES_1 |	\
		 AT91SAM9_PMC_MDIV_6 |	\
		 AT91_PMC_PDIV_2)
#define	CONFIG_SYS_MCKR2_VAL		\
		CONFIG_SYS_MCKR1_VAL
#elif defined(CONFIG_CPU9260)
#define	CONFIG_SYS_MCKR1_VAL		\
		(AT91_PMC_CSS_SLOW |	\
		 AT91_PMC_PRES_1 |	\
		 AT91SAM9_PMC_MDIV_2 |	\
		 AT91_PMC_PDIV_1)
#define	CONFIG_SYS_MCKR2_VAL		\
		(AT91_PMC_CSS_PLLA |	\
		 AT91_PMC_PRES_1 |	\
		 AT91SAM9_PMC_MDIV_2 |	\
		 AT91_PMC_PDIV_1)
#endif

/* define PDC[31:16] as DATA[31:16] */
#define CONFIG_SYS_PIOC_PDR_VAL1	0xFFFF0000
/* no pull-up for D[31:16] */
#define CONFIG_SYS_PIOC_PPUDR_VAL	0xFFFF0000

/* EBI_CSA, 3.3V, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
#define CONFIG_SYS_MATRIX_EBICSA_VAL		\
		(AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A | \
		AT91_MATRIX_CSA_EBI_CS3A | AT91_MATRIX_CSA_VDDIOMSEL_3_3V)

/* SDRAM */
/* SDRAMC_MR Mode register */
#define CONFIG_SYS_SDRC_MR_VAL1		AT91_SDRAMC_MODE_NORMAL
/* SDRAMC_TR - Refresh Timer register */
#define CONFIG_SYS_SDRC_TR_VAL1		0x287
/* SDRAMC_CR - Configuration register*/
#if defined(CONFIG_CPU9G20)
#define CONFIG_SYS_SDRC_CR_VAL_64MB					\
		(AT91_SDRAMC_NC_9 |					\
		 AT91_SDRAMC_NR_13 |					\
		 AT91_SDRAMC_NB_4 |					\
		 AT91_SDRAMC_CAS_2 |					\
		 AT91_SDRAMC_DBW_32 |					\
		 (2 <<  8) |	/* Write Recovery Delay */		\
		 (9 << 12) |	/* Row Cycle Delay */			\
		 (3 << 16) |	/* Row Precharge Delay */		\
		 (3 << 20) |	/* Row to Column Delay */		\
		 (6 << 24) |	/* Active to Precharge Delay */		\
		 (10 << 28))	/* Exit Self Refresh to Active Delay */

#define CONFIG_SYS_SDRC_CR_VAL_128MB					\
		(AT91_SDRAMC_NC_10 |					\
		 AT91_SDRAMC_NR_13 |					\
		 AT91_SDRAMC_NB_4 |					\
		 AT91_SDRAMC_CAS_2 |					\
		 AT91_SDRAMC_DBW_32 |					\
		 (2 <<  8) |	/* Write Recovery Delay */		\
		 (9 << 12) |	/* Row Cycle Delay */			\
		 (3 << 16) |	/* Row Precharge Delay */		\
		 (3 << 20) |	/* Row to Column Delay */		\
		 (6 << 24) |	/* Active to Precharge Delay */		\
		 (10 << 28))	/* Exit Self Refresh to Active Delay */
#elif defined(CONFIG_CPU9260)
#define CONFIG_SYS_SDRC_CR_VAL_64MB					\
		(AT91_SDRAMC_NC_9 |					\
		 AT91_SDRAMC_NR_13 |					\
		 AT91_SDRAMC_NB_4 |					\
		 AT91_SDRAMC_CAS_2 |					\
		 AT91_SDRAMC_DBW_32 |					\
		 (2 <<  8) |	/* Write Recovery Delay */		\
		 (7 << 12) |	/* Row Cycle Delay */			\
		 (2 << 16) |	/* Row Precharge Delay */		\
		 (2 << 20) |	/* Row to Column Delay */		\
		 (5 << 24) |	/* Active to Precharge Delay */		\
		 (8 << 28))	/* Exit Self Refresh to Active Delay */

#define CONFIG_SYS_SDRC_CR_VAL_128MB					\
		(AT91_SDRAMC_NC_10 |					\
		 AT91_SDRAMC_NR_13 |					\
		 AT91_SDRAMC_NB_4 |					\
		 AT91_SDRAMC_CAS_2 |					\
		 AT91_SDRAMC_DBW_32 |					\
		 (2 <<  8) |	/* Write Recovery Delay */		\
		 (7 << 12) |	/* Row Cycle Delay */			\
		 (2 << 16) |	/* Row Precharge Delay */		\
		 (2 << 20) |	/* Row to Column Delay */		\
		 (5 << 24) |	/* Active to Precharge Delay */		\
		 (8 << 28))	/* Exit Self Refresh to Active Delay */
#endif

/* Memory Device Register -> SDRAM */
#define CONFIG_SYS_SDRC_MDR_VAL		AT91_SDRAMC_MD_SDRAM
#define CONFIG_SYS_SDRC_MR_VAL2		AT91_SDRAMC_MODE_PRECHARGE
#define CONFIG_SYS_SDRAM_VAL1		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL3		AT91_SDRAMC_MODE_REFRESH
#define CONFIG_SYS_SDRAM_VAL2		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL3		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL4		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL5		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL6		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL7		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL8		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL9		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL4		AT91_SDRAMC_MODE_LMR
#define CONFIG_SYS_SDRAM_VAL10		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL5		AT91_SDRAMC_MODE_NORMAL
#define CONFIG_SYS_SDRAM_VAL11		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRC_TR_VAL2		1200		/* SDRAM_TR */
#define CONFIG_SYS_SDRAM_VAL12		0		/* SDRAM_BASE */

/* setup SMC0, CS0 (NOR Flash) - 16-bit */
#if defined(CONFIG_CPU9G20)
#define CONFIG_SYS_SMC0_SETUP0_VAL					\
		(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |	\
		 AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0))
#define CONFIG_SYS_SMC0_PULSE0_VAL					\
		(AT91_SMC_PULSE_NWE(8) | AT91_SMC_PULSE_NCS_WR(8) |	\
		 AT91_SMC_PULSE_NRD(14) | AT91_SMC_PULSE_NCS_RD(14))
#define CONFIG_SYS_SMC0_CYCLE0_VAL	\
		(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(14))
#define CONFIG_SYS_SMC0_MODE0_VAL				\
		(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |	\
		 AT91_SMC_MODE_DBW_16 |				\
		 AT91_SMC_MODE_TDF |				\
		 AT91_SMC_MODE_TDF_CYCLE(3))
#elif defined(CONFIG_CPU9260)
#define CONFIG_SYS_SMC0_SETUP0_VAL					\
		(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |	\
		 AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0))
#define CONFIG_SYS_SMC0_PULSE0_VAL					\
		(AT91_SMC_PULSE_NWE(6) | AT91_SMC_PULSE_NCS_WR(6) |	\
		 AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(10))
#define CONFIG_SYS_SMC0_CYCLE0_VAL	\
		(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(10))
#define CONFIG_SYS_SMC0_MODE0_VAL				\
		(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |	\
		 AT91_SMC_MODE_DBW_16 |				\
		 AT91_SMC_MODE_TDF |				\
		 AT91_SMC_MODE_TDF_CYCLE(2))
#endif

/* user reset enable */
#define CONFIG_SYS_RSTC_RMR_VAL			\
		(AT91_RSTC_KEY |		\
		AT91_RSTC_CR_PROCRST |		\
		AT91_RSTC_MR_ERSTL(1) |	\
		AT91_RSTC_MR_ERSTL(2))

/* Disable Watchdog */
#define CONFIG_SYS_WDTC_WDMR_VAL				\
		(AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT |	\
		 AT91_WDT_MR_WDV(0xfff) |			\
		 AT91_WDT_MR_WDDIS |				\
		 AT91_WDT_MR_WDD(0xfff))

/*
 * Hardware drivers
 */
#define CONFIG_AT91SAM9_WATCHDOG
#define CONFIG_AT91_GPIO
#define CONFIG_ATMEL_USART
#define CONFIG_USART_BASE	ATMEL_BASE_DBGU
#define CONFIG_USART_ID		ATMEL_ID_SYS

#define CONFIG_BOOTDELAY	3

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>
#undef CONFIG_CMD_BDI
#undef CONFIG_CMD_IMI
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_IMLS

#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_NAND
#define CONFIG_CMD_USB
#define CONFIG_CMD_FAT
#define CONFIG_CMD_MII

/* SDRAM */
#define CONFIG_NR_DRAM_BANKS	1
#define CONFIG_SYS_SDRAM_BASE		0x20000000
#if defined(CONFIG_CPU9260_128M) || defined(CONFIG_CPU9G20_128M)
#define CONFIG_SYS_SDRAM_SIZE		(128 * 1024 * 1024)
#define CONFIG_SYS_SDRC_CR_VAL	CONFIG_SYS_SDRC_CR_VAL_128MB
#else
#define CONFIG_SYS_SDRAM_SIZE		(64 * 1024 * 1024)
#define CONFIG_SYS_SDRC_CR_VAL	CONFIG_SYS_SDRC_CR_VAL_64MB
#endif

/* NAND flash */
#define CONFIG_NAND_ATMEL
#define CONFIG_SYS_MAX_NAND_DEVICE		1
#define CONFIG_SYS_NAND_BASE			0x40000000
#define CONFIG_SYS_NAND_DBW_8			1
#define CONFIG_SYS_NAND_READY_PIN		AT91_PIO_PORTC, 13
#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIO_PORTC, 14
#define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
#define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)

/* NOR flash */
#if defined(CONFIG_NANDBOOT)
#define CONFIG_SYS_NO_FLASH
#else
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#define PHYS_FLASH_1				0x10000000
#define PHYS_FLASH_2				0x12000000
#define CONFIG_SYS_FLASH_BANKS_LIST		\
		{ PHYS_FLASH_1, PHYS_FLASH_2 }
#define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
#define CONFIG_SYS_MAX_FLASH_SECT		(255+4)
#define CONFIG_SYS_MAX_FLASH_BANKS		2
#define CONFIG_SYS_FLASH_CFI_WIDTH		FLASH_CFI_16BIT
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_MONITOR_BASE			PHYS_FLASH_1
#endif

/* Ethernet */
#define CONFIG_MACB
#define CONFIG_RMII
#define CONFIG_NET_RETRY_COUNT			20
#define CONFIG_MACB_SEARCH_PHY

/* LEDS */
/* Status LED */
#define CONFIG_STATUS_LED
#define CONFIG_BOARD_SPECIFIC_LED
#define STATUS_LED_RED				0
#define STATUS_LED_GREEN			1
#define STATUS_LED_YELLOW			2
#define STATUS_LED_BLUE				3
/* Red */
#define STATUS_LED_BIT				STATUS_LED_RED
#define STATUS_LED_STATE			STATUS_LED_OFF
#define STATUS_LED_PERIOD			(CONFIG_SYS_HZ / 2)
/* Green */
#define STATUS_LED_BIT1				STATUS_LED_GREEN
#define STATUS_LED_STATE1			STATUS_LED_OFF
#define STATUS_LED_PERIOD1			(CONFIG_SYS_HZ / 2)
/* Yellow */
#define STATUS_LED_BIT2				STATUS_LED_YELLOW
#define STATUS_LED_STATE2			STATUS_LED_OFF
#define STATUS_LED_PERIOD2			(CONFIG_SYS_HZ / 2)
/* Blue */
#define STATUS_LED_BIT3				STATUS_LED_BLUE
#define STATUS_LED_STATE3			STATUS_LED_ON
#define STATUS_LED_PERIOD3			(CONFIG_SYS_HZ / 2)
/* Optional value */
#define STATUS_LED_BOOT				STATUS_LED_BIT

#define CONFIG_RED_LED				AT91_PIO_PORTC, 11
#define CONFIG_GREEN_LED			AT91_PIO_PORTC, 12
#define CONFIG_YELLOW_LED			AT91_PIO_PORTC, 7
#define CONFIG_BLUE_LED				AT91_PIO_PORTC, 9

/* USB */
#define CONFIG_USB_ATMEL
#define CONFIG_USB_OHCI_NEW
#define CONFIG_DOS_PARTITION
#define CONFIG_SYS_USB_OHCI_CPU_INIT
#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00500000
#if defined(CONFIG_CPU9G20)
#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9g20"
#elif defined(CONFIG_CPU9260)
#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9260"
#endif
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
#define CONFIG_USB_STORAGE

#define CONFIG_SYS_LOAD_ADDR			0x21000000
#define CONFIG_LOADADDR				CONFIG_SYS_LOAD_ADDR

#define CONFIG_SYS_MEMTEST_START		CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END			\
	(CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - 512 * 1024)

#if defined(CONFIG_NANDBOOT)
#define CONFIG_SYS_USE_NANDFLASH
#undef CONFIG_SYS_USE_FLASH
#else
#define CONFIG_SYS_USE_FLASH
#undef CONFIG_SYS_USE_NANDFLASH
#endif

#if defined(CONFIG_CPU9G20)
#define CONFIG_SYS_BASEDIR	"cpu9G20"
#elif defined(CONFIG_CPU9260)
#define CONFIG_SYS_BASEDIR	"cpu9260"
#endif

#if defined(CONFIG_SYS_USE_FLASH)
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_OFFSET		0x40000
#define CONFIG_ENV_SECT_SIZE		0x20000
#define	CONFIG_ENV_SIZE			0x20000
#define CONFIG_ENV_OVERWRITE

#define CONFIG_BOOTCOMMAND		"run flashboot"

#define MTDIDS_DEFAULT		"nor0=physmap-flash.0,nand0=atmel_nand"
#define MTDPARTS_DEFAULT		\
	"mtdparts=physmap-flash.0:"	\
		"256k(u-boot)ro,"	\
		"128k(u-boot-env)ro,"	\
		"1792k(kernel),"	\
		"-(rootfs);"		\
	"atmel_nand:-(nand)"

#define CONFIG_BOOTARGS "root=/dev/mtdblock3 rootfstype=jffs2 "

#define CONFIG_EXTRA_ENV_SETTINGS				\
	"mtdids=" MTDIDS_DEFAULT "\0"				\
	"mtdparts=" MTDPARTS_DEFAULT "\0"			\
	"partition=nand0,0\0"					\
	"ramargs=setenv bootargs $(bootargs) $(mtdparts)\0"	\
	"ramboot=tftpboot 0x22000000 $(basedir)/uImage;"	\
		"run ramargs;bootm 22000000\0"			\
	"flashboot=run ramargs;bootm 0x10060000\0"		\
	"basedir=" CONFIG_SYS_BASEDIR "\0"			\
	"updtub=tftp 0x24000000 $(basedir)/u-boot.bin;protect "	\
		"off 0x10000000 0x1003ffff;erase 0x10000000 "	\
		"0x1003ffff;cp.b 0x24000000 0x10000000 "	\
		"$(filesize)\0" \
	"updtui=tftp 0x24000000 $(basedir)/uImage;protect off"	\
		" 0x10060000 0x1021ffff;erase 0x10060000 "	\
		"0x1021ffff;cp.b 0x24000000 0x10060000 "	\
		"$(filesize)\0" \
	"updtrfs=tftp 0x24000000 $(basedir)/rootfs.jffs2; "	\
		"protect off 0x10220000 0x13ffffff;erase "	\
		"0x10220000 0x13ffffff;cp.b 0x24000000 "	\
		"0x10220000 $(filesize)\0" \
	""
#elif defined(CONFIG_NANDBOOT)
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET		0x60000
#define CONFIG_ENV_OFFSET_REDUND	0x80000
#define CONFIG_ENV_SECT_SIZE		0x20000
#define	CONFIG_ENV_SIZE			0x20000
#define CONFIG_ENV_SIZE_REDUND		(CONFIG_ENV_SIZE)
#define CONFIG_ENV_OVERWRITE

#define CONFIG_BOOTCOMMAND		"run flashboot"

#define MTDIDS_DEFAULT		"nand0=atmel_nand"
#define MTDPARTS_DEFAULT		\
	"mtdparts=atmel_nand:"		\
		"128k(bootstrap)ro,"	\
		"256k(u-boot)ro,"	\
		"128k(u-boot-env)ro,"	\
		"128k(u-boot-env2)ro,"	\
		"2M(kernel),"	\
		"-(rootfs)"

#define CONFIG_BOOTARGS "root=ubi0:eukrea-cpu9260-rootfs "	\
	"ubi.mtd=5 rootfstype=ubifs at91sam9_wdt.heartbeat=60"

#define CONFIG_EXTRA_ENV_SETTINGS				\
	"mtdids=" MTDIDS_DEFAULT "\0"				\
	"mtdparts=" MTDPARTS_DEFAULT "\0"			\
	"partition=nand0,5\0"					\
	"ramargs=setenv bootargs $(bootargs) $(mtdparts)\0"	\
	"ramboot=tftpboot 0x22000000 $(basedir)/uImage;"	\
		"run ramargs;bootm 22000000\0"			\
	"flashboot=run ramargs; nand read 0x22000000 0xA0000 "	\
		"0x200000; bootm 0x22000000\0"			\
	"basedir=" CONFIG_SYS_BASEDIR "\0"			\
	"u-boot=u-boot-eukrea-cpu9260.bin\0"			\
	"kernel=uImage-eukrea-cpu9260.bin\0"			\
	"rootfs=image-eukrea-cpu9260.ubi\0"			\
	"updtub=tftp ${loadaddr} $(basedir)/${u-boot}; "	\
		"nand erase 20000 40000; "			\
		"nand write ${loadaddr} 20000 40000\0"		\
	"updtui=tftp ${loadaddr} $(basedir)/${kernel}; "	\
		"nand erase a0000 200000; "			\
		"nand write ${loadaddr} a0000 200000\0"		\
	"updtrfs=tftp ${loadaddr} $(basedir)/${rootfs}; "	\
		"nand erase  2a0000 fd60000; "			\
		"nand write ${loadaddr} 2a0000 ${filesize}\0"
#endif

#define CONFIG_BAUDRATE			115200

#if defined(CONFIG_CPU9G20)
#define CONFIG_SYS_PROMPT		"CPU9G20=> "
#elif defined(CONFIG_CPU9260)
#define CONFIG_SYS_PROMPT		"CPU9260=> "
#endif
#define CONFIG_SYS_CBSIZE		256
#define CONFIG_SYS_MAXARGS		16
#define CONFIG_SYS_PBSIZE		\
		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SILENT_CONSOLE
#define CONFIG_NETCONSOLE

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		\
		ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)

#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - \
				GENERATED_GBL_DATA_SIZE)

#endif
Commit	Line	Data
23b80982 TR	1	/*
23b80982 TR	2	* (C) Copyright 2007-2008
c9e798d3	3	* Stelian Pop <stelian@popies.net>
23b80982 TR	4	* Lead Tech Design <www.leadtechdesign.com>
	5	* Ilko Iliev <www.ronetix.at>
	6	*
	7	* (C) Copyright 2009
	8	* Eric Benard <eric@eukrea.com>
	9	*
	10	* Configuration settings for the Eukrea CPU9260 board.
	11	*
1a459660	12	* SPDX-License-Identifier: GPL-2.0+
23b80982 TR	13	*/
	14
	15	#ifndef __CONFIG_H
	16	#define __CONFIG_H
	17
c2b2a07e EB	18	/* to be removed once maemory-map.h is fixed */
	19	#define AT91_BASE_SYS 0xffffe800
	20	#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
23b80982	21
7c966a8b	22	#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000
95d50e5c	23	#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
23b80982 TR	24
23b80982 TR	25	#if defined(CONFIG_CPU9G20)
c2b2a07e	26	#define CONFIG_AT91SAM9G20
23b80982	27	#elif defined(CONFIG_CPU9260)
c2b2a07e	28	#define CONFIG_AT91SAM9260
23b80982 TR	29	#else
	30	#error "Unknown board"
	31	#endif
	32
95d50e5c EB	33	#include <asm/arch/hardware.h>
95d50e5c EB	34
c2b2a07e	35	#define CONFIG_AT91FAMILY
23b80982	36	#define CONFIG_ARCH_CPU_INIT
c2b2a07e EB	37	#define CONFIG_DISPLAY_CPUINFO
c2b2a07e EB	38	#define CONFIG_BOARD_EARLY_INIT_F
23b80982	39
c2b2a07e EB	40	#define CONFIG_CMDLINE_TAG
	41	#define CONFIG_SETUP_MEMORY_TAGS
	42	#define CONFIG_INITRD_TAG
	43
	44	#if defined(CONFIG_NANDBOOT)
	45	#define CONFIG_SKIP_LOWLEVEL_INIT
	46	#define CONFIG_SYS_TEXT_BASE 0x23f00000
	47	#else
	48	#define CONFIG_SYS_TEXT_BASE 0x00000000
	49	#endif
23b80982 TR	50
	51	/* clocks */
	52	#if defined(CONFIG_CPU9G20)
	53	#define MASTER_PLL_DIV 0x01
	54	#define MASTER_PLL_MUL 0x2B
	55	#elif defined(CONFIG_CPU9260)
	56	#define MASTER_PLL_DIV 0x09
	57	#define MASTER_PLL_MUL 0x61
	58	#endif
	59
	60	/* CKGR_MOR - enable main osc. */
	61	#define CONFIG_SYS_MOR_VAL \
	62	(AT91_PMC_MOSCEN \| \
	63	(255 << 8)) /* Main Oscillator Start-up Time */
	64	#if defined(CONFIG_CPU9G20)
	65	#define CONFIG_SYS_PLLAR_VAL \
	66	(AT91_PMC_PLLA_WR_ERRATA \| /* Bit 29 must be 1 when prog */ \
	67	((MASTER_PLL_MUL - 1) << 16) \| (MASTER_PLL_DIV))
	68	#elif defined(CONFIG_CPU9260)
	69	#define CONFIG_SYS_PLLAR_VAL \
	70	(AT91_PMC_PLLA_WR_ERRATA \| /* Bit 29 must be 1 when prog */ \
	71	AT91_PMC_OUT \| \
	72	((MASTER_PLL_MUL - 1) << 16) \| (MASTER_PLL_DIV))
	73	#endif
	74
	75	#if defined(CONFIG_CPU9G20)
	76	#define CONFIG_SYS_MCKR1_VAL \
	77	(AT91_PMC_CSS_PLLA \| \
	78	AT91_PMC_PRES_1 \| \
	79	AT91SAM9_PMC_MDIV_6 \| \
	80	AT91_PMC_PDIV_2)
	81	#define CONFIG_SYS_MCKR2_VAL \
	82	CONFIG_SYS_MCKR1_VAL
	83	#elif defined(CONFIG_CPU9260)
	84	#define CONFIG_SYS_MCKR1_VAL \
	85	(AT91_PMC_CSS_SLOW \| \
	86	AT91_PMC_PRES_1 \| \
	87	AT91SAM9_PMC_MDIV_2 \| \
	88	AT91_PMC_PDIV_1)
	89	#define CONFIG_SYS_MCKR2_VAL \
	90	(AT91_PMC_CSS_PLLA \| \
	91	AT91_PMC_PRES_1 \| \
	92	AT91SAM9_PMC_MDIV_2 \| \
	93	AT91_PMC_PDIV_1)
	94	#endif
	95
	96	/* define PDC[31:16] as DATA[31:16] */
	97	#define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000
	98	/* no pull-up for D[31:16] */
	99	#define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000
	100
	101	/* EBI_CSA, 3.3V, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
	102	#define CONFIG_SYS_MATRIX_EBICSA_VAL \
c2b2a07e EB	103	(AT91_MATRIX_CSA_DBPUC \| AT91_MATRIX_CSA_EBI_CS1A \| \
c2b2a07e EB	104	AT91_MATRIX_CSA_EBI_CS3A \| AT91_MATRIX_CSA_VDDIOMSEL_3_3V)
23b80982 TR	105
	106	/* SDRAM */
	107	/* SDRAMC_MR Mode register */
	108	#define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL
	109	/* SDRAMC_TR - Refresh Timer register */
	110	#define CONFIG_SYS_SDRC_TR_VAL1 0x287
	111	/* SDRAMC_CR - Configuration register*/
	112	#if defined(CONFIG_CPU9G20)
	113	#define CONFIG_SYS_SDRC_CR_VAL_64MB \
	114	(AT91_SDRAMC_NC_9 \| \
	115	AT91_SDRAMC_NR_13 \| \
	116	AT91_SDRAMC_NB_4 \| \
	117	AT91_SDRAMC_CAS_2 \| \
	118	AT91_SDRAMC_DBW_32 \| \
	119	(2 << 8) \| /* Write Recovery Delay */ \
	120	(9 << 12) \| /* Row Cycle Delay */ \
	121	(3 << 16) \| /* Row Precharge Delay */ \
	122	(3 << 20) \| /* Row to Column Delay */ \
	123	(6 << 24) \| /* Active to Precharge Delay */ \
	124	(10 << 28)) /* Exit Self Refresh to Active Delay */
	125
	126	#define CONFIG_SYS_SDRC_CR_VAL_128MB \
	127	(AT91_SDRAMC_NC_10 \| \
	128	AT91_SDRAMC_NR_13 \| \
	129	AT91_SDRAMC_NB_4 \| \
	130	AT91_SDRAMC_CAS_2 \| \
	131	AT91_SDRAMC_DBW_32 \| \
	132	(2 << 8) \| /* Write Recovery Delay */ \
	133	(9 << 12) \| /* Row Cycle Delay */ \
	134	(3 << 16) \| /* Row Precharge Delay */ \
	135	(3 << 20) \| /* Row to Column Delay */ \
	136	(6 << 24) \| /* Active to Precharge Delay */ \
	137	(10 << 28)) /* Exit Self Refresh to Active Delay */
	138	#elif defined(CONFIG_CPU9260)
	139	#define CONFIG_SYS_SDRC_CR_VAL_64MB \
	140	(AT91_SDRAMC_NC_9 \| \
	141	AT91_SDRAMC_NR_13 \| \
	142	AT91_SDRAMC_NB_4 \| \
	143	AT91_SDRAMC_CAS_2 \| \
	144	AT91_SDRAMC_DBW_32 \| \
	145	(2 << 8) \| /* Write Recovery Delay */ \
	146	(7 << 12) \| /* Row Cycle Delay */ \
	147	(2 << 16) \| /* Row Precharge Delay */ \
	148	(2 << 20) \| /* Row to Column Delay */ \
	149	(5 << 24) \| /* Active to Precharge Delay */ \
	150	(8 << 28)) /* Exit Self Refresh to Active Delay */
	151
	152	#define CONFIG_SYS_SDRC_CR_VAL_128MB \
	153	(AT91_SDRAMC_NC_10 \| \
	154	AT91_SDRAMC_NR_13 \| \
	155	AT91_SDRAMC_NB_4 \| \
	156	AT91_SDRAMC_CAS_2 \| \
	157	AT91_SDRAMC_DBW_32 \| \
	158	(2 << 8) \| /* Write Recovery Delay */ \
	159	(7 << 12) \| /* Row Cycle Delay */ \
	160	(2 << 16) \| /* Row Precharge Delay */ \
	161	(2 << 20) \| /* Row to Column Delay */ \
	162	(5 << 24) \| /* Active to Precharge Delay */ \
	163	(8 << 28)) /* Exit Self Refresh to Active Delay */
	164	#endif
	165
	166	/* Memory Device Register -> SDRAM */
	167	#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
	168	#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
169	#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
170	#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
171	#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
172	#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
173	#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
174	#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
175	#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
176	#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
177	#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
178	#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
179	#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
180	#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
181	#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
182	#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
183	#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
184	#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
185
186	/* setup SMC0, CS0 (NOR Flash) - 16-bit */
187	#if defined(CONFIG_CPU9G20)
188	#define CONFIG_SYS_SMC0_SETUP0_VAL \
c2b2a07e EB	189	(AT91_SMC_SETUP_NWE(0) \| AT91_SMC_SETUP_NCS_WR(0) \| \
c2b2a07e EB	190	AT91_SMC_SETUP_NRD(0) \| AT91_SMC_SETUP_NCS_RD(0))
23b80982	191	#define CONFIG_SYS_SMC0_PULSE0_VAL \
c2b2a07e EB	192	(AT91_SMC_PULSE_NWE(8) \| AT91_SMC_PULSE_NCS_WR(8) \| \
c2b2a07e EB	193	AT91_SMC_PULSE_NRD(14) \| AT91_SMC_PULSE_NCS_RD(14))
23b80982	194	#define CONFIG_SYS_SMC0_CYCLE0_VAL \
c2b2a07e	195	(AT91_SMC_CYCLE_NWE(8) \| AT91_SMC_CYCLE_NRD(14))
23b80982	196	#define CONFIG_SYS_SMC0_MODE0_VAL \
c2b2a07e EB	197	(AT91_SMC_MODE_RM_NRD \| AT91_SMC_MODE_WM_NWE \| \
	198	AT91_SMC_MODE_DBW_16 \| \
	199	AT91_SMC_MODE_TDF \| \
	200	AT91_SMC_MODE_TDF_CYCLE(3))
23b80982 TR	201	#elif defined(CONFIG_CPU9260)
23b80982 TR	202	#define CONFIG_SYS_SMC0_SETUP0_VAL \
c2b2a07e EB	203	(AT91_SMC_SETUP_NWE(0) \| AT91_SMC_SETUP_NCS_WR(0) \| \
c2b2a07e EB	204	AT91_SMC_SETUP_NRD(0) \| AT91_SMC_SETUP_NCS_RD(0))
23b80982	205	#define CONFIG_SYS_SMC0_PULSE0_VAL \
c2b2a07e EB	206	(AT91_SMC_PULSE_NWE(6) \| AT91_SMC_PULSE_NCS_WR(6) \| \
c2b2a07e EB	207	AT91_SMC_PULSE_NRD(10) \| AT91_SMC_PULSE_NCS_RD(10))
23b80982	208	#define CONFIG_SYS_SMC0_CYCLE0_VAL \
c2b2a07e	209	(AT91_SMC_CYCLE_NWE(6) \| AT91_SMC_CYCLE_NRD(10))
23b80982	210	#define CONFIG_SYS_SMC0_MODE0_VAL \
c2b2a07e EB	211	(AT91_SMC_MODE_RM_NRD \| AT91_SMC_MODE_WM_NWE \| \
	212	AT91_SMC_MODE_DBW_16 \| \
	213	AT91_SMC_MODE_TDF \| \
	214	AT91_SMC_MODE_TDF_CYCLE(2))
23b80982 TR	215	#endif
	216
	217	/* user reset enable */
	218	#define CONFIG_SYS_RSTC_RMR_VAL \
	219	(AT91_RSTC_KEY \| \
c2b2a07e EB	220	AT91_RSTC_CR_PROCRST \| \
	221	AT91_RSTC_MR_ERSTL(1) \| \
	222	AT91_RSTC_MR_ERSTL(2))
23b80982 TR	223
	224	/* Disable Watchdog */
	225	#define CONFIG_SYS_WDTC_WDMR_VAL \
c2b2a07e EB	226	(AT91_WDT_MR_WDIDLEHLT \| AT91_WDT_MR_WDDBGHLT \| \
	227	AT91_WDT_MR_WDV(0xfff) \| \
	228	AT91_WDT_MR_WDDIS \| \
	229	AT91_WDT_MR_WDD(0xfff))
23b80982 TR	230
	231	/*
	232	* Hardware drivers
	233	*/
c2b2a07e EB	234	#define CONFIG_AT91SAM9_WATCHDOG
	235	#define CONFIG_AT91_GPIO
	236	#define CONFIG_ATMEL_USART
95d50e5c EB	237	#define CONFIG_USART_BASE ATMEL_BASE_DBGU
95d50e5c EB	238	#define CONFIG_USART_ID ATMEL_ID_SYS
23b80982 TR	239
	240	#define CONFIG_BOOTDELAY 3
	241
	242	/*
	243	* BOOTP options
	244	*/
c2b2a07e EB	245	#define CONFIG_BOOTP_BOOTFILESIZE
	246	#define CONFIG_BOOTP_BOOTPATH
	247	#define CONFIG_BOOTP_GATEWAY
	248	#define CONFIG_BOOTP_HOSTNAME
23b80982 TR	249
	250	/*
	251	* Command line configuration.
	252	*/
	253	#include <config_cmd_default.h>
	254	#undef CONFIG_CMD_BDI
	255	#undef CONFIG_CMD_IMI
	256	#undef CONFIG_CMD_FPGA
	257	#undef CONFIG_CMD_LOADS
	258	#undef CONFIG_CMD_IMLS
	259
c2b2a07e EB	260	#define CONFIG_CMD_PING
	261	#define CONFIG_CMD_DHCP
	262	#define CONFIG_CMD_NAND
	263	#define CONFIG_CMD_USB
	264	#define CONFIG_CMD_FAT
	265	#define CONFIG_CMD_MII
23b80982 TR	266
	267	/* SDRAM */
	268	#define CONFIG_NR_DRAM_BANKS 1
c2b2a07e	269	#define CONFIG_SYS_SDRAM_BASE 0x20000000
23b80982	270	#if defined(CONFIG_CPU9260_128M) \|\| defined(CONFIG_CPU9G20_128M)
c2b2a07e	271	#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024)
23b80982 TR	272	#define CONFIG_SYS_SDRC_CR_VAL CONFIG_SYS_SDRC_CR_VAL_128MB
23b80982 TR	273	#else
c2b2a07e	274	#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
23b80982 TR	275	#define CONFIG_SYS_SDRC_CR_VAL CONFIG_SYS_SDRC_CR_VAL_64MB
	276	#endif
	277
	278	/* NAND flash */
c2b2a07e	279	#define CONFIG_NAND_ATMEL
23b80982 TR	280	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	281	#define CONFIG_SYS_NAND_BASE 0x40000000
	282	#define CONFIG_SYS_NAND_DBW_8 1
c2b2a07e EB	283	#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTC, 13
c2b2a07e EB	284	#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTC, 14
23b80982 TR	285	#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
	286	#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
	287
	288	/* NOR flash */
c2b2a07e EB	289	#if defined(CONFIG_NANDBOOT)
	290	#define CONFIG_SYS_NO_FLASH
	291	#else
	292	#define CONFIG_SYS_FLASH_CFI
	293	#define CONFIG_FLASH_CFI_DRIVER
23b80982 TR	294	#define PHYS_FLASH_1 0x10000000
	295	#define PHYS_FLASH_2 0x12000000
	296	#define CONFIG_SYS_FLASH_BANKS_LIST \
	297	{ PHYS_FLASH_1, PHYS_FLASH_2 }
	298	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
	299	#define CONFIG_SYS_MAX_FLASH_SECT (255+4)
	300	#define CONFIG_SYS_MAX_FLASH_BANKS 2
	301	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
c2b2a07e EB	302	#define CONFIG_SYS_FLASH_EMPTY_INFO
	303	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
	304	#define CONFIG_SYS_FLASH_PROTECTION
23b80982	305	#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
c2b2a07e	306	#endif
23b80982 TR	307
23b80982 TR	308	/* Ethernet */
c2b2a07e EB	309	#define CONFIG_MACB
c2b2a07e EB	310	#define CONFIG_RMII
23b80982	311	#define CONFIG_NET_RETRY_COUNT 20
c2b2a07e	312	#define CONFIG_MACB_SEARCH_PHY
23b80982 TR	313
	314	/* LEDS */
	315	/* Status LED */
c2b2a07e EB	316	#define CONFIG_STATUS_LED
c2b2a07e EB	317	#define CONFIG_BOARD_SPECIFIC_LED
23b80982 TR	318	#define STATUS_LED_RED 0
	319	#define STATUS_LED_GREEN 1
	320	#define STATUS_LED_YELLOW 2
	321	#define STATUS_LED_BLUE 3
	322	/* Red */
	323	#define STATUS_LED_BIT STATUS_LED_RED
	324	#define STATUS_LED_STATE STATUS_LED_OFF
	325	#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
	326	/* Green */
	327	#define STATUS_LED_BIT1 STATUS_LED_GREEN
	328	#define STATUS_LED_STATE1 STATUS_LED_OFF
	329	#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
	330	/* Yellow */
	331	#define STATUS_LED_BIT2 STATUS_LED_YELLOW
	332	#define STATUS_LED_STATE2 STATUS_LED_OFF
	333	#define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2)
	334	/* Blue */
	335	#define STATUS_LED_BIT3 STATUS_LED_BLUE
	336	#define STATUS_LED_STATE3 STATUS_LED_ON
	337	#define STATUS_LED_PERIOD3 (CONFIG_SYS_HZ / 2)
	338	/* Optional value */
	339	#define STATUS_LED_BOOT STATUS_LED_BIT
	340
c2b2a07e EB	341	#define CONFIG_RED_LED AT91_PIO_PORTC, 11
	342	#define CONFIG_GREEN_LED AT91_PIO_PORTC, 12
	343	#define CONFIG_YELLOW_LED AT91_PIO_PORTC, 7
	344	#define CONFIG_BLUE_LED AT91_PIO_PORTC, 9
23b80982 TR	345
23b80982 TR	346	/* USB */
c2b2a07e EB	347	#define CONFIG_USB_ATMEL
	348	#define CONFIG_USB_OHCI_NEW
	349	#define CONFIG_DOS_PARTITION
	350	#define CONFIG_SYS_USB_OHCI_CPU_INIT
23b80982	351	#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
c2b2a07e EB	352	#if defined(CONFIG_CPU9G20)
	353	#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g20"
	354	#elif defined(CONFIG_CPU9260)
23b80982	355	#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
c2b2a07e	356	#endif
23b80982	357	#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
c2b2a07e	358	#define CONFIG_USB_STORAGE
23b80982 TR	359
23b80982 TR	360	#define CONFIG_SYS_LOAD_ADDR 0x21000000
c2b2a07e	361	#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
23b80982	362
c2b2a07e EB	363	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
	364	#define CONFIG_SYS_MEMTEST_END \
	365	(CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - 512 * 1024)
23b80982	366
c2b2a07e EB	367	#if defined(CONFIG_NANDBOOT)
	368	#define CONFIG_SYS_USE_NANDFLASH
	369	#undef CONFIG_SYS_USE_FLASH
	370	#else
	371	#define CONFIG_SYS_USE_FLASH
23b80982	372	#undef CONFIG_SYS_USE_NANDFLASH
c2b2a07e EB	373	#endif
	374
	375	#if defined(CONFIG_CPU9G20)
	376	#define CONFIG_SYS_BASEDIR "cpu9G20"
	377	#elif defined(CONFIG_CPU9260)
	378	#define CONFIG_SYS_BASEDIR "cpu9260"
	379	#endif
23b80982 TR	380
23b80982 TR	381	#if defined(CONFIG_SYS_USE_FLASH)
c2b2a07e	382	#define CONFIG_ENV_IS_IN_FLASH
23b80982 TR	383	#define CONFIG_ENV_OFFSET 0x40000
	384	#define CONFIG_ENV_SECT_SIZE 0x20000
	385	#define CONFIG_ENV_SIZE 0x20000
c2b2a07e	386	#define CONFIG_ENV_OVERWRITE
23b80982 TR	387
	388	#define CONFIG_BOOTCOMMAND "run flashboot"
	389
c2b2a07e	390	#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=atmel_nand"
23b80982 TR	391	#define MTDPARTS_DEFAULT \
	392	"mtdparts=physmap-flash.0:" \
	393	"256k(u-boot)ro," \
	394	"128k(u-boot-env)ro," \
	395	"1792k(kernel)," \
	396	"-(rootfs);" \
	397	"atmel_nand:-(nand)"
	398
	399	#define CONFIG_BOOTARGS "root=/dev/mtdblock3 rootfstype=jffs2 "
	400
23b80982 TR	401	#define CONFIG_EXTRA_ENV_SETTINGS \
	402	"mtdids=" MTDIDS_DEFAULT "\0" \
	403	"mtdparts=" MTDPARTS_DEFAULT "\0" \
	404	"partition=nand0,0\0" \
	405	"ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
c2b2a07e	406	"ramboot=tftpboot 0x22000000 $(basedir)/uImage;" \
23b80982 TR	407	"run ramargs;bootm 22000000\0" \
	408	"flashboot=run ramargs;bootm 0x10060000\0" \
	409	"basedir=" CONFIG_SYS_BASEDIR "\0" \
	410	"updtub=tftp 0x24000000 $(basedir)/u-boot.bin;protect " \
	411	"off 0x10000000 0x1003ffff;erase 0x10000000 " \
	412	"0x1003ffff;cp.b 0x24000000 0x10000000 " \
	413	"$(filesize)\0" \
	414	"updtui=tftp 0x24000000 $(basedir)/uImage;protect off" \
	415	" 0x10060000 0x1021ffff;erase 0x10060000 " \
	416	"0x1021ffff;cp.b 0x24000000 0x10060000 " \
	417	"$(filesize)\0" \
	418	"updtrfs=tftp 0x24000000 $(basedir)/rootfs.jffs2; " \
	419	"protect off 0x10220000 0x13ffffff;erase " \
	420	"0x10220000 0x13ffffff;cp.b 0x24000000 " \
	421	"0x10220000 $(filesize)\0" \
	422	""
c2b2a07e EB	423	#elif defined(CONFIG_NANDBOOT)
	424	#define CONFIG_ENV_IS_IN_NAND
	425	#define CONFIG_ENV_OFFSET 0x60000
	426	#define CONFIG_ENV_OFFSET_REDUND 0x80000
	427	#define CONFIG_ENV_SECT_SIZE 0x20000
	428	#define CONFIG_ENV_SIZE 0x20000
	429	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
	430	#define CONFIG_ENV_OVERWRITE
	431
	432	#define CONFIG_BOOTCOMMAND "run flashboot"
	433
	434	#define MTDIDS_DEFAULT "nand0=atmel_nand"
	435	#define MTDPARTS_DEFAULT \
	436	"mtdparts=atmel_nand:" \
	437	"128k(bootstrap)ro," \
	438	"256k(u-boot)ro," \
	439	"128k(u-boot-env)ro," \
	440	"128k(u-boot-env2)ro," \
	441	"2M(kernel)," \
	442	"-(rootfs)"
	443
	444	#define CONFIG_BOOTARGS "root=ubi0:eukrea-cpu9260-rootfs " \
	445	"ubi.mtd=5 rootfstype=ubifs at91sam9_wdt.heartbeat=60"
	446
	447	#define CONFIG_EXTRA_ENV_SETTINGS \
	448	"mtdids=" MTDIDS_DEFAULT "\0" \
	449	"mtdparts=" MTDPARTS_DEFAULT "\0" \
	450	"partition=nand0,5\0" \
	451	"ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
	452	"ramboot=tftpboot 0x22000000 $(basedir)/uImage;" \
	453	"run ramargs;bootm 22000000\0" \
	454	"flashboot=run ramargs; nand read 0x22000000 0xA0000 " \
	455	"0x200000; bootm 0x22000000\0" \
	456	"basedir=" CONFIG_SYS_BASEDIR "\0" \
	457	"u-boot=u-boot-eukrea-cpu9260.bin\0" \
	458	"kernel=uImage-eukrea-cpu9260.bin\0" \
	459	"rootfs=image-eukrea-cpu9260.ubi\0" \
	460	"updtub=tftp ${loadaddr} $(basedir)/${u-boot}; " \
	461	"nand erase 20000 40000; " \
	462	"nand write ${loadaddr} 20000 40000\0" \
	463	"updtui=tftp ${loadaddr} $(basedir)/${kernel}; " \
	464	"nand erase a0000 200000; " \
	465	"nand write ${loadaddr} a0000 200000\0" \
	466	"updtrfs=tftp ${loadaddr} $(basedir)/${rootfs}; " \
	467	"nand erase 2a0000 fd60000; " \
	468	"nand write ${loadaddr} 2a0000 ${filesize}\0"
23b80982 TR	469	#endif
	470
	471	#define CONFIG_BAUDRATE 115200
23b80982 TR	472
	473	#if defined(CONFIG_CPU9G20)
	474	#define CONFIG_SYS_PROMPT "CPU9G20=> "
	475	#elif defined(CONFIG_CPU9260)
	476	#define CONFIG_SYS_PROMPT "CPU9260=> "
	477	#endif
	478	#define CONFIG_SYS_CBSIZE 256
	479	#define CONFIG_SYS_MAXARGS 16
	480	#define CONFIG_SYS_PBSIZE \
	481	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
c2b2a07e EB	482	#define CONFIG_SYS_LONGHELP
	483	#define CONFIG_CMDLINE_EDITING
	484	#define CONFIG_SILENT_CONSOLE
	485	#define CONFIG_NETCONSOLE
23b80982 TR	486
	487	/*
	488	* Size of malloc() pool
	489	*/
	490	#define CONFIG_SYS_MALLOC_LEN \
	491	ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
23b80982	492
c2b2a07e EB	493	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - \
	494	GENERATED_GBL_DATA_SIZE)
	495
23b80982	496	#endif