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6e7fb6ea SR |
1 | /* |
2 | * (C) Copyright 2005 | |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
4 | * John Otken, jotken@softadvances.com | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | /************************************************************************ | |
26 | * luan.h - configuration for LUAN board | |
27 | ***********************************************************************/ | |
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | /*----------------------------------------------------------------------- | |
32 | * High Level Configuration Options | |
33 | *----------------------------------------------------------------------*/ | |
34 | #define CONFIG_LUAN 1 /* Board is Luan */ | |
35 | #define CONFIG_440SP 1 /* Specific PPC440SP support */ | |
36 | #define CONFIG_4xx 1 /* PPC4xx family */ | |
37 | #define CONFIG_440 1 | |
38 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ | |
39 | ||
2ae18241 WD |
40 | #define CONFIG_SYS_TEXT_BASE 0xFFFB0000 |
41 | ||
490f2040 SR |
42 | /* |
43 | * Include common defines/options for all AMCC eval boards | |
44 | */ | |
45 | #define CONFIG_HOSTNAME luan | |
46 | #include "amcc-common.h" | |
47 | ||
00cdb4ce | 48 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ |
6e7fb6ea SR |
49 | #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ |
50 | ||
51 | /*----------------------------------------------------------------------- | |
52 | * Base addresses -- Note these are effective addresses where the | |
53 | * actual resources get mapped (not physical addresses) | |
54 | *----------------------------------------------------------------------*/ | |
6d0f6bcf JCPV |
55 | #define CONFIG_SYS_LARGE_FLASH 0xffc00000 /* 4MB flash address CS0 */ |
56 | #define CONFIG_SYS_SMALL_FLASH 0xff900000 /* 1MB flash address CS2 */ | |
57 | #define CONFIG_SYS_SRAM_BASE 0xff800000 /* 1MB SRAM address CS2 */ | |
bf560807 | 58 | #define CONFIG_SYS_SRAM_SIZE (1 << 20) |
6d0f6bcf | 59 | #define CONFIG_SYS_EPLD_BASE 0xff000000 /* EPLD and FRAM CS1 */ |
6e7fb6ea | 60 | |
6d0f6bcf | 61 | #define CONFIG_SYS_ISRAM_BASE 0xf8000000 /* internal 8k SRAM (L2 cache) */ |
6e7fb6ea | 62 | |
6d0f6bcf JCPV |
63 | #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ |
64 | #define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ | |
65 | #define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */ | |
6e7fb6ea | 66 | |
6d0f6bcf JCPV |
67 | #if CONFIG_SYS_LARGE_FLASH == 0xffc00000 |
68 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LARGE_FLASH | |
6e7fb6ea | 69 | #else |
6d0f6bcf | 70 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_SMALL_FLASH |
6e7fb6ea SR |
71 | #endif |
72 | ||
6d0f6bcf JCPV |
73 | #if CONFIG_SYS_SRAM_BASE |
74 | #define CONFIG_SYS_KBYTES_SDRAM 1024*2 | |
6e7fb6ea | 75 | #else |
6d0f6bcf | 76 | #define CONFIG_SYS_KBYTES_SDRAM 1024 |
6e7fb6ea SR |
77 | #endif |
78 | ||
79 | /*----------------------------------------------------------------------- | |
80 | * Initial RAM & stack pointer (placed in SDRAM) | |
81 | *----------------------------------------------------------------------*/ | |
6d0f6bcf JCPV |
82 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE |
83 | #define CONFIG_SYS_INIT_RAM_END (8 << 10) | |
84 | #define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */ | |
85 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
86 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
6e7fb6ea SR |
87 | |
88 | /*----------------------------------------------------------------------- | |
89 | * Serial Port | |
90 | *----------------------------------------------------------------------*/ | |
550650dd | 91 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
6d0f6bcf | 92 | #define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* external 11.059MHz clk */ |
6e7fb6ea | 93 | |
6e7fb6ea SR |
94 | /*----------------------------------------------------------------------- |
95 | * Environment | |
96 | *----------------------------------------------------------------------*/ | |
97 | /* | |
98 | * Define here the location of the environment variables (FLASH or EEPROM). | |
99 | * Note: DENX encourages to use redundant environment in FLASH. | |
100 | */ | |
5a1aceb0 | 101 | #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ |
6e7fb6ea SR |
102 | |
103 | /*----------------------------------------------------------------------- | |
104 | * FLASH related | |
105 | *----------------------------------------------------------------------*/ | |
6d0f6bcf JCPV |
106 | #define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max number of memory banks */ |
107 | #define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ | |
6e7fb6ea | 108 | |
6d0f6bcf JCPV |
109 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
110 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
6e7fb6ea | 111 | |
6d0f6bcf | 112 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
6e7fb6ea | 113 | |
6d0f6bcf JCPV |
114 | #define CONFIG_SYS_FLASH_ADDR0 0x555 |
115 | #define CONFIG_SYS_FLASH_ADDR1 0x2aa | |
116 | #define CONFIG_SYS_FLASH_WORD_SIZE unsigned char | |
6e7fb6ea | 117 | |
5a1aceb0 | 118 | #ifdef CONFIG_ENV_IS_IN_FLASH |
0e8d1586 | 119 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ |
6d0f6bcf | 120 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) |
0e8d1586 | 121 | #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ |
6e7fb6ea SR |
122 | |
123 | /* Address and size of Redundant Environment Sector */ | |
0e8d1586 JCPV |
124 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) |
125 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
5a1aceb0 | 126 | #endif /* CONFIG_ENV_IS_IN_FLASH */ |
6e7fb6ea SR |
127 | |
128 | /*----------------------------------------------------------------------- | |
129 | * DDR SDRAM | |
130 | *----------------------------------------------------------------------*/ | |
00cdb4ce SR |
131 | #define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ |
132 | #define SPD_EEPROM_ADDRESS {0x53, 0x52} /* SPD i2c spd addresses*/ | |
e4bbed28 | 133 | #define CONFIG_DDR_ECC 1 /* with ECC support */ |
6e7fb6ea SR |
134 | |
135 | /*----------------------------------------------------------------------- | |
136 | * I2C | |
137 | *----------------------------------------------------------------------*/ | |
6d0f6bcf | 138 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
6e7fb6ea | 139 | |
6d0f6bcf JCPV |
140 | #define CONFIG_SYS_I2C_MULTI_EEPROMS |
141 | #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) | |
142 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
143 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
144 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
4f92ed5f | 145 | |
490f2040 SR |
146 | /* |
147 | * Default environment variables | |
148 | */ | |
149 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
150 | CONFIG_AMCC_DEF_ENV \ | |
151 | CONFIG_AMCC_DEF_ENV_PPC \ | |
152 | CONFIG_AMCC_DEF_ENV_NOR_UPD \ | |
6e7fb6ea SR |
153 | "kernel_addr=fc000000\0" \ |
154 | "ramdisk_addr=fc100000\0" \ | |
6e7fb6ea | 155 | "" |
6e7fb6ea | 156 | |
a00eccfe | 157 | #define CONFIG_HAS_ETH0 |
6e7fb6ea SR |
158 | #define CONFIG_PHY_ADDR 1 |
159 | #define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */ | |
160 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
161 | ||
6e7fb6ea SR |
162 | #ifdef DEBUG |
163 | #define CONFIG_PANIC_HANG | |
164 | #else | |
165 | #define CONFIG_HW_WATCHDOG /* watchdog */ | |
166 | #endif | |
167 | ||
7f5c0157 | 168 | /* |
490f2040 | 169 | * Commands additional to the ones defined in amcc-common.h |
7f5c0157 | 170 | */ |
9bbb1c08 | 171 | #define CONFIG_CMD_PCI |
9bbb1c08 | 172 | #define CONFIG_CMD_SDRAM |
6e7fb6ea | 173 | |
6e7fb6ea SR |
174 | /*----------------------------------------------------------------------- |
175 | * PCI stuff | |
176 | *----------------------------------------------------------------------- | |
177 | */ | |
9bbb1c08 | 178 | #if defined(CONFIG_CMD_PCI) |
6e7fb6ea SR |
179 | |
180 | /* General PCI */ | |
181 | #define CONFIG_PCI /* include pci support */ | |
182 | #define CONFIG_PCI_PNP /* do (not) pci plug-and-play */ | |
183 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
184 | ||
185 | /* Board-specific PCI */ | |
6d0f6bcf JCPV |
186 | #define CONFIG_SYS_PCI_TARGET_INIT |
187 | #undef CONFIG_SYS_PCI_MASTER_INIT | |
6e7fb6ea | 188 | |
6d0f6bcf JCPV |
189 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ |
190 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x4403 /* whatever */ | |
6e7fb6ea | 191 | |
9bbb1c08 | 192 | #endif |
6e7fb6ea | 193 | |
6e7fb6ea | 194 | #endif /* __CONFIG_H */ |