projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 76316a31 | 1 | /* |
| 4aecfb16 | 2 | * (C) Copyright 2007-2010 Michal Simek |
| 76316a31 | 3 | * |
| cb1bc63b | 4 | * Michal SIMEK <monstr@monstr.eu> |
| 76316a31 | 5 | * |
| 1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
| 76316a31 MS |
7 | */ |
| 8 | ||
| 9 | #ifndef __CONFIG_H | |
| 10 | #define __CONFIG_H | |
| 11 | ||
| 52a822ed | 12 | #include "../board/xilinx/microblaze-generic/xparameters.h" |
| 76316a31 | 13 | |
| 4aecfb16 | 14 | /* MicroBlaze CPU */ |
| 1a50f164 | 15 | #define MICROBLAZE_V5 1 |
| 76316a31 | 16 | |
| bcec8f49 | 17 | /* linear and spi flash memory */ |
| 1fe7e8fa SL |
18 | #ifdef XILINX_FLASH_START |
| 19 | #define FLASH | |
| bcec8f49 | 20 | #undef SPIFLASH |
| 1fe7e8fa SL |
21 | #undef RAMENV /* hold environment in flash */ |
| 22 | #else | |
| bcec8f49 | 23 | #ifdef XILINX_SPI_FLASH_BASEADDR |
| 1fe7e8fa | 24 | #undef FLASH |
| bcec8f49 SL |
25 | #define SPIFLASH |
| 26 | #undef RAMENV /* hold environment in flash */ | |
| 27 | #else | |
| 28 | #undef FLASH | |
| 29 | #undef SPIFLASH | |
| 1fe7e8fa SL |
30 | #define RAMENV /* hold environment in RAM */ |
| 31 | #endif | |
| bcec8f49 | 32 | #endif |
| 1fe7e8fa | 33 | |
| 76316a31 | 34 | /* uart */ |
| 67659e2e MS |
35 | /* The following table includes the supported baudrates */ |
| 36 | # define CONFIG_SYS_BAUDRATE_TABLE \ | |
| 37 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} | |
| 38 | ||
| 76316a31 | 39 | /* setting reset address */ |
| 14d0a02a | 40 | /*#define CONFIG_SYS_RESET_ADDRESS CONFIG_SYS_TEXT_BASE*/ |
| 76316a31 MS |
41 | |
| 42 | /* gpio */ | |
| 4c6a6f02 | 43 | #ifdef XILINX_GPIO_BASEADDR |
| 4e779ad2 | 44 | # define CONFIG_XILINX_GPIO |
| 4aecfb16 | 45 | # define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR |
| 4c6a6f02 | 46 | #endif |
| 76316a31 | 47 | |
| 0f21f98d MS |
48 | /* watchdog */ |
| 49 | #if defined(XILINX_WATCHDOG_BASEADDR) && defined(XILINX_WATCHDOG_IRQ) | |
| 50 | # define CONFIG_WATCHDOG_BASEADDR XILINX_WATCHDOG_BASEADDR | |
| 51 | # define CONFIG_WATCHDOG_IRQ XILINX_WATCHDOG_IRQ | |
| b5e9b9a9 MS |
52 | # ifndef CONFIG_SPL_BUILD |
| 53 | # define CONFIG_HW_WATCHDOG | |
| 54 | # define CONFIG_XILINX_TB_WATCHDOG | |
| 55 | # endif | |
| 0f21f98d MS |
56 | #endif |
| 57 | ||
| e945f6dc MS |
58 | #define CONFIG_SYS_MALLOC_LEN 0xC0000 |
| 59 | ||
| 60 | /* Stack location before relocation */ | |
| 4fcd0b33 MS |
61 | #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_TEXT_BASE - \ |
| 62 | CONFIG_SYS_MALLOC_F_LEN) | |
| 76316a31 | 63 | |
| 8f371b18 SL |
64 | /* |
| 65 | * CFI flash memory layout - Example | |
| 66 | * CONFIG_SYS_FLASH_BASE = 0x2200_0000; | |
| 67 | * CONFIG_SYS_FLASH_SIZE = 0x0080_0000; 8MB | |
| 68 | * | |
| 69 | * SECT_SIZE = 0x20000; 128kB is one sector | |
| 70 | * CONFIG_ENV_SIZE = SECT_SIZE; 128kB environment store | |
| 71 | * | |
| 72 | * 0x2200_0000 CONFIG_SYS_FLASH_BASE | |
| 73 | * FREE 256kB | |
| 74 | * 0x2204_0000 CONFIG_ENV_ADDR | |
| 75 | * ENV_AREA 128kB | |
| 76 | * 0x2206_0000 | |
| 77 | * FREE | |
| 78 | * 0x2280_0000 CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE | |
| 79 | * | |
| 80 | */ | |
| 81 | ||
| 76316a31 | 82 | #ifdef FLASH |
| 4aecfb16 MS |
83 | # define CONFIG_SYS_FLASH_BASE XILINX_FLASH_START |
| 84 | # define CONFIG_SYS_FLASH_SIZE XILINX_FLASH_SIZE | |
| 85 | # define CONFIG_SYS_FLASH_CFI 1 | |
| 86 | # define CONFIG_FLASH_CFI_DRIVER 1 | |
| 87 | /* ?empty sector */ | |
| 88 | # define CONFIG_SYS_FLASH_EMPTY_INFO 1 | |
| 89 | /* max number of memory banks */ | |
| 90 | # define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
| 91 | /* max number of sectors on one chip */ | |
| 92 | # define CONFIG_SYS_MAX_FLASH_SECT 512 | |
| 93 | /* hardware flash protection */ | |
| 94 | # define CONFIG_SYS_FLASH_PROTECTION | |
| 22ff7f4d MS |
95 | /* use buffered writes (20x faster) */ |
| 96 | # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 | |
| 4aecfb16 | 97 | # ifdef RAMENV |
| 4aecfb16 MS |
98 | # define CONFIG_ENV_SIZE 0x1000 |
| 99 | # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) | |
| 100 | ||
| bcec8f49 | 101 | # else /* FLASH && !RAMENV */ |
| 4aecfb16 MS |
102 | /* 128K(one sector) for env */ |
| 103 | # define CONFIG_ENV_SECT_SIZE 0x20000 | |
| 104 | # define CONFIG_ENV_ADDR \ | |
| 105 | (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE)) | |
| 106 | # define CONFIG_ENV_SIZE 0x20000 | |
| bcec8f49 | 107 | # endif /* FLASH && !RAMBOOT */ |
| 76316a31 | 108 | #else /* !FLASH */ |
| bcec8f49 SL |
109 | |
| 110 | #ifdef SPIFLASH | |
| bcec8f49 | 111 | # define CONFIG_SYS_SPI_BASE XILINX_SPI_FLASH_BASEADDR |
| bcec8f49 | 112 | # define CONFIG_SPI 1 |
| bcec8f49 SL |
113 | # define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 |
| 114 | # define CONFIG_SF_DEFAULT_SPEED XILINX_SPI_FLASH_MAX_FREQ | |
| 115 | # define CONFIG_SF_DEFAULT_CS XILINX_SPI_FLASH_CS | |
| 116 | ||
| 117 | # ifdef RAMENV | |
| bcec8f49 SL |
118 | # define CONFIG_ENV_SIZE 0x1000 |
| 119 | # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) | |
| 120 | ||
| 121 | # else /* SPIFLASH && !RAMENV */ | |
| bcec8f49 SL |
122 | # define CONFIG_ENV_SPI_MODE SPI_MODE_3 |
| 123 | # define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED | |
| 124 | # define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS | |
| 125 | /* 128K(two sectors) for env */ | |
| 126 | # define CONFIG_ENV_SECT_SIZE 0x10000 | |
| 127 | # define CONFIG_ENV_SIZE (2 * CONFIG_ENV_SECT_SIZE) | |
| 128 | /* Warning: adjust the offset in respect of other flash content and size */ | |
| 129 | # define CONFIG_ENV_OFFSET (128 * CONFIG_ENV_SECT_SIZE) /* at 8MB */ | |
| 130 | # endif /* SPIFLASH && !RAMBOOT */ | |
| 131 | #else /* !SPIFLASH */ | |
| 132 | ||
| 4aecfb16 | 133 | /* ENV in RAM */ |
| 4aecfb16 MS |
134 | # define CONFIG_ENV_SIZE 0x1000 |
| 135 | # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) | |
| bcec8f49 | 136 | #endif /* !SPIFLASH */ |
| 76316a31 MS |
137 | #endif /* !FLASH */ |
| 138 | ||
| e9b737de | 139 | #if defined(XILINX_USE_ICACHE) |
| 4aecfb16 | 140 | # define CONFIG_ICACHE |
| e9b737de | 141 | #else |
| 4aecfb16 | 142 | # undef CONFIG_ICACHE |
| e9b737de MS |
143 | #endif |
| 144 | ||
| 145 | #if defined(XILINX_USE_DCACHE) | |
| 4aecfb16 | 146 | # define CONFIG_DCACHE |
| e9b737de | 147 | #else |
| 4aecfb16 | 148 | # undef CONFIG_DCACHE |
| e9b737de MS |
149 | #endif |
| 150 | ||
| 5811830f MS |
151 | #ifndef XILINX_DCACHE_BYTE_SIZE |
| 152 | #define XILINX_DCACHE_BYTE_SIZE 32768 | |
| 153 | #endif | |
| 154 | ||
| 079a136c JL |
155 | /* |
| 156 | * BOOTP options | |
| 157 | */ | |
| 158 | #define CONFIG_BOOTP_BOOTFILESIZE | |
| 159 | #define CONFIG_BOOTP_BOOTPATH | |
| 160 | #define CONFIG_BOOTP_GATEWAY | |
| 161 | #define CONFIG_BOOTP_HOSTNAME | |
| 76316a31 | 162 | |
| 5dc11a51 JL |
163 | /* |
| 164 | * Command line configuration. | |
| 165 | */ | |
| 5dc11a51 | 166 | #define CONFIG_CMD_MFSL |
| 4d49b280 | 167 | |
| 5dc11a51 | 168 | #if defined(FLASH) |
| bcec8f49 | 169 | # if !defined(RAMENV) |
| bcec8f49 SL |
170 | # define CONFIG_CMD_SAVES |
| 171 | # endif | |
| 172 | ||
| 173 | #else | |
| 174 | #if defined(SPIFLASH) | |
| bcec8f49 | 175 | |
| 4aecfb16 | 176 | # if !defined(RAMENV) |
| 4aecfb16 MS |
177 | # define CONFIG_CMD_SAVES |
| 178 | # endif | |
| 5dc11a51 | 179 | #endif |
| bcec8f49 | 180 | #endif |
| 76316a31 | 181 | |
| 5dc11a51 | 182 | #if defined(CONFIG_CMD_JFFS2) |
| 7cfb13a7 SL |
183 | # define CONFIG_MTD_PARTITIONS |
| 184 | #endif | |
| 185 | ||
| 7cfb13a7 SL |
186 | #if defined(CONFIG_CMD_UBI) |
| 187 | # define CONFIG_MTD_PARTITIONS | |
| 7cfb13a7 SL |
188 | #endif |
| 189 | ||
| 190 | #if defined(CONFIG_MTD_PARTITIONS) | |
| 191 | /* MTD partitions */ | |
| 942556a9 SR |
192 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
| 193 | #define CONFIG_FLASH_CFI_MTD | |
| c82a541d | 194 | #define MTDIDS_DEFAULT "nor0=flash-0" |
| 144876a3 MS |
195 | |
| 196 | /* default mtd partition table */ | |
| c82a541d | 197 | #define MTDPARTS_DEFAULT "mtdparts=flash-0:256k(u-boot),"\ |
| 144876a3 MS |
198 | "256k(env),3m(kernel),1m(romfs),"\ |
| 199 | "1m(cramfs),-(jffs2)" | |
| 200 | #endif | |
| 201 | ||
| 4aecfb16 MS |
202 | /* size of console buffer */ |
| 203 | #define CONFIG_SYS_CBSIZE 512 | |
| 204 | /* print buffer size */ | |
| 205 | #define CONFIG_SYS_PBSIZE \ | |
| 206 | (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
| 207 | /* max number of command args */ | |
| 208 | #define CONFIG_SYS_MAXARGS 15 | |
| 6d0f6bcf | 209 | #define CONFIG_SYS_LONGHELP |
| 4aecfb16 | 210 | /* default load address */ |
| 44a3a91c | 211 | #define CONFIG_SYS_LOAD_ADDR 0 |
| 76316a31 | 212 | |
| 76316a31 | 213 | #define CONFIG_BOOTARGS "root=romfs" |
| 330e5545 | 214 | #define CONFIG_HOSTNAME XILINX_BOARD_NAME |
| 853643d8 | 215 | #define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm" |
| 76316a31 MS |
216 | |
| 217 | /* architecture dependent code */ | |
| 6d0f6bcf | 218 | #define CONFIG_SYS_USR_EXCEP /* user exception */ |
| 76316a31 | 219 | |
| 0900bee9 | 220 | #define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot;echo" |
| 144876a3 | 221 | |
| 2902a9b7 | 222 | #ifndef CONFIG_EXTRA_ENV_SETTINGS |
| 4aecfb16 | 223 | #define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" \ |
| c82a541d SL |
224 | "nor0=flash-0\0"\ |
| 225 | "mtdparts=mtdparts=flash-0:"\ | |
| 144876a3 | 226 | "256k(u-boot),256k(env),3m(kernel),"\ |
| 78376452 MS |
227 | "1m(romfs),1m(cramfs),-(jffs2)\0"\ |
| 228 | "nc=setenv stdout nc;"\ | |
| 229 | "setenv stdin nc\0" \ | |
| 230 | "serial=setenv stdout serial;"\ | |
| 231 | "setenv stdin serial\0" | |
| 2902a9b7 | 232 | #endif |
| 144876a3 | 233 | |
| 188dc16b | 234 | #define CONFIG_CMDLINE_EDITING |
| 188dc16b | 235 | |
| 37e892d9 MS |
236 | /* Enable flat device tree support */ |
| 237 | #define CONFIG_LMB 1 | |
| 37e892d9 | 238 | |
| 4632b1ea | 239 | #if defined(CONFIG_XILINX_AXIEMAC) |
| f5e5e1ff | 240 | # define CONFIG_MII 1 |
| f5e5e1ff SL |
241 | # define CONFIG_PHY_GIGE 1 |
| 242 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1 | |
| f5e5e1ff SL |
243 | # define CONFIG_PHY_ATHEROS 1 |
| 244 | # define CONFIG_PHY_BROADCOM 1 | |
| 245 | # define CONFIG_PHY_DAVICOM 1 | |
| 246 | # define CONFIG_PHY_LXT 1 | |
| 247 | # define CONFIG_PHY_MARVELL 1 | |
| f5e5e1ff SL |
248 | # define CONFIG_PHY_NATSEMI 1 |
| 249 | # define CONFIG_PHY_REALTEK 1 | |
| 250 | # define CONFIG_PHY_VITESSE 1 | |
| 251 | #else | |
| 252 | # undef CONFIG_MII | |
| f5e5e1ff SL |
253 | #endif |
| 254 | ||
| 9d242745 | 255 | /* SPL part */ |
| 9d242745 MS |
256 | #define CONFIG_CMD_SPL |
| 257 | #define CONFIG_SPL_FRAMEWORK | |
| 9d242745 MS |
258 | |
| 259 | #define CONFIG_SPL_LDSCRIPT "arch/microblaze/cpu/u-boot-spl.lds" | |
| 260 | ||
| 4dd09742 | 261 | #ifdef CONFIG_SYS_FLASH_BASE |
| 4dd09742 MS |
262 | # define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_FLASH_BASE |
| 263 | #endif | |
| 9d242745 MS |
264 | |
| 265 | /* for booting directly linux */ | |
| 9d242745 | 266 | |
| 9d242745 MS |
267 | #define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \ |
| 268 | 0x40000) | |
| 5aa79f26 | 269 | #define CONFIG_SYS_FDT_SIZE (16<<10) |
| 9d242745 MS |
270 | #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_TEXT_BASE + \ |
| 271 | 0x1000000) | |
| 272 | ||
| 273 | /* SP location before relocation, must use scratch RAM */ | |
| 274 | /* BRAM start */ | |
| 275 | #define CONFIG_SYS_INIT_RAM_ADDR 0x0 | |
| 276 | /* BRAM size - will be generated */ | |
| ca7d2266 | 277 | #define CONFIG_SYS_INIT_RAM_SIZE 0x100000 |
| 9d242745 | 278 | |
| ca7d2266 MS |
279 | # define CONFIG_SPL_STACK_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ |
| 280 | CONFIG_SYS_INIT_RAM_SIZE - \ | |
| 281 | CONFIG_SYS_MALLOC_F_LEN) | |
| 9d242745 MS |
282 | |
| 283 | /* Just for sure that there is a space for stack */ | |
| 284 | #define CONFIG_SPL_STACK_SIZE 0x100 | |
| 285 | ||
| 9d242745 MS |
286 | #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE |
| 287 | ||
| 288 | #define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_INIT_RAM_SIZE - \ | |
| 289 | CONFIG_SYS_INIT_RAM_ADDR - \ | |
| ca7d2266 | 290 | CONFIG_SYS_MALLOC_F_LEN - \ |
| 9d242745 MS |
291 | CONFIG_SPL_STACK_SIZE) |
| 292 | ||
| 76316a31 | 293 | #endif /* __CONFIG_H */ |