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53d4a498 BS |
1 | /* |
2 | * (C) Copyright 2003-2007 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
0ffb941c | 5 | * Based on Motion-PRO board config file by Robert McCullough, rob@promessinc.com |
53d4a498 | 6 | * |
3765b3e7 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
53d4a498 BS |
8 | */ |
9 | ||
10 | #ifndef __CONFIG_H | |
11 | #define __CONFIG_H | |
12 | ||
53d4a498 BS |
13 | /* |
14 | * High Level Configuration Options | |
15 | */ | |
16 | ||
53d4a498 | 17 | /* CPU and board */ |
b2a6dfe4 | 18 | #define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */ |
53d4a498 BS |
19 | #define CONFIG_MOTIONPRO 1 /* ... on Promess Motion-PRO board */ |
20 | ||
31d82672 | 21 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
53d4a498 | 22 | |
2ae18241 WD |
23 | #define CONFIG_SYS_TEXT_BASE 0xfff00000 |
24 | ||
079a136c JL |
25 | /* |
26 | * BOOTP options | |
27 | */ | |
28 | #define CONFIG_BOOTP_BOOTFILESIZE | |
29 | #define CONFIG_BOOTP_BOOTPATH | |
30 | #define CONFIG_BOOTP_GATEWAY | |
31 | #define CONFIG_BOOTP_HOSTNAME | |
32 | ||
53d4a498 | 33 | /* |
5dc11a51 | 34 | * Command line configuration. |
53d4a498 | 35 | */ |
7a8ddeea WD |
36 | #define CONFIG_CMD_BEDBUG |
37 | #define CONFIG_CMD_DATE | |
7a8ddeea WD |
38 | #define CONFIG_CMD_DTT |
39 | #define CONFIG_CMD_EEPROM | |
7a8ddeea WD |
40 | #define CONFIG_CMD_IDE |
41 | #define CONFIG_CMD_IMMAP | |
42 | #define CONFIG_CMD_JFFS2 | |
7a8ddeea | 43 | #define CONFIG_CMD_REGINFO |
53d4a498 BS |
44 | |
45 | /* | |
46 | * Serial console configuration | |
47 | */ | |
48 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ | |
49 | #define CONFIG_NETCONSOLE 1 /* network console */ | |
6d0f6bcf | 50 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
53d4a498 | 51 | |
53d4a498 BS |
52 | /* |
53 | * Ethernet configuration | |
54 | */ | |
55 | #define CONFIG_MPC5xxx_FEC 1 | |
86321fc1 | 56 | #define CONFIG_MPC5xxx_FEC_MII100 |
53d4a498 BS |
57 | #define CONFIG_PHY_ADDR 0x2 |
58 | #define CONFIG_PHY_TYPE 0x79c874 | |
c00125e0 | 59 | #define CONFIG_RESET_PHY_R 1 |
53d4a498 BS |
60 | |
61 | /* | |
62 | * Autobooting | |
63 | */ | |
53d4a498 | 64 | #undef CONFIG_BOOTARGS |
53d4a498 | 65 | |
7a8ddeea | 66 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
7a8ddeea | 67 | |
53d4a498 BS |
68 | /* |
69 | * Default environment settings | |
70 | */ | |
71 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
53d4a498 BS |
72 | "netdev=eth0\0" \ |
73 | "hostname=motionpro\0" \ | |
0ffb941c WG |
74 | "netmask=255.255.255.0\0" \ |
75 | "ipaddr=192.168.1.106\0" \ | |
76 | "serverip=192.168.1.100\0" \ | |
77 | "gatewayip=192.168.1.100\0" \ | |
1f1369c3 | 78 | "console=ttyPSC0,115200\0" \ |
7a8ddeea WD |
79 | "u-boot_addr=400000\0" \ |
80 | "kernel_addr=400000\0" \ | |
81 | "fdt_addr=700000\0" \ | |
82 | "ramdisk_addr=800000\0" \ | |
fa5c2ba1 | 83 | "multi_image_addr=800000\0" \ |
0ffb941c WG |
84 | "rootpath=/opt/eldk-4.2/ppc_6xx\0" \ |
85 | "u-boot=/tftpboot/motionpro/u-boot.bin\0" \ | |
86 | "bootfile=/tftpboot/motionpro/uImage\0" \ | |
87 | "fdt_file=/tftpboot/motionpro/motionpro.dtb\0" \ | |
88 | "ramdisk_file=/tftpboot/motionpro/uRamdisk\0" \ | |
fa5c2ba1 | 89 | "multi_image_file=kernel+initrd+dtb.img\0" \ |
7049288f | 90 | "load=tftp ${u-boot_addr} ${u-boot}\0" \ |
7a8ddeea WD |
91 | "update=prot off fff00000 +${filesize};" \ |
92 | "era fff00000 +${filesize}; " \ | |
7049288f | 93 | "cp.b ${u-boot_addr} fff00000 ${filesize};" \ |
7a8ddeea | 94 | "prot on fff00000 +${filesize}\0" \ |
53d4a498 | 95 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
53d4a498 | 96 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
7049288f | 97 | "nfsroot=${serverip}:${rootpath}\0" \ |
0ffb941c WG |
98 | "fat_args=setenv bootargs root=/dev/sda rw\0" \ |
99 | "mtdids=nor0=ff000000.flash\0" \ | |
100 | "mtdparts=ff000000.flash:13m(fs),2m(kernel),384k(uboot)," \ | |
101 | "128k(env),128k(redund_env)," \ | |
102 | "128k(dtb),128k(user_data)\0" \ | |
103 | "addcons=setenv bootargs ${bootargs} console=${console}\0" \ | |
104 | "addmtd=setenv bootargs ${bootargs} mtdparts=${mtdparts}\0" \ | |
7049288f BS |
105 | "addip=setenv bootargs ${bootargs} " \ |
106 | "ip=${ipaddr}:${serverip}:${gatewayip}:" \ | |
107 | "${netmask}:${hostname}:${netdev}:off panic=1 " \ | |
108 | "console=${console}\0" \ | |
109 | "net_nfs=tftp ${kernel_addr} ${bootfile}; " \ | |
0ffb941c WG |
110 | "tftp ${fdt_addr} ${fdt_file}; " \ |
111 | "run nfsargs addip addmtd; " \ | |
7049288f BS |
112 | "bootm ${kernel_addr} - ${fdt_addr}\0" \ |
113 | "net_self=tftp ${kernel_addr} ${bootfile}; " \ | |
114 | "tftp ${fdt_addr} ${fdt_file}; " \ | |
115 | "tftp ${ramdisk_addr} ${ramdisk_file}; " \ | |
0ffb941c WG |
116 | "nfs ${ramdisk_addr} ${serverip}:${rootpath}/images/uRamdisk; " \ |
117 | "run ramargs addip addcons addmtd; " \ | |
7049288f | 118 | "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ |
0ffb941c | 119 | "fat_multi=run fat_args addip addmtd; fatload ide 0:1 " \ |
fa5c2ba1 BS |
120 | "${multi_image_addr} ${multi_image_file}; " \ |
121 | "bootm ${multi_image_addr}\0" \ | |
53d4a498 | 122 | "" |
0ffb941c | 123 | #define CONFIG_BOOTCOMMAND "run fat_multi" |
53d4a498 | 124 | |
53d4a498 BS |
125 | /* |
126 | * do board-specific init | |
127 | */ | |
128 | #define CONFIG_BOARD_EARLY_INIT_R 1 | |
129 | ||
53d4a498 BS |
130 | /* |
131 | * Low level configuration | |
132 | */ | |
133 | ||
53d4a498 | 134 | /* |
d3afa1ee | 135 | * Clock configuration: SYS_XTALIN = 33MHz |
53d4a498 | 136 | */ |
6d0f6bcf | 137 | #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 |
53d4a498 | 138 | |
06241d50 | 139 | /* |
c99512d6 | 140 | * Set IPB speed to 100MHz |
06241d50 | 141 | */ |
6d0f6bcf | 142 | #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK |
06241d50 | 143 | |
53d4a498 BS |
144 | /* |
145 | * Memory map | |
146 | */ | |
147 | /* | |
148 | * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000. | |
149 | * Setting MBAR to otherwise will cause system hang when using SmartDMA such | |
150 | * as network commands. | |
151 | */ | |
7a8ddeea | 152 | #define CONFIG_SYS_MBAR 0xf0000000 |
6d0f6bcf | 153 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
53d4a498 BS |
154 | |
155 | /* | |
156 | * If building for running out of SDRAM, then MBAR has been set up beforehand | |
157 | * (e.g., by the BDI). Otherwise we must specify the default boot-up value of | |
158 | * MBAR, as given in the doccumentation. | |
159 | */ | |
14d0a02a | 160 | #if CONFIG_SYS_TEXT_BASE == 0x00100000 |
6d0f6bcf | 161 | #define CONFIG_SYS_DEFAULT_MBAR 0xf0000000 |
14d0a02a | 162 | #else /* CONFIG_SYS_TEXT_BASE != 0x00100000 */ |
6d0f6bcf JCPV |
163 | #define CONFIG_SYS_DEFAULT_MBAR 0x80000000 |
164 | #define CONFIG_SYS_LOWBOOT 1 | |
14d0a02a | 165 | #endif /* CONFIG_SYS_TEXT_BASE == 0x00100000 */ |
53d4a498 BS |
166 | |
167 | /* Use SRAM until RAM will be available */ | |
6d0f6bcf | 168 | #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM |
553f0982 | 169 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE |
53d4a498 | 170 | |
25ddd1fb | 171 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 172 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
53d4a498 | 173 | |
14d0a02a | 174 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf JCPV |
175 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
176 | #define CONFIG_SYS_RAMBOOT 1 | |
53d4a498 BS |
177 | #endif |
178 | ||
0ffb941c | 179 | #define CONFIG_SYS_MONITOR_LEN (384 << 10) /* 384 kB for Monitor */ |
6d0f6bcf JCPV |
180 | #define CONFIG_SYS_MALLOC_LEN (1024 << 10) /* 1 MiB for malloc() */ |
181 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* initial mem map for Linux */ | |
53d4a498 | 182 | |
53d4a498 BS |
183 | /* |
184 | * Chip selects configuration | |
185 | */ | |
186 | /* Boot Chipselect */ | |
6d0f6bcf JCPV |
187 | #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE |
188 | #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE | |
189 | #define CONFIG_SYS_BOOTCS_CFG 0x00045D00 | |
53d4a498 BS |
190 | |
191 | /* Flash memory addressing */ | |
6d0f6bcf JCPV |
192 | #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE |
193 | #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE | |
194 | #define CONFIG_SYS_CS0_CFG CONFIG_SYS_BOOTCS_CFG | |
53d4a498 BS |
195 | |
196 | /* Dual Port SRAM -- Kollmorgen Drive memory addressing */ | |
6d0f6bcf JCPV |
197 | #define CONFIG_SYS_CS1_START 0x50000000 |
198 | #define CONFIG_SYS_CS1_SIZE 0x10000 | |
199 | #define CONFIG_SYS_CS1_CFG 0x05055800 | |
53d4a498 BS |
200 | |
201 | /* Local register access */ | |
6d0f6bcf JCPV |
202 | #define CONFIG_SYS_CS2_START 0x50010000 |
203 | #define CONFIG_SYS_CS2_SIZE 0x10000 | |
204 | #define CONFIG_SYS_CS2_CFG 0x05055800 | |
53d4a498 BS |
205 | |
206 | /* Anybus CompactCom Module memory addressing */ | |
6d0f6bcf JCPV |
207 | #define CONFIG_SYS_CS3_START 0x50020000 |
208 | #define CONFIG_SYS_CS3_SIZE 0x10000 | |
209 | #define CONFIG_SYS_CS3_CFG 0x05055800 | |
53d4a498 BS |
210 | |
211 | /* No burst and dead cycle = 2 for all CSs */ | |
6d0f6bcf JCPV |
212 | #define CONFIG_SYS_CS_BURST 0x00000000 |
213 | #define CONFIG_SYS_CS_DEADCYCLE 0x22222222 | |
53d4a498 | 214 | |
53d4a498 BS |
215 | /* |
216 | * SDRAM configuration | |
217 | */ | |
d3afa1ee BS |
218 | /* 2 x MT48LC16M16A2BG-75 IT:D, CASL 3, 32 bit data bus */ |
219 | #define SDRAM_CONFIG1 0x62322900 | |
220 | #define SDRAM_CONFIG2 0x88c70000 | |
221 | #define SDRAM_CONTROL 0x504f0000 | |
222 | #define SDRAM_MODE 0x00cd0000 | |
53d4a498 | 223 | |
53d4a498 BS |
224 | /* |
225 | * Flash configuration | |
226 | */ | |
6d0f6bcf | 227 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
00b1883a | 228 | #define CONFIG_FLASH_CFI_DRIVER 1 |
6d0f6bcf JCPV |
229 | #define CONFIG_SYS_FLASH_BASE 0xff000000 |
230 | #define CONFIG_SYS_FLASH_SIZE 0x01000000 | |
231 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ | |
232 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
233 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ | |
53d4a498 BS |
234 | #define CONFIG_FLASH_16BIT /* Flash is 16-bit */ |
235 | ||
7d98ba77 PK |
236 | /* |
237 | * MTD configuration | |
238 | */ | |
68d7d651 | 239 | #define CONFIG_CMD_MTDPARTS |
942556a9 SR |
240 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
241 | #define CONFIG_FLASH_CFI_MTD | |
7d98ba77 PK |
242 | #define MTDIDS_DEFAULT "nor0=motionpro-0" |
243 | #define MTDPARTS_DEFAULT "mtdparts=motionpro-0:" \ | |
0ffb941c | 244 | "13m(fs),2m(kernel),384k(uboot)," \ |
d3afa1ee BS |
245 | "128k(env),128k(redund_env)," \ |
246 | "128k(dtb),-(user_data)" | |
53d4a498 | 247 | |
fa5c2ba1 BS |
248 | /* |
249 | * IDE/ATA configuration | |
250 | */ | |
6d0f6bcf JCPV |
251 | #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA |
252 | #define CONFIG_SYS_IDE_MAXBUS 1 | |
253 | #define CONFIG_SYS_IDE_MAXDEVICE 1 | |
fa5c2ba1 BS |
254 | #define CONFIG_IDE_PREINIT |
255 | ||
6d0f6bcf JCPV |
256 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x0060 |
257 | #define CONFIG_SYS_ATA_REG_OFFSET CONFIG_SYS_ATA_DATA_OFFSET | |
258 | #define CONFIG_SYS_ATA_STRIDE 4 | |
fa5c2ba1 | 259 | |
de1de02a PK |
260 | /* |
261 | * I2C configuration | |
262 | */ | |
263 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
6d0f6bcf JCPV |
264 | #define CONFIG_SYS_I2C_MODULE 2 /* select I2C module #2 */ |
265 | #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ | |
266 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
de1de02a | 267 | |
de1de02a PK |
268 | /* |
269 | * EEPROM configuration | |
270 | */ | |
6d0f6bcf JCPV |
271 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
272 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 1 /* 2 bytes per write cycle */ | |
273 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* 2ms/cycle + 3ms extra */ | |
de1de02a | 274 | |
de1de02a PK |
275 | /* |
276 | * RTC configuration | |
277 | */ | |
278 | #define CONFIG_RTC_DS1337 1 | |
6d0f6bcf | 279 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
de1de02a | 280 | |
a11c0b85 BS |
281 | /* |
282 | * Status LED configuration | |
283 | */ | |
a11c0b85 BS |
284 | |
285 | #define ENABLE_GPIO_OUT 0x00000024 | |
286 | #define LED_ON 0x00000010 | |
287 | ||
93b78f53 BS |
288 | /* |
289 | * Temperature sensor | |
290 | */ | |
291 | #define CONFIG_DTT_LM75 1 | |
292 | #define CONFIG_DTT_SENSORS { 0x49 } | |
293 | ||
53d4a498 BS |
294 | /* |
295 | * Environment settings | |
296 | */ | |
5a1aceb0 | 297 | #define CONFIG_ENV_IS_IN_FLASH 1 |
53d4a498 | 298 | /* This has to be a multiple of the Flash sector size */ |
6d0f6bcf | 299 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
0e8d1586 JCPV |
300 | #define CONFIG_ENV_SIZE 0x1000 |
301 | #define CONFIG_ENV_SECT_SIZE 0x20000 | |
53d4a498 | 302 | |
4520fd4d | 303 | /* Configuration of redundant environment */ |
0e8d1586 JCPV |
304 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
305 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
53d4a498 BS |
306 | |
307 | /* | |
308 | * Pin multiplexing configuration | |
309 | */ | |
310 | ||
311 | /* PSC1: UART1 | |
312 | * PSC2: GPIO (default) | |
313 | * PSC3: GPIO (default) | |
314 | * USB: 2xUART4/5 | |
315 | * Ethernet: Ethernet 100Mbit with MD | |
316 | * Timer: CAN2/GPIO | |
317 | * PSC6/IRDA: GPIO (default) | |
318 | */ | |
6d0f6bcf | 319 | #define CONFIG_SYS_GPS_PORT_CONFIG 0x1105a004 |
53d4a498 | 320 | |
c75e6396 BS |
321 | /* |
322 | * Motion-PRO's CPLD revision control register | |
323 | */ | |
6d0f6bcf | 324 | #define CPLD_REV_REGISTER (CONFIG_SYS_CS2_START + 0x06) |
c75e6396 | 325 | |
53d4a498 BS |
326 | /* |
327 | * Miscellaneous configurable options | |
328 | */ | |
6d0f6bcf | 329 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
6d0f6bcf JCPV |
330 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
331 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
332 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
333 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
53d4a498 | 334 | |
6d0f6bcf JCPV |
335 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
336 | #define CONFIG_SYS_MEMTEST_END 0x03e00000 /* 1 ... 62 MiB in DRAM */ | |
337 | #define CONFIG_SYS_ALT_MEMTEST | |
53d4a498 | 338 | |
6d0f6bcf | 339 | #define CONFIG_SYS_LOAD_ADDR 0x200000 /* default kernel load addr */ |
53d4a498 | 340 | |
53d4a498 BS |
341 | /* |
342 | * Various low-level settings | |
343 | */ | |
6d0f6bcf JCPV |
344 | #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI |
345 | #define CONFIG_SYS_HID0_FINAL HID0_ICE | |
53d4a498 | 346 | |
6d0f6bcf | 347 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
53d4a498 | 348 | |
53d4a498 | 349 | /* Not needed for MPC 5xxx U-Boot, but used by tools/updater */ |
6d0f6bcf | 350 | #define CONFIG_SYS_RESET_ADDRESS 0xfff00100 |
53d4a498 | 351 | |
1f1369c3 BS |
352 | #define OF_CPU "PowerPC,5200@0" |
353 | #define OF_SOC "soc5200@f0000000" | |
354 | #define OF_TBCLK (bd->bi_busfreq / 4) | |
7049288f | 355 | #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" |
1f1369c3 | 356 | |
53d4a498 | 357 | #endif /* __CONFIG_H */ |