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c474a8eb MK |
1 | /* |
2 | * Copyright (C) 2009 Samsung Electronics | |
3 | * Minkyu Kang <mk7.kang@samsung.com> | |
4 | * Kyungmin Park <kyungmin.park@samsung.com> | |
5 | * | |
6 | * Configuation settings for the SAMSUNG Universal (s5pc100) board. | |
7 | * | |
1a459660 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
c474a8eb MK |
9 | */ |
10 | ||
11 | #ifndef __CONFIG_H | |
12 | #define __CONFIG_H | |
13 | ||
14 | /* High Level Configuration Options */ | |
c474a8eb | 15 | #define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */ |
889a275d | 16 | #define CONFIG_S5P 1 /* which is in a S5P Family */ |
c474a8eb MK |
17 | #define CONFIG_S5PC110 1 /* which is in a S5PC110 */ |
18 | #define CONFIG_MACH_GONI 1 /* working with Goni */ | |
19 | ||
3709844f AA |
20 | #define CONFIG_SYS_CACHELINE_SIZE 64 |
21 | ||
a45ddf7a | 22 | #include <linux/sizes.h> |
c474a8eb MK |
23 | #include <asm/arch/cpu.h> /* get chip and board defs */ |
24 | ||
25 | #define CONFIG_ARCH_CPU_INIT | |
26 | #define CONFIG_DISPLAY_CPUINFO | |
27 | #define CONFIG_DISPLAY_BOARDINFO | |
28 | ||
c474a8eb MK |
29 | /* input clock of PLL: has 24MHz input clock at S5PC110 */ |
30 | #define CONFIG_SYS_CLK_FREQ_C110 24000000 | |
31 | ||
32 | /* DRAM Base */ | |
33 | #define CONFIG_SYS_SDRAM_BASE 0x30000000 | |
34 | ||
35bea619 MK |
35 | /* Text Base */ |
36 | #define CONFIG_SYS_TEXT_BASE 0x34800000 | |
37 | ||
c474a8eb MK |
38 | #define CONFIG_SETUP_MEMORY_TAGS |
39 | #define CONFIG_CMDLINE_TAG | |
2ac9a35b | 40 | #define CONFIG_REVISION_TAG |
c474a8eb MK |
41 | #define CONFIG_INITRD_TAG |
42 | #define CONFIG_CMDLINE_EDITING | |
43 | ||
2ecd7797 | 44 | /* Size of malloc() pool before and after relocation */ |
2ecd7797 | 45 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 << 20)) |
a45ddf7a | 46 | |
c474a8eb MK |
47 | /* |
48 | * select serial console configuration | |
49 | */ | |
50 | #define CONFIG_SERIAL2 1 /* use SERIAL2 */ | |
c474a8eb MK |
51 | #define CONFIG_BAUDRATE 115200 |
52 | ||
87f314e9 | 53 | /* MMC */ |
7d2d58b4 JC |
54 | #define CONFIG_GENERIC_MMC |
55 | #define CONFIG_MMC | |
56 | #define CONFIG_SDHCI | |
57 | #define CONFIG_S5P_SDHCI | |
311757be | 58 | #define SDHCI_MAX_HOSTS 4 |
87f314e9 | 59 | |
96caf02f MK |
60 | /* PWM */ |
61 | #define CONFIG_PWM 1 | |
62 | ||
c474a8eb MK |
63 | #define CONFIG_SYS_NO_FLASH 1 |
64 | ||
c474a8eb MK |
65 | #define CONFIG_CMD_CACHE |
66 | #define CONFIG_CMD_REGINFO | |
67 | #define CONFIG_CMD_ONENAND | |
87f314e9 | 68 | #define CONFIG_CMD_MMC |
2d281b32 | 69 | #define CONFIG_CMD_DFU |
a3c274de | 70 | #define CONFIG_CMD_GPT |
c474a8eb | 71 | |
2d281b32 | 72 | /* USB Composite download gadget - g_dnl */ |
01acd6ab | 73 | #define CONFIG_USB_FUNCTION_DFU |
2d281b32 | 74 | #define CONFIG_DFU_MMC |
0fabb6af ŁM |
75 | #define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M |
76 | #define DFU_DEFAULT_POLL_TIMEOUT 300 | |
77 | ||
78 | /* TIZEN THOR downloader support */ | |
79 | #define CONFIG_CMD_THOR_DOWNLOAD | |
01acd6ab | 80 | #define CONFIG_USB_FUNCTION_THOR |
c474a8eb | 81 | |
2d281b32 MZ |
82 | /* USB Samsung's IDs */ |
83 | #define CONFIG_G_DNL_VENDOR_NUM 0x04E8 | |
84 | #define CONFIG_G_DNL_PRODUCT_NUM 0x6601 | |
0fabb6af ŁM |
85 | #define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM |
86 | #define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D | |
124c5998 ŁM |
87 | #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 |
88 | #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 | |
2d281b32 | 89 | #define CONFIG_G_DNL_MANUFACTURER "Samsung" |
c474a8eb MK |
90 | |
91 | /* Actual modem binary size is 16MiB. Add 2MiB for bad block handling */ | |
92 | #define MTDIDS_DEFAULT "onenand0=samsung-onenand" | |
93 | #define MTDPARTS_DEFAULT "mtdparts=samsung-onenand:1m(bootloader)"\ | |
94 | ",256k(params)"\ | |
95 | ",2816k(config)"\ | |
96 | ",8m(csa)"\ | |
97 | ",7m(kernel)"\ | |
98 | ",1m(log)"\ | |
99 | ",12m(modem)"\ | |
a45ddf7a | 100 | ",60m(qboot)\0" |
c474a8eb | 101 | |
2d281b32 MZ |
102 | #define CONFIG_ZERO_BOOTDELAY_CHECK |
103 | ||
104 | /* partitions definitions */ | |
105 | #define PARTS_CSA "csa-mmc" | |
106 | #define PARTS_BOOTLOADER "u-boot" | |
107 | #define PARTS_BOOT "boot" | |
108 | #define PARTS_ROOT "platform" | |
109 | #define PARTS_DATA "data" | |
110 | #define PARTS_CSC "csc" | |
111 | #define PARTS_UMS "ums" | |
112 | ||
113 | #define CONFIG_DFU_ALT \ | |
114 | "u-boot raw 0x80 0x400;" \ | |
115 | "uImage ext4 0 2;" \ | |
116 | "exynos3-goni.dtb ext4 0 2;" \ | |
117 | ""PARTS_ROOT" part 0 5\0" | |
118 | ||
119 | #define PARTS_DEFAULT \ | |
120 | "uuid_disk=${uuid_gpt_disk};" \ | |
121 | "name="PARTS_CSA",size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \ | |
122 | "name="PARTS_BOOTLOADER",size=60MiB," \ | |
123 | "uuid=${uuid_gpt_"PARTS_BOOTLOADER"};" \ | |
124 | "name="PARTS_BOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \ | |
125 | "name="PARTS_ROOT",size=1GiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \ | |
126 | "name="PARTS_DATA",size=3GiB,uuid=${uuid_gpt_"PARTS_DATA"};" \ | |
127 | "name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \ | |
128 | "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \ | |
c474a8eb | 129 | |
a45ddf7a | 130 | #define CONFIG_BOOTCOMMAND "run mmcboot" |
c474a8eb MK |
131 | |
132 | #define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" | |
133 | ||
a45ddf7a | 134 | #define CONFIG_RAMDISK_BOOT "root=/dev/ram0 rw rootfstype=ext4" \ |
c474a8eb MK |
135 | " ${console} ${meminfo}" |
136 | ||
137 | #define CONFIG_COMMON_BOOT "${console} ${meminfo} ${mtdparts}" | |
138 | ||
a45ddf7a MZ |
139 | #define CONFIG_BOOTARGS "root=/dev/mtdblock8 rootfstype=ext4 " \ |
140 | CONFIG_COMMON_BOOT | |
c474a8eb MK |
141 | |
142 | #define CONFIG_UPDATEB "updateb=onenand erase 0x0 0x100000;" \ | |
143 | " onenand write 0x32008000 0x0 0x100000\0" | |
144 | ||
2ac9a35b PW |
145 | #define CONFIG_MISC_COMMON |
146 | #define CONFIG_MISC_INIT_R | |
147 | ||
c474a8eb MK |
148 | #define CONFIG_ENV_OVERWRITE |
149 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV | |
2ac9a35b PW |
150 | #define CONFIG_ENV_VARS_UBOOT_CONFIG |
151 | #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG | |
c474a8eb MK |
152 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
153 | CONFIG_UPDATEB \ | |
154 | "updatek=" \ | |
155 | "onenand erase 0xc00000 0x600000;" \ | |
156 | "onenand write 0x31008000 0xc00000 0x600000\0" \ | |
157 | "updateu=" \ | |
158 | "onenand erase 0x01560000 0x1eaa0000;" \ | |
159 | "onenand write 0x32000000 0x1260000 0x8C0000\0" \ | |
160 | "bootk=" \ | |
a45ddf7a | 161 | "run loaduimage;" \ |
c474a8eb MK |
162 | "bootm 0x30007FC0\0" \ |
163 | "flashboot=" \ | |
164 | "set bootargs root=/dev/mtdblock${bootblock} " \ | |
a45ddf7a | 165 | "rootfstype=${rootfstype} ${opts} " \ |
c474a8eb MK |
166 | "${lcdinfo} " CONFIG_COMMON_BOOT "; run bootk\0" \ |
167 | "ubifsboot=" \ | |
168 | "set bootargs root=ubi0!rootfs rootfstype=ubifs " \ | |
a45ddf7a | 169 | "${opts} ${lcdinfo} " \ |
c474a8eb MK |
170 | CONFIG_COMMON_BOOT "; run bootk\0" \ |
171 | "tftpboot=" \ | |
172 | "set bootargs root=ubi0!rootfs rootfstype=ubifs " \ | |
a45ddf7a MZ |
173 | "${opts} ${lcdinfo} " CONFIG_COMMON_BOOT \ |
174 | "; tftp 0x30007FC0 uImage; bootm 0x30007FC0\0" \ | |
c474a8eb MK |
175 | "ramboot=" \ |
176 | "set bootargs " CONFIG_RAMDISK_BOOT \ | |
a45ddf7a | 177 | "initrd=0x33000000,8M ramdisk=8192\0" \ |
c474a8eb | 178 | "mmcboot=" \ |
a45ddf7a MZ |
179 | "set bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ |
180 | "rootfstype=${rootfstype} ${opts} ${lcdinfo} " \ | |
c474a8eb MK |
181 | CONFIG_COMMON_BOOT "; run bootk\0" \ |
182 | "boottrace=setenv opts initcall_debug; run bootcmd\0" \ | |
183 | "bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \ | |
184 | "verify=n\0" \ | |
a45ddf7a | 185 | "rootfstype=ext4\0" \ |
c474a8eb | 186 | "console=" CONFIG_DEFAULT_CONSOLE \ |
c474a8eb | 187 | "meminfo=mem=80M mem=256M@0x40000000 mem=128M@0x50000000\0" \ |
2d281b32 | 188 | "loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x30007FC0 uImage\0" \ |
a45ddf7a MZ |
189 | "mmcdev=0\0" \ |
190 | "mmcbootpart=2\0" \ | |
191 | "mmcrootpart=5\0" \ | |
2d281b32 | 192 | "partitions=" PARTS_DEFAULT \ |
c474a8eb MK |
193 | "bootblock=9\0" \ |
194 | "ubiblock=8\0" \ | |
195 | "ubi=enabled\0" \ | |
2d281b32 MZ |
196 | "opts=always_resume=1\0" \ |
197 | "dfu_alt_info=" CONFIG_DFU_ALT "\0" | |
c474a8eb | 198 | |
c474a8eb MK |
199 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
200 | #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ | |
c474a8eb MK |
201 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
202 | #define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ | |
203 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
204 | /* Boot Argument Buffer Size */ | |
205 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
206 | /* memtest works on */ | |
207 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE | |
208 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000) | |
209 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4000000) | |
210 | ||
c474a8eb MK |
211 | /* Goni has 3 banks of DRAM, but swap the bank */ |
212 | #define CONFIG_NR_DRAM_BANKS 3 | |
213 | #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* OneDRAM Bank #0 */ | |
214 | #define PHYS_SDRAM_1_SIZE (80 << 20) /* 80 MB in Bank #0 */ | |
215 | #define PHYS_SDRAM_2 0x40000000 /* mDDR DMC1 Bank #1 */ | |
216 | #define PHYS_SDRAM_2_SIZE (256 << 20) /* 256 MB in Bank #1 */ | |
217 | #define PHYS_SDRAM_3 0x50000000 /* mDDR DMC2 Bank #2 */ | |
218 | #define PHYS_SDRAM_3_SIZE (128 << 20) /* 128 MB in Bank #2 */ | |
219 | ||
220 | #define CONFIG_SYS_MONITOR_BASE 0x00000000 | |
221 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 KiB */ | |
222 | ||
223 | /* FLASH and environment organization */ | |
34ecd694 ŁM |
224 | #define CONFIG_MMC_DEFAULT_DEV 0 |
225 | #define CONFIG_ENV_IS_IN_MMC | |
226 | #define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV | |
227 | #define CONFIG_ENV_SIZE 4096 | |
228 | #define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */ | |
229 | #define CONFIG_ENV_OVERWRITE | |
c474a8eb MK |
230 | |
231 | #define CONFIG_USE_ONENAND_BOARD_INIT | |
232 | #define CONFIG_SAMSUNG_ONENAND 1 | |
233 | #define CONFIG_SYS_ONENAND_BASE 0xB0000000 | |
234 | ||
235 | #define CONFIG_DOS_PARTITION 1 | |
236 | ||
a45ddf7a MZ |
237 | #define CONFIG_CMD_FAT |
238 | #define CONFIG_CMD_EXT4 | |
2d281b32 | 239 | #define CONFIG_CMD_EXT4_WRITE |
a45ddf7a MZ |
240 | |
241 | /* write support for filesystems */ | |
242 | #define CONFIG_FAT_WRITE | |
243 | #define CONFIG_EXT4_WRITE | |
244 | ||
a3c274de MZ |
245 | /* GPT */ |
246 | #define CONFIG_EFI_PARTITION | |
247 | #define CONFIG_PARTITION_UUIDS | |
248 | ||
177feff3 MK |
249 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000) |
250 | ||
7cb54948 ŁM |
251 | #define CONFIG_SYS_CACHELINE_SIZE 64 |
252 | ||
be3b51aa ŁM |
253 | #define CONFIG_POWER |
254 | #define CONFIG_POWER_I2C | |
255 | #define CONFIG_POWER_MAX8998 | |
2a7dd9d7 | 256 | |
85776b02 ŁM |
257 | #include <asm/arch/gpio.h> |
258 | /* | |
259 | * I2C Settings | |
260 | */ | |
9b97b727 AS |
261 | #define CONFIG_SOFT_I2C_GPIO_SCL S5PC110_GPIO_J43 |
262 | #define CONFIG_SOFT_I2C_GPIO_SDA S5PC110_GPIO_J40 | |
85776b02 | 263 | |
ea818dbb HS |
264 | #define CONFIG_SYS_I2C |
265 | #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ | |
266 | #define CONFIG_SYS_I2C_SOFT_SPEED 50000 | |
267 | #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F | |
85776b02 | 268 | #define CONFIG_I2C_MULTI_BUS |
4d38395c RB |
269 | #define CONFIG_SYS_I2C_INIT_BOARD |
270 | ||
85776b02 | 271 | #define CONFIG_SYS_MAX_I2C_BUS 7 |
e30824f4 | 272 | #define CONFIG_USB_GADGET_DWC2_OTG_PHY |
d2f588f3 | 273 | #define CONFIG_CMD_USB_MASS_STORAGE |
01acd6ab | 274 | #define CONFIG_USB_FUNCTION_MASS_STORAGE |
85776b02 | 275 | |
c474a8eb | 276 | #endif /* __CONFIG_H */ |