[people/ms/u-boot.git] / include / configs / sama5d3xek.h

/*
 * Configuation settings for the SAMA5D3xEK board.
 *
 * Copyright (C) 2012 - 2013 Atmel
 *
 * based on at91sam9m10g45ek.h by:
 * Stelian Pop <stelian@popies.net>
 * Lead Tech Design <www.leadtechdesign.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include "at91-sama5_common.h"

#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG

/*
 * This needs to be defined for the OHCI code to work but it is defined as
 * ATMEL_ID_UHPHS in the CPU specific header files.
 */
#define ATMEL_ID_UHP			ATMEL_ID_UHPHS

/*
 * Specify the clock enable bit in the PMC_SCER register.
 */
#define ATMEL_PMC_UHP			AT91SAM926x_PMC_UHP

/* LCD */
#define LCD_BPP				LCD_COLOR16
#define LCD_OUTPUT_BPP                  24
#define CONFIG_LCD_LOGO
#define CONFIG_LCD_INFO
#define CONFIG_LCD_INFO_BELOW_LOGO
#define CONFIG_ATMEL_HLCD
#define CONFIG_ATMEL_LCD_RGB565

/* board specific (not enough SRAM) */
#define CONFIG_SAMA5D3_LCD_BASE		0x23E00000

/* NOR flash */
#ifdef CONFIG_MTD_NOR_FLASH
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_FLASH_BASE		0x10000000
#define CONFIG_SYS_MAX_FLASH_SECT	131
#define CONFIG_SYS_MAX_FLASH_BANKS	1
#endif

/* SDRAM */
#define CONFIG_NR_DRAM_BANKS		1
#define CONFIG_SYS_SDRAM_BASE           ATMEL_BASE_DDRCS
#define CONFIG_SYS_SDRAM_SIZE		0x20000000

#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_INIT_SP_ADDR		0x318000
#else
#define CONFIG_SYS_INIT_SP_ADDR \
	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
#endif

/* SerialFlash */

#ifdef CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED		30000000
#endif

/* NAND flash */
#define CONFIG_CMD_NAND

#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_ATMEL
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
#define CONFIG_SYS_NAND_ONFI_DETECTION
/* PMECC & PMERRLOC */
#define CONFIG_ATMEL_NAND_HWECC
#define CONFIG_ATMEL_NAND_HW_PMECC
#define CONFIG_PMECC_CAP		4
#define CONFIG_PMECC_SECTOR_SIZE	512
#define CONFIG_CMD_NAND_TRIMFFS
#endif

#define CONFIG_PHY_MICREL_KSZ9021

/* USB */

#ifdef CONFIG_CMD_USB
#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_USB_OHCI_CPU_INIT
#define CONFIG_SYS_USB_OHCI_REGS_BASE		ATMEL_BASE_OHCI
#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"sama5d3"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	3
#endif

#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
#define CONFIG_FAT_WRITE
#endif

#define CONFIG_SYS_LOAD_ADDR			0x22000000 /* load address */

#ifdef CONFIG_SYS_USE_SERIALFLASH
/* override the bootcmd, bootargs and other configuration for spi flash env*/
#elif CONFIG_SYS_USE_NANDFLASH
/* override the bootcmd, bootargs and other configuration nandflash env */
#elif CONFIG_SYS_USE_MMC
/* override the bootcmd, bootargs and other configuration for sd/mmc env */
#else
#define CONFIG_ENV_IS_NOWHERE
#endif

/* SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE		0x300000
#define CONFIG_SPL_MAX_SIZE		0x18000
#define CONFIG_SPL_BSS_START_ADDR	0x20000000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
#define CONFIG_SYS_SPL_MALLOC_START	0x20080000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000

#define CONFIG_SYS_MONITOR_LEN		(512 << 10)

#ifdef CONFIG_SYS_USE_MMC
#define CONFIG_SPL_LDSCRIPT		arch/arm/mach-at91/armv7/u-boot-spl.lds
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"

#elif CONFIG_SYS_USE_NANDFLASH
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x40000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_SIZE	0x800
#define CONFIG_SYS_NAND_PAGE_COUNT	64
#define CONFIG_SYS_NAND_OOBSIZE		64
#define CONFIG_SYS_NAND_BLOCK_SIZE	0x20000
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0x0
#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER

#elif CONFIG_SYS_USE_SERIALFLASH
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x10000

#endif

#endif
Commit	Line	Data
3225f34e BS	1	/*
	2	* Configuation settings for the SAMA5D3xEK board.
	3	*
	4	* Copyright (C) 2012 - 2013 Atmel
	5	*
	6	* based on at91sam9m10g45ek.h by:
	7	* Stelian Pop <stelian@popies.net>
	8	* Lead Tech Design <www.leadtechdesign.com>
	9	*
1a459660	10	* SPDX-License-Identifier: GPL-2.0+
3225f34e BS	11	*/
	12
	13	#ifndef __CONFIG_H
	14	#define __CONFIG_H
	15
b2d387bc	16	#include "at91-sama5_common.h"
3225f34e	17
89a3658a WJ	18	#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
89a3658a WJ	19
3225f34e BS	20	/*
	21	* This needs to be defined for the OHCI code to work but it is defined as
	22	* ATMEL_ID_UHPHS in the CPU specific header files.
	23	*/
	24	#define ATMEL_ID_UHP ATMEL_ID_UHPHS
	25
	26	/*
	27	* Specify the clock enable bit in the PMC_SCER register.
	28	*/
	29	#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
	30
	31	/* LCD */
3225f34e BS	32	#define LCD_BPP LCD_COLOR16
	33	#define LCD_OUTPUT_BPP 24
	34	#define CONFIG_LCD_LOGO
3225f34e BS	35	#define CONFIG_LCD_INFO
3225f34e BS	36	#define CONFIG_LCD_INFO_BELOW_LOGO
3225f34e BS	37	#define CONFIG_ATMEL_HLCD
3225f34e BS	38	#define CONFIG_ATMEL_LCD_RGB565
3225f34e BS	39
	40	/* board specific (not enough SRAM) */
	41	#define CONFIG_SAMA5D3_LCD_BASE 0x23E00000
	42
d6b79434	43	/* NOR flash */
e856bdcf	44	#ifdef CONFIG_MTD_NOR_FLASH
d6b79434 BS	45	#define CONFIG_FLASH_CFI_DRIVER
	46	#define CONFIG_SYS_FLASH_CFI
	47	#define CONFIG_SYS_FLASH_PROTECTION
	48	#define CONFIG_SYS_FLASH_BASE 0x10000000
	49	#define CONFIG_SYS_MAX_FLASH_SECT 131
	50	#define CONFIG_SYS_MAX_FLASH_BANKS 1
d6b79434	51	#endif
3225f34e	52
3225f34e BS	53	/* SDRAM */
	54	#define CONFIG_NR_DRAM_BANKS 1
	55	#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
	56	#define CONFIG_SYS_SDRAM_SIZE 0x20000000
	57
c5e8885a	58	#ifdef CONFIG_SPL_BUILD
a97cb061	59	#define CONFIG_SYS_INIT_SP_ADDR 0x318000
c5e8885a	60	#else
3225f34e	61	#define CONFIG_SYS_INIT_SP_ADDR \
a97cb061	62	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
c5e8885a	63	#endif
3225f34e BS	64
3225f34e BS	65	/* SerialFlash */
3225f34e BS	66
3225f34e BS	67	#ifdef CONFIG_CMD_SF
3225f34e BS	68	#define CONFIG_SF_DEFAULT_SPEED 30000000
	69	#endif
	70
	71	/* NAND flash */
	72	#define CONFIG_CMD_NAND
	73
	74	#ifdef CONFIG_CMD_NAND
3225f34e BS	75	#define CONFIG_NAND_ATMEL
	76	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	77	#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
	78	/* our ALE is AD21 */
	79	#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
	80	/* our CLE is AD22 */
	81	#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
	82	#define CONFIG_SYS_NAND_ONFI_DETECTION
	83	/* PMECC & PMERRLOC */
	84	#define CONFIG_ATMEL_NAND_HWECC
	85	#define CONFIG_ATMEL_NAND_HW_PMECC
	86	#define CONFIG_PMECC_CAP 4
	87	#define CONFIG_PMECC_SECTOR_SIZE 512
3225f34e BS	88	#define CONFIG_CMD_NAND_TRIMFFS
	89	#endif
	90
e08d6f3a	91	#define CONFIG_PHY_MICREL_KSZ9021
3225f34e	92
3225f34e	93	/* USB */
3225f34e BS	94
3225f34e BS	95	#ifdef CONFIG_CMD_USB
dcd2f1a0	96	#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
3225f34e BS	97	#define CONFIG_USB_OHCI_NEW
	98	#define CONFIG_SYS_USB_OHCI_CPU_INIT
	99	#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI
	100	#define CONFIG_SYS_USB_OHCI_SLOT_NAME "sama5d3"
	101	#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
3225f34e BS	102	#endif
	103
	104	#if defined(CONFIG_CMD_USB) \|\| defined(CONFIG_CMD_MMC)
a248558a	105	#define CONFIG_FAT_WRITE
3225f34e BS	106	#endif
	107
	108	#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
	109
	110	#ifdef CONFIG_SYS_USE_SERIALFLASH
7a53b954	111	/* override the bootcmd, bootargs and other configuration for spi flash env*/
3225f34e	112	#elif CONFIG_SYS_USE_NANDFLASH
dc018fef	113	/* override the bootcmd, bootargs and other configuration nandflash env */
3225f34e	114	#elif CONFIG_SYS_USE_MMC
372ca03f	115	/* override the bootcmd, bootargs and other configuration for sd/mmc env */
3225f34e	116	#else
a4c79b3a	117	#define CONFIG_ENV_IS_NOWHERE
3225f34e BS	118	#endif
3225f34e BS	119
c5e8885a	120	/* SPL */
c5e8885a BS	121	#define CONFIG_SPL_FRAMEWORK
c5e8885a BS	122	#define CONFIG_SPL_TEXT_BASE 0x300000
a97cb061	123	#define CONFIG_SPL_MAX_SIZE 0x18000
c5e8885a BS	124	#define CONFIG_SPL_BSS_START_ADDR 0x20000000
	125	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
	126	#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
	127	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
	128
8a45b0ba BS	129	#define CONFIG_SYS_MONITOR_LEN (512 << 10)
8a45b0ba BS	130
c5e8885a	131	#ifdef CONFIG_SYS_USE_MMC
993ea97e	132	#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/armv7/u-boot-spl.lds
e2ccdf89	133	#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
205b4f33	134	#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
8a45b0ba	135
27019e4a	136	#elif CONFIG_SYS_USE_NANDFLASH
27019e4a BS	137	#define CONFIG_SPL_NAND_DRIVERS
	138	#define CONFIG_SPL_NAND_BASE
	139	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
	140	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	141	#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
	142	#define CONFIG_SYS_NAND_PAGE_COUNT 64
	143	#define CONFIG_SYS_NAND_OOBSIZE 64
	144	#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
	145	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
e166a831	146	#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
27019e4a	147
8a45b0ba	148	#elif CONFIG_SYS_USE_SERIALFLASH
8a45b0ba	149	#define CONFIG_SPL_SPI_LOAD
a97cb061	150	#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000
8a45b0ba	151
c5e8885a BS	152	#endif
c5e8885a BS	153
3225f34e	154	#endif