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rename CFG_ macros to CONFIG_SYS
[people/ms/u-boot.git] / include / configs / sequoia.h
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887e2ec9 1/*
fc84a849 2 * (C) Copyright 2006-2008
887e2ec9
SR		 3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * (C) Copyright 2006
6 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
7 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
214398d9 25/*
e802594b 26 * sequoia.h - configuration for Sequoia & Rainier boards
214398d9 27 */
887e2ec9
SR		 28#ifndef __CONFIG_H
29#define __CONFIG_H
30
214398d9 31/*
887e2ec9 32 * High Level Configuration Options
214398d9 33 */
e802594b 34/* This config file is used for Sequoia (440EPx) and Rainier (440GRx) */
854bc8da 35#ifndef CONFIG_RAINIER
214398d9 36#define CONFIG_440EPX 1 /* Specific PPC440EPx */
72675dc6 37#define CONFIG_HOSTNAME sequoia
854bc8da 38#else
214398d9 39#define CONFIG_440GRX 1 /* Specific PPC440GRx */
72675dc6 40#define CONFIG_HOSTNAME rainier
854bc8da 41#endif
214398d9
LJ		 42#define CONFIG_440 1 /* ... PPC440 family */
43#define CONFIG_4xx 1 /* ... PPC4xx family */
72675dc6
SR		 44
45/*
46 * Include common defines/options for all AMCC eval boards
47 */
48#include "amcc-common.h"
49
e3b8c78b 50/* Detect Sequoia PLL input clock automatically via CPLD bit */
6d0f6bcf 51#define CONFIG_SYS_CLK_FREQ ((in8(CONFIG_SYS_BCSR_BASE + 3) & 0x80) ? \
193b4a3b 52 33333333 : 33000000)
887e2ec9 53
bc778812
AG		 54/*
55 * Define this if you want support for video console with radeon 9200 pci card
56 * Also set TEXT_BASE to 0xFFF80000 in board/amcc/sequoia/config.mk in this case
57 */
58#undef CONFIG_VIDEO
59
60#ifdef CONFIG_VIDEO
d25dfe08
SR		 61/*
62 * 44x dcache supported is working now on sequoia, but we don't enable
63 * it yet since it needs further testing
64 */
214398d9 65#define CONFIG_4xx_DCACHE /* enable dcache */
d25dfe08
SR		 66#endif
67
214398d9
LJ		 68#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
69#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
887e2ec9 70
214398d9
LJ		 71/*
72 * Base addresses -- Note these are effective addresses where the actual
73 * resources get mapped (not physical addresses).
74 */
6d0f6bcf
JCPV		 75#define CONFIG_SYS_TLB_FOR_BOOT_FLASH 0x0003
76#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
77#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */
78#define CONFIG_SYS_NAND_ADDR 0xd0000000 /* NAND Flash */
79#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
80#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_OCM_BASE
81#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
82#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
83#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
84#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
85#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
887e2ec9
SR		 86
87/* Don't change either of these */
6d0f6bcf 88#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
887e2ec9 89
6d0f6bcf
JCPV		 90#define CONFIG_SYS_USB2D0_BASE 0xe0000100
91#define CONFIG_SYS_USB_DEVICE 0xe0000000
92#define CONFIG_SYS_USB_HOST 0xe0000400
93#define CONFIG_SYS_BCSR_BASE 0xc0000000
887e2ec9 94
214398d9 95/*
887e2ec9 96 * Initial RAM & stack pointer
214398d9 97 */
887e2ec9 98/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
6d0f6bcf
JCPV		 99#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
100#define CONFIG_SYS_INIT_RAM_END (4 << 10)
101#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */
102#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
103#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR
887e2ec9 104
214398d9 105/*
887e2ec9 106 * Serial Port
214398d9 107 */
6d0f6bcf 108#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
887e2ec9
SR		 109/* define this if you want console on UART1 */
110#undef CONFIG_UART1_CONSOLE
111
214398d9 112/*
887e2ec9 113 * Environment
214398d9 114 */
d12ae808 115#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
5a1aceb0 116#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environ vars */
887e2ec9 117#else
51bfee19 118#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environ vars */
0e8d1586 119#define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */
887e2ec9 120#endif
887e2ec9 121
214398d9 122/*
887e2ec9 123 * FLASH related
214398d9 124 */
6d0f6bcf 125#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
00b1883a 126#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
887e2ec9 127
6d0f6bcf 128#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
887e2ec9 129
6d0f6bcf
JCPV		 130#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
131#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
887e2ec9 132
6d0f6bcf
JCPV		 133#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
134#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
887e2ec9 135
6d0f6bcf
JCPV		 136#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
137#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
887e2ec9 138
6d0f6bcf
JCPV		 139#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
140#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
887e2ec9 141
5a1aceb0 142#ifdef CONFIG_ENV_IS_IN_FLASH
0e8d1586 143#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
6d0f6bcf 144#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
0e8d1586 145#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
887e2ec9
SR		 146
147/* Address and size of Redundant Environment Sector */
0e8d1586
JCPV		 148#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
149#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
887e2ec9
SR		 150#endif
151
887e2ec9
SR		 152/*
153 * IPL (Initial Program Loader, integrated inside CPU)
154 * Will load first 4k from NAND (SPL) into cache and execute it from there.
155 *
156 * SPL (Secondary Program Loader)
157 * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
158 * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
159 * controller and the NAND controller so that the special U-Boot image can be
160 * loaded from NAND to SDRAM.
161 *
162 * NUB (NAND U-Boot)
163 * This NAND U-Boot (NUB) is a special U-Boot version which can be started
164 * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
165 *
166 * On 440EPx the SPL is copied to SDRAM before the NAND controller is
167 * set up. While still running from cache, I experienced problems accessing
168 * the NAND controller. sr - 2006-08-25
169 */
6d0f6bcf
JCPV		 170#define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
171#define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
172#define CONFIG_SYS_NAND_BOOT_SPL_DST (CONFIG_SYS_OCM_BASE + (12 << 10)) /* Copy SPL here */
173#define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
174#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from */
214398d9 175 /* this addr */
6d0f6bcf 176#define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
887e2ec9
SR		 177
178/*
179 * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
180 */
6d0f6bcf
JCPV		 181#define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
182#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) /* Size of RAM U-Boot image */
887e2ec9
SR		 183
184/*
185 * Now the NAND chip has to be defined (no autodetection used!)
186 */
6d0f6bcf
JCPV		 187#define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */
188#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
189#define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */
190#define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
191#undef CONFIG_SYS_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
192
193#define CONFIG_SYS_NAND_ECCSIZE 256
194#define CONFIG_SYS_NAND_ECCBYTES 3
195#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
196#define CONFIG_SYS_NAND_OOBSIZE 16
197#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
198#define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
9d909604 199
51bfee19 200#ifdef CONFIG_ENV_IS_IN_NAND
d12ae808
SR		 201/*
202 * For NAND booting the environment is embedded in the U-Boot image. Please take
203 * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
204 */
6d0f6bcf
JCPV		 205#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
206#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
0e8d1586 207#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
887e2ec9
SR		 208#endif
209
214398d9 210/*
887e2ec9 211 * DDR SDRAM
214398d9 212 */
6d0f6bcf 213#define CONFIG_SYS_MBYTES_SDRAM (256) /* 256MB */
02388983 214#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
214398d9 215#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
02388983 216#endif
6d0f6bcf 217#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
14f73ca6 218 /* 440EPx errata CHIP 11 */
887e2ec9 219
214398d9 220/*
887e2ec9 221 * I2C
214398d9 222 */
6d0f6bcf 223#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
887e2ec9 224
6d0f6bcf
JCPV		 225#define CONFIG_SYS_I2C_MULTI_EEPROMS
226#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
227#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
228#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
229#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
887e2ec9 230
887e2ec9 231/* I2C SYSMON (LM75, AD7414 is almost compatible) */
214398d9
LJ		 232#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
233#define CONFIG_DTT_AD7414 1 /* use AD7414 */
234#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
6d0f6bcf
JCPV		 235#define CONFIG_SYS_DTT_MAX_TEMP 70
236#define CONFIG_SYS_DTT_LOW_TEMP -30
237#define CONFIG_SYS_DTT_HYSTERESIS 3
887e2ec9 238
72675dc6
SR		 239/*
240 * Default environment variables
241 */
887e2ec9 242#define CONFIG_EXTRA_ENV_SETTINGS \
72675dc6
SR		 243 CONFIG_AMCC_DEF_ENV \
244 CONFIG_AMCC_DEF_ENV_POWERPC \
245 CONFIG_AMCC_DEF_ENV_PPC_OLD \
246 CONFIG_AMCC_DEF_ENV_NOR_UPD \
247 CONFIG_AMCC_DEF_ENV_NAND_UPD \
4ef62514
SR		 248 "kernel_addr=FC000000\0" \
249 "ramdisk_addr=FC180000\0" \
887e2ec9 250 ""
887e2ec9
SR		 251
252#define CONFIG_M88E1111_PHY 1
253#define CONFIG_IBM_EMAC4_V4 1
887e2ec9
SR		 254#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
255
214398d9 256#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
887e2ec9
SR		 257#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
258
259#define CONFIG_HAS_ETH0
887e2ec9
SR		 260#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
261#define CONFIG_PHY1_ADDR 1
262
263/* USB */
854bc8da 264#ifdef CONFIG_440EPX
2d146843 265#define CONFIG_USB_OHCI_NEW
887e2ec9 266#define CONFIG_USB_STORAGE
6d0f6bcf 267#define CONFIG_SYS_OHCI_BE_CONTROLLER
2d146843 268
6d0f6bcf
JCPV		 269#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
270#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
271#define CONFIG_SYS_USB_OHCI_REGS_BASE CONFIG_SYS_USB_HOST
272#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440"
273#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
887e2ec9
SR		 274
275/* Comment this out to enable USB 1.1 device */
276#define USB_2_0_DEVICE
277
854bc8da
SR		 278#endif /* CONFIG_440EPX */
279
887e2ec9
SR		 280/* Partitions */
281#define CONFIG_MAC_PARTITION
282#define CONFIG_DOS_PARTITION
283#define CONFIG_ISO_PARTITION
284
079a136c 285/*
72675dc6 286 * Commands additional to the ones defined in amcc-common.h
079a136c 287 */
46da1e96 288#define CONFIG_CMD_DTT
46da1e96 289#define CONFIG_CMD_FAT
46da1e96 290#define CONFIG_CMD_NAND
46da1e96 291#define CONFIG_CMD_PCI
46da1e96
JL		 292#define CONFIG_CMD_SDRAM
293
294#ifdef CONFIG_440EPX
295#define CONFIG_CMD_USB
296#endif
297
9de469bd 298#ifndef CONFIG_RAINIER
6d0f6bcf 299#define CONFIG_SYS_POST_FPU_ON CONFIG_SYS_POST_FPU
9de469bd 300#else
6d0f6bcf 301#define CONFIG_SYS_POST_FPU_ON 0
9de469bd 302#endif
887e2ec9 303
a11e0696 304/* POST support */
6d0f6bcf
JCPV		 305#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
306 CONFIG_SYS_POST_CPU | \
307 CONFIG_SYS_POST_ETHER | \
308 CONFIG_SYS_POST_FPU_ON | \
309 CONFIG_SYS_POST_I2C | \
310 CONFIG_SYS_POST_MEMORY | \
311 CONFIG_SYS_POST_SPR | \
312 CONFIG_SYS_POST_UART)
313
314#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
a11e0696 315#define CONFIG_LOGBUFFER
6d0f6bcf 316#define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
a11e0696 317
6d0f6bcf 318#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
a11e0696 319
887e2ec9
SR		 320#define CONFIG_SUPPORT_VFAT
321
214398d9 322/*
887e2ec9 323 * PCI stuff
214398d9 324 */
887e2ec9 325/* General PCI */
214398d9
LJ		 326#define CONFIG_PCI /* include pci support */
327#define CONFIG_PCI_PNP /* do pci plug-and-play */
6d0f6bcf 328#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
214398d9 329#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
6d0f6bcf
JCPV		 330#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to */
331 /* CONFIG_SYS_PCI_MEMBASE */
887e2ec9 332/* Board-specific PCI */
6d0f6bcf
JCPV		 333#define CONFIG_SYS_PCI_TARGET_INIT
334#define CONFIG_SYS_PCI_MASTER_INIT
887e2ec9 335
6d0f6bcf
JCPV		 336#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
337#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */
887e2ec9 338
214398d9 339/*
887e2ec9 340 * External Bus Controller (EBC) Setup
214398d9 341 */
887e2ec9
SR		 342
343/*
344 * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
345 */
346#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
6d0f6bcf 347#define CONFIG_SYS_NAND_CS 3 /* NAND chip connected to CSx */
214398d9 348/* Memory Bank 0 (NOR-FLASH) initialization */
6d0f6bcf
JCPV		 349#define CONFIG_SYS_EBC_PB0AP 0x03017200
350#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xda000)
887e2ec9 351
214398d9 352/* Memory Bank 3 (NAND-FLASH) initialization */
6d0f6bcf
JCPV		 353#define CONFIG_SYS_EBC_PB3AP 0x018003c0
354#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
887e2ec9 355#else
6d0f6bcf 356#define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */
214398d9 357/* Memory Bank 3 (NOR-FLASH) initialization */
6d0f6bcf
JCPV		 358#define CONFIG_SYS_EBC_PB3AP 0x03017200
359#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_FLASH_BASE | 0xda000)
887e2ec9 360
214398d9 361/* Memory Bank 0 (NAND-FLASH) initialization */
6d0f6bcf
JCPV		 362#define CONFIG_SYS_EBC_PB0AP 0x018003c0
363#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
887e2ec9
SR		 364#endif
365
214398d9 366/* Memory Bank 2 (CPLD) initialization */
6d0f6bcf
JCPV		 367#define CONFIG_SYS_EBC_PB2AP 0x24814580
368#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_BCSR_BASE | 0x38000)
887e2ec9 369
6d0f6bcf 370#define CONFIG_SYS_BCSR5_PCI66EN 0x80
5a5958b7 371
214398d9 372/*
43a2b0e7 373 * NAND FLASH
214398d9 374 */
6d0f6bcf 375#define CONFIG_SYS_MAX_NAND_DEVICE 1
43a2b0e7 376#define NAND_MAX_CHIPS 1
6d0f6bcf
JCPV		 377#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
378#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
43a2b0e7 379
214398d9 380/*
b05e8bf5
LJ		 381 * PPC440 GPIO Configuration
382 */
383/* test-only: take GPIO init from pcs440ep ???? in config file */
6d0f6bcf 384#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
b05e8bf5
LJ		 385{ \
386/* GPIO Core 0 */ \
387{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
388{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
389{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
390{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
391{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
392{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
393{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \
394{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \
395{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \
396{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \
397{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \
398{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \
399{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
400{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \
401{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO14 */ \
402{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \
403{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO16 GMCTxD(4) */ \
404{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO17 GMCTxD(5) */ \
405{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO18 GMCTxD(6) */ \
406{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO19 GMCTxD(7) */ \
407{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \
408{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \
409{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \
410{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO23 SCPD0 */ \
411{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO24 GMCTxD(2) */ \
412{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO25 GMCTxD(3) */ \
413{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \
414{GPIO0_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
415{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO28 USB2D_TXVALID */ \
416{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
417{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
418{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
419}, \
420{ \
421/* GPIO Core 1 */ \
422{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \
423{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \
eab10073
SF		 424{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO34 UART0_8PIN_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
425{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
426{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO36 UART0_CTS_N EBC_DATA(0) UART3_SIN*/ \
427{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \
428{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_8PIN_DTR_N UART1_SOUT */ \
429{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_8PIN_RI_N UART1_SIN */ \
b05e8bf5
LJ		 430{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \
431{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \
432{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \
433{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \
434{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
435{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
436{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
437{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
438{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
439{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
440{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
441{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
442{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
443{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
444{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
445{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \
446{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
447{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
448{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
449{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
450{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
451{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
452{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
453{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
454} \
455}
456
bc778812
AG		 457#ifdef CONFIG_VIDEO
458#define CONFIG_BIOSEMU /* x86 bios emulator for vga bios */
459#define CONFIG_ATI_RADEON_FB /* use radeon framebuffer driver */
460#define VIDEO_IO_OFFSET 0xe8000000
6d0f6bcf 461#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
bc778812
AG		 462#define CONFIG_VIDEO_SW_CURSOR
463#define CONFIG_VIDEO_LOGO
464#define CONFIG_CFB_CONSOLE
465#define CONFIG_SPLASH_SCREEN
466#define CONFIG_VGA_AS_SINGLE_DEVICE
467#define CONFIG_CMD_BMP
468#endif
469
214398d9 470#endif /* __CONFIG_H */
"Das U-Boot" Source Tree