[people/ms/u-boot.git] / include / configs / sequoia.h

/*
 * (C) Copyright 2006-2008
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * (C) Copyright 2006
 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
 * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * sequoia.h - configuration for Sequoia & Rainier boards
 */
#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
/* This config file is used for Sequoia (440EPx) and Rainier (440GRx)	*/
#ifndef CONFIG_RAINIER
#define CONFIG_440EPX		1	/* Specific PPC440EPx		*/
#define CONFIG_HOSTNAME		sequoia
#else
#define CONFIG_440GRX		1	/* Specific PPC440GRx		*/
#define CONFIG_HOSTNAME		rainier
#endif
#define CONFIG_440		1	/* ... PPC440 family		*/

#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE	0xFFF80000
#endif

/*
 * Include common defines/options for all AMCC eval boards
 */
#include "amcc-common.h"

/* Detect Sequoia PLL input clock automatically via CPLD bit		*/
#define CONFIG_SYS_CLK_FREQ    ((in8(CONFIG_SYS_BCSR_BASE + 3) & 0x80) ? \
				33333333 : 33000000)

/*
 * Define this if you want support for video console with radeon 9200 pci card
 * Also set CONFIG_SYS_TEXT_BASE to 0xFFF80000 in board/amcc/sequoia/config.mk in this case
 */
#undef CONFIG_VIDEO

#ifdef CONFIG_VIDEO
/*
 * 44x dcache supported is working now on sequoia, but we don't enable
 * it yet since it needs further testing
 */
#define CONFIG_4xx_DCACHE		/* enable dcache		*/
#endif

#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
#define CONFIG_MISC_INIT_R	1	/* Call misc_init_r		*/

/*
 * Base addresses -- Note these are effective addresses where the actual
 * resources get mapped (not physical addresses).
 */
#define CONFIG_SYS_TLB_FOR_BOOT_FLASH	0x0003
#define CONFIG_SYS_BOOT_BASE_ADDR	0xf0000000
#define CONFIG_SYS_FLASH_BASE		0xfc000000	/* start of FLASH	*/
#define CONFIG_SYS_NAND_ADDR		0xd0000000	/* NAND Flash		*/
#define CONFIG_SYS_OCM_BASE		0xe0010000	/* ocm			*/
#define CONFIG_SYS_OCM_DATA_ADDR	CONFIG_SYS_OCM_BASE
#define CONFIG_SYS_PCI_BASE		0xe0000000	/* Internal PCI regs	*/
#define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped pci memory	*/
#define CONFIG_SYS_PCI_MEMBASE1	CONFIG_SYS_PCI_MEMBASE  + 0x10000000
#define CONFIG_SYS_PCI_MEMBASE2	CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
#define CONFIG_SYS_PCI_MEMBASE3	CONFIG_SYS_PCI_MEMBASE2 + 0x10000000

#define CONFIG_SYS_USB2D0_BASE		0xe0000100
#define CONFIG_SYS_USB_DEVICE		0xe0000000
#define CONFIG_SYS_USB_HOST		0xe0000400
#define CONFIG_SYS_BCSR_BASE		0xc0000000

/*
 * Initial RAM & stack pointer
 */
/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache	*/
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_BASE	/* OCM			*/
#define CONFIG_SYS_INIT_RAM_SIZE	(4 << 10)
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)

/*
 * Serial Port
 */
#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
#define CONFIG_SYS_EXT_SERIAL_CLOCK	11059200	/* ext. 11.059MHz clk	*/

/*
 * Environment
 */
#if defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_ENV_IS_NOWHERE		/* Store env in memory only	*/
#define CONFIG_ENV_SIZE		(8 << 10)
#else
#define CONFIG_ENV_IS_IN_FLASH		/* use FLASH for environ vars	*/
#endif

#if defined(CONFIG_CMD_FLASH)
/*
 * FLASH related
 */
#define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible	*/
#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/

#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks	      */
#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip  */

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)    */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)    */

#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)   */
#define CONFIG_SYS_FLASH_PROTECTION	1	/* use hardware flash protection      */

#define CONFIG_SYS_FLASH_EMPTY_INFO	      /* print 'E' for empty sector on flinfo */
#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash      */
#endif /* CONFIG_CMD_FLASH */

#ifdef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector	      */
#define CONFIG_ENV_ADDR		((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector   */

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
#endif

/*
 * DDR SDRAM
 */
#define CONFIG_SYS_MBYTES_SDRAM        (256)	/* 256MB			*/
#if !defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_DDR_DATA_EYE		/* use DDR2 optimization	*/
#endif
#define CONFIG_SYS_MEM_TOP_HIDE	(4 << 10) /* don't use last 4kbytes	*/
					/* 440EPx errata CHIP 11	*/

/*
 * I2C
 */
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000

#define CONFIG_SYS_I2C_EEPROM_ADDR	(0xa8>>1)
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10

/* I2C bootstrap EEPROM */
#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR	0x52
#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET	0
#define CONFIG_4xx_CONFIG_BLOCKSIZE		16

/* I2C SYSMON (LM75, AD7414 is almost compatible)			*/
#define CONFIG_DTT_LM75		1	/* ON Semi's LM75		*/
#define CONFIG_DTT_AD7414	1	/* use AD7414			*/
#define CONFIG_DTT_SENSORS	{0}	/* Sensor addresses		*/
#define CONFIG_SYS_DTT_MAX_TEMP	70
#define CONFIG_SYS_DTT_LOW_TEMP	-30
#define CONFIG_SYS_DTT_HYSTERESIS	3

/*
 * Default environment variables
 */
#define	CONFIG_EXTRA_ENV_SETTINGS					\
	CONFIG_AMCC_DEF_ENV						\
	CONFIG_AMCC_DEF_ENV_POWERPC					\
	CONFIG_AMCC_DEF_ENV_PPC_OLD					\
	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
	"kernel_addr=FC000000\0"					\
	"ramdisk_addr=FC180000\0"					\
	""

#define CONFIG_M88E1111_PHY	1
#define	CONFIG_IBM_EMAC4_V4	1
#define CONFIG_PHY_ADDR		0	/* PHY address, See schematics	*/

#define CONFIG_PHY_RESET        1	/* reset phy upon startup	*/
#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */

#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
#define CONFIG_PHY1_ADDR	1

/* USB */
#ifdef CONFIG_440EPX

#undef CONFIG_USB_EHCI	/* OHCI by default */

#ifdef CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_PPC4XX
#define CONFIG_SYS_PPC4XX_USB_ADDR	0xe0000300
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_EHCI_MMIO_BIG_ENDIAN
#define CONFIG_EHCI_DESC_BIG_ENDIAN
#else /* CONFIG_USB_EHCI */
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_OHCI_BE_CONTROLLER

#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
#define CONFIG_SYS_USB_OHCI_CPU_INIT	1
#define CONFIG_SYS_USB_OHCI_REGS_BASE	CONFIG_SYS_USB_HOST
#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"ppc440"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
#endif

#define CONFIG_USB_STORAGE
/* Comment this out to enable USB 1.1 device */
#define USB_2_0_DEVICE

#endif /* CONFIG_440EPX */

/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION

/*
 * Commands additional to the ones defined in amcc-common.h
 */
#define CONFIG_CMD_CHIP_CONFIG
#define CONFIG_CMD_DTT
#define CONFIG_CMD_FAT
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PCI
#define CONFIG_CMD_SDRAM

#ifdef CONFIG_440EPX
#endif

#ifndef CONFIG_RAINIER
#define CONFIG_SYS_POST_FPU_ON		CONFIG_SYS_POST_FPU
#else
#define CONFIG_SYS_POST_FPU_ON		0
#endif

/*
 * Don't run the memory POST on the NAND-booting version. It will
 * overwrite part of the U-Boot image which is already loaded from NAND
 * to SDRAM.
 */
#if defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_SYS_POST_MEMORY_ON	0
#else
#define CONFIG_SYS_POST_MEMORY_ON	CONFIG_SYS_POST_MEMORY
#endif

/* POST support */
#define CONFIG_POST		(CONFIG_SYS_POST_CACHE	   | \
				 CONFIG_SYS_POST_CPU	   | \
				 CONFIG_SYS_POST_ETHER	   | \
				 CONFIG_SYS_POST_FPU_ON    | \
				 CONFIG_SYS_POST_I2C	   | \
				 CONFIG_SYS_POST_MEMORY_ON | \
				 CONFIG_SYS_POST_SPR	   | \
				 CONFIG_SYS_POST_UART)

#define CONFIG_LOGBUFFER
#define CONFIG_SYS_POST_CACHE_ADDR	0x7fff0000	/* free virtual address     */

#define CONFIG_SYS_CONSOLE_IS_IN_ENV	/* Otherwise it catches logbuffer as output */

#define CONFIG_SUPPORT_VFAT

/*
 * PCI stuff
 */
/* General PCI */
#define CONFIG_PCI			/* include pci support		*/
#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
#define CONFIG_SYS_PCI_CACHE_LINE_SIZE	0	/* to avoid problems with PNP	*/
#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
#define CONFIG_SYS_PCI_TARGBASE	0x80000000	/* PCIaddr mapped to	*/
						/*   CONFIG_SYS_PCI_MEMBASE	*/
/* Board-specific PCI */
#define CONFIG_SYS_PCI_TARGET_INIT
#define CONFIG_SYS_PCI_MASTER_INIT
#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ

#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC				*/
#define CONFIG_SYS_PCI_SUBSYS_ID       0xcafe	/* Whatever			*/

/*
 * External Bus Controller (EBC) Setup
 */

/*
 * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
 */
#if !defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_SYS_NAND_CS		3	/* NAND chip connected to CSx	*/
/* Memory Bank 0 (NOR-FLASH) initialization				*/
#define CONFIG_SYS_EBC_PB0AP		0x03017200
#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_FLASH_BASE | 0xda000)

/* Memory Bank 3 (NAND-FLASH) initialization				*/
#define CONFIG_SYS_EBC_PB3AP		0x018003c0
#define CONFIG_SYS_EBC_PB3CR		(CONFIG_SYS_NAND_ADDR | 0x1c000)
#else
#define CONFIG_SYS_NAND_CS		0	/* NAND chip connected to CSx	*/
/* Memory Bank 3 (NOR-FLASH) initialization				*/
#define CONFIG_SYS_EBC_PB3AP		0x03017200
#define CONFIG_SYS_EBC_PB3CR		(CONFIG_SYS_FLASH_BASE | 0xda000)

/* Memory Bank 0 (NAND-FLASH) initialization				*/
#define CONFIG_SYS_EBC_PB0AP		0x018003c0
#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_NAND_ADDR | 0x1c000)
#endif

/* Memory Bank 2 (CPLD) initialization					*/
#define CONFIG_SYS_EBC_PB2AP		0x24814580
#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_BCSR_BASE | 0x38000)

#define CONFIG_SYS_BCSR5_PCI66EN	0x80

/*
 * NAND FLASH
 */
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_BASE		(CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
#define CONFIG_SYS_NAND_SELECT_DEVICE  1	/* nand driver supports mutipl. chips */

/*
 * PPC440 GPIO Configuration
 */
/* test-only: take GPIO init from pcs440ep ???? in config file */
#define CONFIG_SYS_4xx_GPIO_TABLE { /*	  Out		  GPIO	Alternate1	Alternate2	Alternate3 */ \
{											\
/* GPIO Core 0 */									\
{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0	EBC_ADDR(7)	DMA_REQ(2)	*/	\
{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1	EBC_ADDR(6)	DMA_ACK(2)	*/	\
{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO2	EBC_ADDR(5)	DMA_EOT/TC(2)	*/	\
{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO3	EBC_ADDR(4)	DMA_REQ(3)	*/	\
{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO4	EBC_ADDR(3)	DMA_ACK(3)	*/	\
{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO5	EBC_ADDR(2)	DMA_EOT/TC(3)	*/	\
{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO6	EBC_CS_N(1)			*/	\
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7	EBC_CS_N(2)			*/	\
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8	EBC_CS_N(3)			*/	\
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9	EBC_CS_N(4)			*/	\
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5)			*/	\
{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR			*/	\
{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO12				*/	\
{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO13				*/	\
{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO14				*/	\
{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO15				*/	\
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO16 GMCTxD(4)			*/	\
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO17 GMCTxD(5)			*/	\
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO18 GMCTxD(6)			*/	\
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO19 GMCTxD(7)			*/	\
{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO20 RejectPkt0			*/	\
{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO21 RejectPkt1			*/	\
{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO22				*/	\
{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO23 SCPD0				*/	\
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO24 GMCTxD(2)			*/	\
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO25 GMCTxD(3)			*/	\
{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26				*/	\
{GPIO0_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ	USB2D_RXERROR	*/	\
{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO28		USB2D_TXVALID	*/	\
{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO29 EBC_EXT_HDLA	USB2D_PAD_SUSPNDM */	\
{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO30 EBC_EXT_ACK	USB2D_XCVRSELECT*/	\
{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO31 EBC_EXR_BUSREQ	USB2D_TERMSELECT*/	\
},											\
{											\
/* GPIO Core 1 */									\
{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO32 USB2D_OPMODE0	EBC_DATA(2)	*/	\
{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO33 USB2D_OPMODE1	EBC_DATA(3)	*/	\
{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO34 UART0_8PIN_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO36 UART0_CTS_N	EBC_DATA(0)	UART3_SIN*/ \
{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO37 UART0_RTS_N	EBC_DATA(1)	UART3_SOUT*/ \
{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_8PIN_DTR_N UART1_SOUT	*/	\
{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_8PIN_RI_N UART1_SIN	*/	\
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0)			*/	\
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1)			*/	\
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2)			*/	\
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3)			*/	\
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4)	DMA_ACK(1)	*/	\
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6)	DMA_EOT/TC(1)	*/	\
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7)	DMA_REQ(0)	*/	\
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8)	DMA_ACK(0)	*/	\
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9)	DMA_EOT/TC(0)	*/	\
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49  Unselect via TraceSelect Bit	*/	\
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit	*/	\
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit	*/	\
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit	*/	\
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit	*/	\
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit	*/	\
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55  Unselect via TraceSelect Bit	*/	\
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit	*/	\
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57  Unselect via TraceSelect Bit	*/	\
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit	*/	\
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit	*/	\
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit	*/	\
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit	*/	\
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit	*/	\
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit	*/	\
}											\
}

#ifdef CONFIG_VIDEO
#define CONFIG_BIOSEMU			/* x86 bios emulator for vga bios */
#define CONFIG_ATI_RADEON_FB		/* use radeon framebuffer driver */
#define VIDEO_IO_OFFSET			0xe8000000
#define CONFIG_SYS_ISA_IO_BASE_ADDRESS		VIDEO_IO_OFFSET
#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_VIDEO_LOGO
#define CONFIG_CFB_CONSOLE
#define CONFIG_SPLASH_SCREEN
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_CMD_BMP
#endif

#endif /* __CONFIG_H */
Commit	Line	Data
887e2ec9	1	/*
fc84a849	2	* (C) Copyright 2006-2008
887e2ec9 SR	3	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	4	*
	5	* (C) Copyright 2006
	6	* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
	7	* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
	8	*
1a459660	9	* SPDX-License-Identifier: GPL-2.0+
887e2ec9 SR	10	*/
887e2ec9 SR	11
214398d9	12	/*
e802594b	13	* sequoia.h - configuration for Sequoia & Rainier boards
214398d9	14	*/
887e2ec9 SR	15	#ifndef __CONFIG_H
	16	#define __CONFIG_H
	17
214398d9	18	/*
887e2ec9	19	* High Level Configuration Options
214398d9	20	*/
e802594b	21	/* This config file is used for Sequoia (440EPx) and Rainier (440GRx) */
854bc8da	22	#ifndef CONFIG_RAINIER
214398d9	23	#define CONFIG_440EPX 1 /* Specific PPC440EPx */
72675dc6	24	#define CONFIG_HOSTNAME sequoia
854bc8da	25	#else
214398d9	26	#define CONFIG_440GRX 1 /* Specific PPC440GRx */
72675dc6	27	#define CONFIG_HOSTNAME rainier
854bc8da	28	#endif
214398d9	29	#define CONFIG_440 1 /* ... PPC440 family */
72675dc6	30
2ae18241 WD	31	#ifndef CONFIG_SYS_TEXT_BASE
	32	#define CONFIG_SYS_TEXT_BASE 0xFFF80000
	33	#endif
	34
72675dc6 SR	35	/*
	36	* Include common defines/options for all AMCC eval boards
	37	*/
	38	#include "amcc-common.h"
	39
e3b8c78b	40	/* Detect Sequoia PLL input clock automatically via CPLD bit */
6d0f6bcf	41	#define CONFIG_SYS_CLK_FREQ ((in8(CONFIG_SYS_BCSR_BASE + 3) & 0x80) ? \
193b4a3b	42	33333333 : 33000000)
887e2ec9	43
bc778812 AG	44	/*
bc778812 AG	45	* Define this if you want support for video console with radeon 9200 pci card
14d0a02a	46	* Also set CONFIG_SYS_TEXT_BASE to 0xFFF80000 in board/amcc/sequoia/config.mk in this case
bc778812 AG	47	*/
	48	#undef CONFIG_VIDEO
	49
	50	#ifdef CONFIG_VIDEO
d25dfe08 SR	51	/*
	52	* 44x dcache supported is working now on sequoia, but we don't enable
	53	* it yet since it needs further testing
	54	*/
214398d9	55	#define CONFIG_4xx_DCACHE /* enable dcache */
d25dfe08 SR	56	#endif
d25dfe08 SR	57
214398d9 LJ	58	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
214398d9 LJ	59	#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
887e2ec9	60
214398d9 LJ	61	/*
	62	* Base addresses -- Note these are effective addresses where the actual
	63	* resources get mapped (not physical addresses).
	64	*/
6d0f6bcf JCPV	65	#define CONFIG_SYS_TLB_FOR_BOOT_FLASH 0x0003
	66	#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
	67	#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */
	68	#define CONFIG_SYS_NAND_ADDR 0xd0000000 /* NAND Flash */
	69	#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
	70	#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_OCM_BASE
	71	#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
	72	#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
	73	#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
	74	#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
	75	#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
887e2ec9	76
6d0f6bcf JCPV	77	#define CONFIG_SYS_USB2D0_BASE 0xe0000100
	78	#define CONFIG_SYS_USB_DEVICE 0xe0000000
	79	#define CONFIG_SYS_USB_HOST 0xe0000400
	80	#define CONFIG_SYS_BCSR_BASE 0xc0000000
887e2ec9	81
214398d9	82	/*
887e2ec9	83	* Initial RAM & stack pointer
214398d9	84	*/
887e2ec9	85	/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
6d0f6bcf	86	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
553f0982	87	#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
25ddd1fb	88	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
800eb096	89	#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
887e2ec9	90
214398d9	91	/*
887e2ec9	92	* Serial Port
214398d9	93	*/
550650dd	94	#define CONFIG_CONS_INDEX 1 /* Use UART0 */
6d0f6bcf	95	#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
887e2ec9	96
214398d9	97	/*
887e2ec9	98	* Environment
214398d9	99	*/
345b77ba	100	#if defined(CONFIG_SYS_RAMBOOT)
d873133f SR	101	#define CONFIG_ENV_IS_NOWHERE /* Store env in memory only */
d873133f SR	102	#define CONFIG_ENV_SIZE (8 << 10)
887e2ec9	103	#else
d873133f	104	#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environ vars */
887e2ec9	105	#endif
887e2ec9	106
d873133f	107	#if defined(CONFIG_CMD_FLASH)
214398d9	108	/*
887e2ec9	109	* FLASH related
214398d9	110	*/
6d0f6bcf	111	#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
00b1883a	112	#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
887e2ec9	113
6d0f6bcf	114	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
887e2ec9	115
6d0f6bcf JCPV	116	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
6d0f6bcf JCPV	117	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
887e2ec9	118
6d0f6bcf JCPV	119	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	120	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
887e2ec9	121
6d0f6bcf JCPV	122	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
6d0f6bcf JCPV	123	#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
887e2ec9	124
6d0f6bcf JCPV	125	#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
6d0f6bcf JCPV	126	#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
ef0f2f57	127	#endif /* CONFIG_CMD_FLASH */
887e2ec9	128
5a1aceb0	129	#ifdef CONFIG_ENV_IS_IN_FLASH
0e8d1586	130	#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
6d0f6bcf	131	#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
0e8d1586	132	#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
887e2ec9 SR	133
887e2ec9 SR	134	/* Address and size of Redundant Environment Sector */
0e8d1586 JCPV	135	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
0e8d1586 JCPV	136	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
887e2ec9 SR	137	#endif
887e2ec9 SR	138
214398d9	139	/*
887e2ec9	140	* DDR SDRAM
214398d9	141	*/
6d0f6bcf	142	#define CONFIG_SYS_MBYTES_SDRAM (256) /* 256MB */
345b77ba	143	#if !defined(CONFIG_SYS_RAMBOOT)
214398d9	144	#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
02388983	145	#endif
6d0f6bcf	146	#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
14f73ca6	147	/* 440EPx errata CHIP 11 */
887e2ec9	148
214398d9	149	/*
887e2ec9	150	* I2C
214398d9	151	*/
880540de	152	#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
887e2ec9	153
6d0f6bcf JCPV	154	#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
	155	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	156	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	157	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
887e2ec9	158
cfc25874 SR	159	/* I2C bootstrap EEPROM */
	160	#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52
	161	#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
	162	#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
	163
887e2ec9	164	/* I2C SYSMON (LM75, AD7414 is almost compatible) */
214398d9 LJ	165	#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
	166	#define CONFIG_DTT_AD7414 1 /* use AD7414 */
	167	#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
6d0f6bcf JCPV	168	#define CONFIG_SYS_DTT_MAX_TEMP 70
	169	#define CONFIG_SYS_DTT_LOW_TEMP -30
	170	#define CONFIG_SYS_DTT_HYSTERESIS 3
887e2ec9	171
72675dc6 SR	172	/*
	173	* Default environment variables
	174	*/
887e2ec9	175	#define CONFIG_EXTRA_ENV_SETTINGS \
72675dc6 SR	176	CONFIG_AMCC_DEF_ENV \
	177	CONFIG_AMCC_DEF_ENV_POWERPC \
	178	CONFIG_AMCC_DEF_ENV_PPC_OLD \
	179	CONFIG_AMCC_DEF_ENV_NOR_UPD \
4ef62514 SR	180	"kernel_addr=FC000000\0" \
4ef62514 SR	181	"ramdisk_addr=FC180000\0" \
887e2ec9	182	""
887e2ec9 SR	183
	184	#define CONFIG_M88E1111_PHY 1
	185	#define CONFIG_IBM_EMAC4_V4 1
887e2ec9 SR	186	#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
887e2ec9 SR	187
214398d9	188	#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
887e2ec9 SR	189	#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
	190
	191	#define CONFIG_HAS_ETH0
887e2ec9 SR	192	#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
	193	#define CONFIG_PHY1_ADDR 1
	194
	195	/* USB */
854bc8da	196	#ifdef CONFIG_440EPX
559e2c87 CZ	197
	198	#undef CONFIG_USB_EHCI /* OHCI by default */
	199
	200	#ifdef CONFIG_USB_EHCI
	201	#define CONFIG_USB_EHCI_PPC4XX
	202	#define CONFIG_SYS_PPC4XX_USB_ADDR 0xe0000300
	203	#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
	204	#define CONFIG_EHCI_MMIO_BIG_ENDIAN
	205	#define CONFIG_EHCI_DESC_BIG_ENDIAN
559e2c87	206	#else /* CONFIG_USB_EHCI */
2d146843	207	#define CONFIG_USB_OHCI_NEW
6d0f6bcf	208	#define CONFIG_SYS_OHCI_BE_CONTROLLER
2d146843	209
6d0f6bcf JCPV	210	#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
	211	#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
	212	#define CONFIG_SYS_USB_OHCI_REGS_BASE CONFIG_SYS_USB_HOST
	213	#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440"
	214	#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
559e2c87	215	#endif
887e2ec9	216
559e2c87	217	#define CONFIG_USB_STORAGE
887e2ec9 SR	218	/* Comment this out to enable USB 1.1 device */
	219	#define USB_2_0_DEVICE
	220
854bc8da SR	221	#endif /* CONFIG_440EPX */
854bc8da SR	222
887e2ec9 SR	223	/* Partitions */
	224	#define CONFIG_MAC_PARTITION
	225	#define CONFIG_DOS_PARTITION
	226	#define CONFIG_ISO_PARTITION
	227
079a136c	228	/*
72675dc6	229	* Commands additional to the ones defined in amcc-common.h
079a136c	230	*/
cfc25874	231	#define CONFIG_CMD_CHIP_CONFIG
46da1e96	232	#define CONFIG_CMD_DTT
46da1e96	233	#define CONFIG_CMD_FAT
46da1e96	234	#define CONFIG_CMD_NAND
46da1e96	235	#define CONFIG_CMD_PCI
46da1e96 JL	236	#define CONFIG_CMD_SDRAM
	237
	238	#ifdef CONFIG_440EPX
46da1e96 JL	239	#endif
46da1e96 JL	240
9de469bd	241	#ifndef CONFIG_RAINIER
6d0f6bcf	242	#define CONFIG_SYS_POST_FPU_ON CONFIG_SYS_POST_FPU
9de469bd	243	#else
6d0f6bcf	244	#define CONFIG_SYS_POST_FPU_ON 0
9de469bd	245	#endif
887e2ec9	246
9a929170 SR	247	/*
	248	* Don't run the memory POST on the NAND-booting version. It will
	249	* overwrite part of the U-Boot image which is already loaded from NAND
	250	* to SDRAM.
	251	*/
345b77ba	252	#if defined(CONFIG_SYS_RAMBOOT)
9a929170 SR	253	#define CONFIG_SYS_POST_MEMORY_ON 0
	254	#else
	255	#define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY
	256	#endif
	257
a11e0696	258	/* POST support */
6d0f6bcf JCPV	259	#define CONFIG_POST (CONFIG_SYS_POST_CACHE \| \
	260	CONFIG_SYS_POST_CPU \| \
	261	CONFIG_SYS_POST_ETHER \| \
9a929170	262	CONFIG_SYS_POST_FPU_ON \| \
6d0f6bcf	263	CONFIG_SYS_POST_I2C \| \
9a929170	264	CONFIG_SYS_POST_MEMORY_ON \| \
6d0f6bcf JCPV	265	CONFIG_SYS_POST_SPR \| \
	266	CONFIG_SYS_POST_UART)
	267
a11e0696	268	#define CONFIG_LOGBUFFER
6d0f6bcf	269	#define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
a11e0696	270
6d0f6bcf	271	#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
a11e0696	272
887e2ec9 SR	273	#define CONFIG_SUPPORT_VFAT
887e2ec9 SR	274
214398d9	275	/*
887e2ec9	276	* PCI stuff
214398d9	277	*/
887e2ec9	278	/* General PCI */
214398d9	279	#define CONFIG_PCI /* include pci support */
842033e6	280	#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
214398d9	281	#define CONFIG_PCI_PNP /* do pci plug-and-play */
6d0f6bcf	282	#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
214398d9	283	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
6d0f6bcf JCPV	284	#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to */
6d0f6bcf JCPV	285	/* CONFIG_SYS_PCI_MEMBASE */
887e2ec9	286	/* Board-specific PCI */
6d0f6bcf JCPV	287	#define CONFIG_SYS_PCI_TARGET_INIT
6d0f6bcf JCPV	288	#define CONFIG_SYS_PCI_MASTER_INIT
a760b020	289	#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
887e2ec9	290
6d0f6bcf JCPV	291	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
6d0f6bcf JCPV	292	#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */
887e2ec9	293
214398d9	294	/*
887e2ec9	295	* External Bus Controller (EBC) Setup
214398d9	296	*/
887e2ec9 SR	297
	298	/*
	299	* On Sequoia CS0 and CS3 are switched when configuring for NAND booting
	300	*/
345b77ba	301	#if !defined(CONFIG_SYS_RAMBOOT)
6d0f6bcf	302	#define CONFIG_SYS_NAND_CS 3 /* NAND chip connected to CSx */
214398d9	303	/* Memory Bank 0 (NOR-FLASH) initialization */
6d0f6bcf JCPV	304	#define CONFIG_SYS_EBC_PB0AP 0x03017200
6d0f6bcf JCPV	305	#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE \| 0xda000)
887e2ec9	306
214398d9	307	/* Memory Bank 3 (NAND-FLASH) initialization */
6d0f6bcf JCPV	308	#define CONFIG_SYS_EBC_PB3AP 0x018003c0
6d0f6bcf JCPV	309	#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_NAND_ADDR \| 0x1c000)
887e2ec9	310	#else
6d0f6bcf	311	#define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */
214398d9	312	/* Memory Bank 3 (NOR-FLASH) initialization */
6d0f6bcf JCPV	313	#define CONFIG_SYS_EBC_PB3AP 0x03017200
6d0f6bcf JCPV	314	#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_FLASH_BASE \| 0xda000)
887e2ec9	315
214398d9	316	/* Memory Bank 0 (NAND-FLASH) initialization */
6d0f6bcf JCPV	317	#define CONFIG_SYS_EBC_PB0AP 0x018003c0
6d0f6bcf JCPV	318	#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR \| 0x1c000)
887e2ec9 SR	319	#endif
887e2ec9 SR	320
214398d9	321	/* Memory Bank 2 (CPLD) initialization */
6d0f6bcf JCPV	322	#define CONFIG_SYS_EBC_PB2AP 0x24814580
6d0f6bcf JCPV	323	#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_BCSR_BASE \| 0x38000)
887e2ec9	324
6d0f6bcf	325	#define CONFIG_SYS_BCSR5_PCI66EN 0x80
5a5958b7	326
214398d9	327	/*
43a2b0e7	328	* NAND FLASH
214398d9	329	*/
6d0f6bcf	330	#define CONFIG_SYS_MAX_NAND_DEVICE 1
6d0f6bcf JCPV	331	#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
6d0f6bcf JCPV	332	#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
43a2b0e7	333
214398d9	334	/*
b05e8bf5 LJ	335	* PPC440 GPIO Configuration
	336	*/
	337	/* test-only: take GPIO init from pcs440ep ???? in config file */
6d0f6bcf	338	#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
b05e8bf5 LJ	339	{ \
	340	/* GPIO Core 0 */ \
	341	{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
	342	{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
	343	{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
	344	{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
	345	{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
	346	{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
	347	{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \
	348	{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \
	349	{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \
	350	{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \
	351	{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \
	352	{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \
	353	{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
	354	{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \
	355	{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO14 */ \
	356	{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \
	357	{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO16 GMCTxD(4) */ \
	358	{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO17 GMCTxD(5) */ \
	359	{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO18 GMCTxD(6) */ \
	360	{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO19 GMCTxD(7) */ \
	361	{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \
	362	{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \
	363	{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \
	364	{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO23 SCPD0 */ \
	365	{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO24 GMCTxD(2) */ \
	366	{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO25 GMCTxD(3) */ \
	367	{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \
	368	{GPIO0_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
	369	{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO28 USB2D_TXVALID */ \
	370	{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
	371	{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
	372	{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
	373	}, \
	374	{ \
	375	/* GPIO Core 1 */ \
	376	{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \
	377	{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \
eab10073 SF	378	{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO34 UART0_8PIN_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
	379	{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
	380	{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO36 UART0_CTS_N EBC_DATA(0) UART3_SIN*/ \
	381	{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \
	382	{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_8PIN_DTR_N UART1_SOUT */ \
	383	{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_8PIN_RI_N UART1_SIN */ \
b05e8bf5 LJ	384	{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \
	385	{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \
	386	{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \
	387	{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \
	388	{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
	389	{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
	390	{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
	391	{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
	392	{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
	393	{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
	394	{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
	395	{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
	396	{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
	397	{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
	398	{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
	399	{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \
	400	{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
	401	{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
	402	{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
	403	{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
	404	{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
	405	{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
	406	{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
	407	{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
	408	} \
	409	}
	410
bc778812 AG	411	#ifdef CONFIG_VIDEO
	412	#define CONFIG_BIOSEMU /* x86 bios emulator for vga bios */
	413	#define CONFIG_ATI_RADEON_FB /* use radeon framebuffer driver */
	414	#define VIDEO_IO_OFFSET 0xe8000000
6d0f6bcf	415	#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
bc778812 AG	416	#define CONFIG_VIDEO_SW_CURSOR
	417	#define CONFIG_VIDEO_LOGO
	418	#define CONFIG_CFB_CONSOLE
	419	#define CONFIG_SPLASH_SCREEN
	420	#define CONFIG_VGA_AS_SINGLE_DEVICE
	421	#define CONFIG_CMD_BMP
	422	#endif
	423
214398d9	424	#endif /* __CONFIG_H */