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Commit | Line | Data |
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7faddaec NI |
1 | /* |
2 | * Configuation settings for the Renesas SH7763RDP board | |
3 | * | |
4 | * Copyright (C) 2008 Renesas Solutions Corp. | |
5 | * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> | |
6 | * | |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
7faddaec NI |
8 | */ |
9 | ||
10 | #ifndef __SH7763RDP_H | |
11 | #define __SH7763RDP_H | |
12 | ||
13 | #define CONFIG_SH 1 | |
14 | #define CONFIG_SH4 1 | |
15 | #define CONFIG_CPU_SH7763 1 | |
16 | #define CONFIG_SH7763RDP 1 | |
17 | #define __LITTLE_ENDIAN 1 | |
18 | ||
19 | /* | |
20 | * Command line configuration. | |
21 | */ | |
22 | #define CONFIG_CMD_SDRAM | |
23 | #define CONFIG_CMD_FLASH | |
24 | #define CONFIG_CMD_MEMORY | |
ba932445 | 25 | #define CONFIG_CMD_NET |
c8ceca95 | 26 | #define CONFIG_CMD_MII |
ba932445 | 27 | #define CONFIG_CMD_PING |
bdab39d3 | 28 | #define CONFIG_CMD_SAVEENV |
ba932445 NI |
29 | #define CONFIG_CMD_NFS |
30 | #define CONFIG_CMD_JFFS2 | |
7faddaec NI |
31 | |
32 | #define CONFIG_BOOTDELAY -1 | |
33 | #define CONFIG_BOOTARGS "console=ttySC2,115200 root=1f01" | |
34 | #define CONFIG_ENV_OVERWRITE 1 | |
35 | ||
36 | #define CONFIG_VERSION_VARIABLE | |
37 | #undef CONFIG_SHOW_BOOT_PROGRESS | |
38 | ||
39 | /* SCIF */ | |
6c58a030 | 40 | #define CONFIG_SCIF_CONSOLE 1 |
7faddaec NI |
41 | #define CONFIG_BAUDRATE 115200 |
42 | #define CONFIG_CONS_SCIF2 1 | |
43 | ||
00cb2e32 | 44 | #define CONFIG_SYS_TEXT_BASE 0x8FFC0000 |
6d0f6bcf | 45 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
6d0f6bcf JCPV |
46 | #define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */ |
47 | #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ | |
48 | #define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */ | |
49 | #define CONFIG_SYS_BARGSIZE 512 /* Buffer size for Boot Arguments | |
7faddaec | 50 | passed to kernel */ |
6d0f6bcf | 51 | #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate |
7faddaec NI |
52 | settings for this board */ |
53 | ||
7faddaec | 54 | /* SDRAM */ |
6d0f6bcf JCPV |
55 | #define CONFIG_SYS_SDRAM_BASE (0x8C000000) |
56 | #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) | |
57 | #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) | |
58 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) | |
7faddaec NI |
59 | |
60 | /* Flash(NOR) */ | |
6d0f6bcf JCPV |
61 | #define CONFIG_SYS_FLASH_BASE (0xA0000000) |
62 | #define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT) | |
63 | #define CONFIG_SYS_MAX_FLASH_BANKS (1) | |
64 | #define CONFIG_SYS_MAX_FLASH_SECT (520) | |
7faddaec NI |
65 | |
66 | /* U-boot setting */ | |
6d0f6bcf JCPV |
67 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024) |
68 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) | |
69 | #define CONFIG_SYS_MONITOR_LEN (128 * 1024) | |
7faddaec | 70 | /* Size of DRAM reserved for malloc() use */ |
6d0f6bcf | 71 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) |
6d0f6bcf | 72 | #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) |
7faddaec | 73 | |
6d0f6bcf | 74 | #define CONFIG_SYS_FLASH_CFI |
00b1883a | 75 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
76 | #undef CONFIG_SYS_FLASH_QUIET_TEST |
77 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ | |
7faddaec | 78 | /* Timeout for Flash erase operations (in ms) */ |
6d0f6bcf | 79 | #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) |
7faddaec | 80 | /* Timeout for Flash write operations (in ms) */ |
6d0f6bcf | 81 | #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) |
7faddaec | 82 | /* Timeout for Flash set sector lock bit operations (in ms) */ |
6d0f6bcf | 83 | #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) |
7faddaec | 84 | /* Timeout for Flash clear lock bit operations (in ms) */ |
6d0f6bcf | 85 | #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) |
7faddaec | 86 | /* Use hardware flash sectors protection instead of U-Boot software protection */ |
6d0f6bcf JCPV |
87 | #undef CONFIG_SYS_FLASH_PROTECTION |
88 | #undef CONFIG_SYS_DIRECT_FLASH_TFTP | |
5a1aceb0 | 89 | #define CONFIG_ENV_IS_IN_FLASH |
0e8d1586 JCPV |
90 | #define CONFIG_ENV_SECT_SIZE (128 * 1024) |
91 | #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) | |
6d0f6bcf JCPV |
92 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE)) |
93 | /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ | |
94 | #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) | |
0e8d1586 | 95 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) |
6d0f6bcf | 96 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE)) |
7faddaec NI |
97 | |
98 | /* Clock */ | |
99 | #define CONFIG_SYS_CLK_FREQ 66666666 | |
684a501e NI |
100 | #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ |
101 | #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ | |
be45c632 | 102 | #define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */ |
7faddaec | 103 | |
ba932445 NI |
104 | /* Ether */ |
105 | #define CONFIG_SH_ETHER 1 | |
106 | #define CONFIG_SH_ETHER_USE_PORT (1) | |
107 | #define CONFIG_SH_ETHER_PHY_ADDR (0x01) | |
c8ceca95 YS |
108 | #define CONFIG_PHYLIB |
109 | #define CONFIG_BITBANGMII | |
110 | #define CONFIG_BITBANGMII_MULTI | |
a80a6619 | 111 | #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII |
ba932445 | 112 | |
7faddaec | 113 | #endif /* __SH7763RDP_H */ |