[people/ms/u-boot.git] / include / configs / socrates.h

/*
 * (C) Copyright 2008
 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
 *
 * Wolfgang Denk <wd@denx.de>
 * Copyright 2004 Freescale Semiconductor.
 * (C) Copyright 2002,2003 Motorola,Inc.
 * Xianghua Xiao <X.Xiao@motorola.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * Socrates
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* High Level Configuration Options */
#define CONFIG_SOCRATES		1

#define	CONFIG_SYS_TEXT_BASE	0xfff80000

#define CONFIG_PCI_INDIRECT_BRIDGE

#define CONFIG_TSEC_ENET		/* tsec ethernet support	*/

#define CONFIG_MISC_INIT_R	1	/* Call misc_init_r		*/
#define CONFIG_BOARD_EARLY_INIT_R 1	/* Call board_early_init_r	*/

/*
 * Only possible on E500 Version 2 or newer cores.
 */
#define CONFIG_ENABLE_36BIT_PHYS	1

/*
 * sysclk for MPC85xx
 *
 * Two valid values are:
 *    33000000
 *    66000000
 *
 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
 * is likely the desired value here, so that is now the default.
 * The board, however, can run at 66MHz.  In any event, this value
 * must match the settings of some switches.  Details can be found
 * in the README.mpc85xxads.
 */

#ifndef CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_CLK_FREQ	66666666
#endif

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE			/* toggle L2 cache		*/
#define CONFIG_BTB			/* toggle branch predition	*/

#define CONFIG_SYS_INIT_DBCR DBCR_IDM		/* Enable Debug Exceptions	*/

#undef	CONFIG_SYS_DRAM_TEST			/* memory test, takes time	*/
#define CONFIG_SYS_MEMTEST_START	0x00400000
#define CONFIG_SYS_MEMTEST_END		0x00C00000

#define CONFIG_SYS_CCSRBAR		0xE0000000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR

/* DDR Setup */
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD

#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE	0xDeadBeef

#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_VERY_BIG_RAM

#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL	2

/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS	0x50	/* CTLR 0 DIMM 0 */

#define CONFIG_DDR_DEFAULT_CL	30		/* CAS latency 3	*/

/* Hardcoded values, to use instead of SPD */
#define CONFIG_SYS_DDR_CS0_BNDS		0x0000000f
#define CONFIG_SYS_DDR_CS0_CONFIG		0x80010102
#define CONFIG_SYS_DDR_TIMING_0		0x00260802
#define CONFIG_SYS_DDR_TIMING_1		0x3935D322
#define CONFIG_SYS_DDR_TIMING_2		0x14904CC8
#define CONFIG_SYS_DDR_MODE			0x00480432
#define CONFIG_SYS_DDR_INTERVAL		0x030C0100
#define CONFIG_SYS_DDR_CONFIG_2		0x04400000
#define CONFIG_SYS_DDR_CONFIG			0xC3008000
#define CONFIG_SYS_DDR_CLK_CONTROL		0x03800000
#define CONFIG_SYS_SDRAM_SIZE			256 /* in Megs */

/*
 * Flash on the LocalBus
 */
#define CONFIG_SYS_LBC_CACHE_BASE	0xf0000000	/* Localbus cacheable	 */

#define CONFIG_SYS_FLASH0		0xFE000000
#define CONFIG_SYS_FLASH1		0xFC000000
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }

#define CONFIG_SYS_LBC_FLASH_BASE	CONFIG_SYS_FLASH1	/* Localbus flash start	*/
#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH	*/

#define CONFIG_SYS_BR0_PRELIM		0xfe001001	/* port size 16bit	*/
#define CONFIG_SYS_OR0_PRELIM		0xfe000030	/* 32MB Flash		*/
#define CONFIG_SYS_BR1_PRELIM		0xfc001001	/* port size 16bit	*/
#define CONFIG_SYS_OR1_PRELIM		0xfe000030	/* 32MB Flash		*/

#define CONFIG_SYS_FLASH_CFI				/* flash is CFI compat.	*/
#define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver*/

#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks	*/
#define CONFIG_SYS_MAX_FLASH_SECT	256		/* sectors per device	*/
#undef	CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms)	*/

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor	*/

#define CONFIG_SYS_LBC_LCRR		0x00030004    /* LB clock ratio reg	*/
#define CONFIG_SYS_LBC_LBCR		0x00000000    /* LB config reg		*/
#define CONFIG_SYS_LBC_LSRT		0x20000000    /* LB sdram refresh timer	*/
#define CONFIG_SYS_LBC_MRTPR		0x20000000    /* LB refresh timer presc.*/

#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address	*/
#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size used area in RAM*/

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN		(384 * 1024)	/* Reserve 384KiB for Mon */
#define CONFIG_SYS_MALLOC_LEN		(4 << 20)	/* Reserve 4 MB for malloc */

/* FPGA and NAND */
#define CONFIG_SYS_FPGA_BASE		0xc0000000
#define CONFIG_SYS_FPGA_SIZE		0x00100000	/* 1 MB		*/
#define CONFIG_SYS_HMI_BASE		0xc0010000
#define CONFIG_SYS_BR3_PRELIM		0xc0001881	/* UPMA, 32-bit */
#define CONFIG_SYS_OR3_PRELIM		0xfff00000	/* 1 MB 	*/

#define CONFIG_SYS_NAND_BASE		(CONFIG_SYS_FPGA_BASE + 0x70)
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_CMD_NAND

/* LIME GDC */
#define CONFIG_SYS_LIME_BASE		0xc8000000
#define CONFIG_SYS_LIME_SIZE		0x04000000	/* 64 MB	*/
#define CONFIG_SYS_BR2_PRELIM		0xc80018a1	/* UPMB, 32-bit	*/
#define CONFIG_SYS_OR2_PRELIM		0xfc000000	/* 64 MB	*/

#define CONFIG_VIDEO_MB862xx
#define CONFIG_VIDEO_MB862xx_ACCEL
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#define VIDEO_FB_16BPP_PIXEL_SWAP
#define VIDEO_FB_16BPP_WORD_SWAP
#define CONFIG_SPLASH_SCREEN
#define CONFIG_VIDEO_BMP_GZIP
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(2 << 20)	/* decompressed img */

/* SDRAM Clock frequency, 100MHz (0x0000) or 133MHz (0x10000) */
#define CONFIG_SYS_MB862xx_CCF		0x10000
/* SDRAM parameter */
#define CONFIG_SYS_MB862xx_MMR		0x4157BA63

/* Serial Port */

#define CONFIG_CONS_INDEX     1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)

#define CONFIG_BAUDRATE         115200

#define CONFIG_SYS_BAUDRATE_TABLE  \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}

#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
#define CONFIG_AUTO_COMPLETE	1	/* add autocompletion support */

/*
 * I2C
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	102124
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_FSL_I2C2_SPEED	102124
#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100

/* I2C RTC */
#define CONFIG_RTC_RX8025		/* Use Epson rx8025 rtc via i2c	*/
#define CONFIG_SYS_I2C_RTC_ADDR	0x32	/* at address 0x32		*/

/* I2C W83782G HW-Monitoring IC */
#define CONFIG_SYS_I2C_W83782G_ADDR	0x28	/* W83782G address 		*/

/* I2C temp sensor */
/* Socrates uses Maxim's	DS75, which is compatible with LM75 */
#define CONFIG_DTT_LM75		1
#define CONFIG_DTT_SENSORS	{4}		/* Sensor addresses	*/
#define CONFIG_SYS_DTT_MAX_TEMP	125
#define CONFIG_SYS_DTT_LOW_TEMP	-55
#define CONFIG_SYS_DTT_HYSTERESIS	3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4

/*
 * General PCI
 * Memory space is mapped 1-1.
 */
#define CONFIG_SYS_PCI_PHYS		0x80000000	/* 1G PCI TLB */

/* PCI is clocked by the external source at 33 MHz */
#define CONFIG_PCI_CLK_FREQ	33000000
#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M			*/
#define CONFIG_SYS_PCI1_IO_BASE	0xE2000000
#define CONFIG_SYS_PCI1_IO_PHYS	CONFIG_SYS_PCI1_IO_BASE
#define CONFIG_SYS_PCI1_IO_SIZE	0x01000000	/* 16M			*/

#if defined(CONFIG_PCI)
#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
#endif	/* CONFIG_PCI */

#define CONFIG_MII		1	/* MII PHY management */
#define CONFIG_TSEC1	1
#define CONFIG_TSEC1_NAME	"TSEC0"
#define CONFIG_TSEC3	1
#define CONFIG_TSEC3_NAME	"TSEC1"
#undef CONFIG_MPC85XX_FEC

#define TSEC1_PHY_ADDR		0
#define TSEC3_PHY_ADDR		1

#define TSEC1_PHYIDX		0
#define TSEC3_PHYIDX		0
#define TSEC1_FLAGS		TSEC_GIGABIT
#define TSEC3_FLAGS		TSEC_GIGABIT

/* Options are: TSEC[0,1] */
#define CONFIG_ETHPRIME		"TSEC0"
#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */

#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1

/*
 * Environment
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env	*/
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE		0x4000
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define	CONFIG_TIMESTAMP		/* Print image info with ts	*/

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */
#define CONFIG_CMD_BMP
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DTT
#undef CONFIG_CMD_EEPROM
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_REGINFO

#if defined(CONFIG_PCI)
    #define CONFIG_CMD_PCI
#endif

#undef CONFIG_WATCHDOG			/* watchdog disabled		*/

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address		*/

#if defined(CONFIG_CMD_KGDB)
    #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
    #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif

#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buf Size	*/
#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux	*/

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port*/
#endif

#define CONFIG_LOADADDR	 200000		/* default addr for tftp & bootm*/


#define CONFIG_PREBOOT	"echo;"	\
	"echo Welcome on the ABB Socrates Board;" \
	"echo"

#undef	CONFIG_BOOTARGS		/* the boot command will set bootargs	*/

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"consdev=ttyS0\0"						\
	"uboot_file=/home/tftp/syscon3/u-boot.bin\0"			\
	"bootfile=/home/tftp/syscon3/uImage\0"				\
	"fdt_file=/home/tftp/syscon3/socrates.dtb\0"			\
	"initrd_file=/home/tftp/syscon3/uinitrd.gz\0"			\
	"uboot_addr=FFFA0000\0"						\
	"kernel_addr=FE000000\0"					\
	"fdt_addr=FE1E0000\0"						\
	"ramdisk_addr=FE200000\0"					\
	"fdt_addr_r=B00000\0"						\
	"kernel_addr_r=200000\0"					\
	"ramdisk_addr_r=400000\0"					\
	"rootpath=/opt/eldk/ppc_85xxDP\0"				\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=$serverip:$rootpath\0"				\
	"addcons=setenv bootargs $bootargs "				\
		"console=$consdev,$baudrate\0"				\
	"addip=setenv bootargs $bootargs "				\
		"ip=$ipaddr:$serverip:$gatewayip:$netmask"		\
		":$hostname:$netdev:off panic=1\0"			\
	"boot_nor=run ramargs addcons;"					\
		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
		"tftp ${fdt_addr_r} ${fdt_file}; "			\
		"run nfsargs addip addcons;"				\
		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
	"update_uboot=tftp 100000 ${uboot_file};"			\
		"protect off fffa0000 ffffffff;"			\
		"era fffa0000 ffffffff;"				\
		"cp.b 100000 fffa0000 ${filesize};"			\
		"setenv filesize;saveenv\0"				\
	"update_kernel=tftp 100000 ${bootfile};"			\
		"era fe000000 fe1dffff;"				\
		"cp.b 100000 fe000000 ${filesize};"			\
		"setenv filesize;saveenv\0"				\
	"update_fdt=tftp 100000 ${fdt_file};" 				\
		"era fe1e0000 fe1fffff;"				\
		"cp.b 100000 fe1e0000 ${filesize};"			\
		"setenv filesize;saveenv\0"				\
	"update_initrd=tftp 100000 ${initrd_file};" 			\
		"era fe200000 fe9fffff;"				\
		"cp.b 100000 fe200000 ${filesize};"			\
		"setenv filesize;saveenv\0"				\
	"clean_data=era fea00000 fff5ffff\0"				\
	"usbargs=setenv bootargs root=/dev/sda1 rw\0" 			\
	"load_usb=usb start;" 						\
		"ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0"	\
	"boot_usb=run load_usb usbargs addcons;"			\
		"bootm ${kernel_addr_r} - ${fdt_addr};"			\
		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
	""
#define CONFIG_BOOTCOMMAND	"run boot_nor"

/* pass open firmware flat tree */

/* USB support */
#define CONFIG_USB_OHCI_NEW		1
#define CONFIG_PCI_OHCI			1
#define CONFIG_PCI_OHCI_DEVNO		3 /* Number in PCI list */
#define CONFIG_PCI_EHCI_DEVNO		(CONFIG_PCI_OHCI_DEVNO / 2)
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"ohci_pci"
#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS	1
#define CONFIG_DOS_PARTITION		1

#endif	/* __CONFIG_H */
Commit	Line	Data
5d108ac8 SP	1	/*
	2	* (C) Copyright 2008
	3	* Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
	4	*
	5	* Wolfgang Denk <wd@denx.de>
	6	* Copyright 2004 Freescale Semiconductor.
	7	* (C) Copyright 2002,2003 Motorola,Inc.
	8	* Xianghua Xiao <X.Xiao@motorola.com>
	9	*
3765b3e7	10	* SPDX-License-Identifier: GPL-2.0+
5d108ac8 SP	11	*/
	12
	13	/*
	14	* Socrates
	15	*/
	16
	17	#ifndef __CONFIG_H
	18	#define __CONFIG_H
	19
	20	/* High Level Configuration Options */
5d108ac8 SP	21	#define CONFIG_SOCRATES 1
5d108ac8 SP	22
2ae18241 WD	23	#define CONFIG_SYS_TEXT_BASE 0xfff80000
2ae18241 WD	24
842033e6	25	#define CONFIG_PCI_INDIRECT_BRIDGE
5d108ac8 SP	26
	27	#define CONFIG_TSEC_ENET /* tsec ethernet support */
	28
	29	#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
3e79b588	30	#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */
5d108ac8	31
5d108ac8 SP	32	/*
	33	* Only possible on E500 Version 2 or newer cores.
	34	*/
	35	#define CONFIG_ENABLE_36BIT_PHYS 1
	36
	37	/*
	38	* sysclk for MPC85xx
	39	*
	40	* Two valid values are:
	41	* 33000000
	42	* 66000000
	43	*
	44	* Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
	45	* is likely the desired value here, so that is now the default.
	46	* The board, however, can run at 66MHz. In any event, this value
	47	* must match the settings of some switches. Details can be found
	48	* in the README.mpc85xxads.
	49	*/
	50
	51	#ifndef CONFIG_SYS_CLK_FREQ
	52	#define CONFIG_SYS_CLK_FREQ 66666666
	53	#endif
	54
	55	/*
	56	* These can be toggled for performance analysis, otherwise use default.
	57	*/
	58	#define CONFIG_L2_CACHE /* toggle L2 cache */
	59	#define CONFIG_BTB /* toggle branch predition */
5d108ac8	60
6d0f6bcf	61	#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
5d108ac8	62
6d0f6bcf JCPV	63	#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
	64	#define CONFIG_SYS_MEMTEST_START 0x00400000
	65	#define CONFIG_SYS_MEMTEST_END 0x00C00000
5d108ac8	66
e46fedfe TT	67	#define CONFIG_SYS_CCSRBAR 0xE0000000
e46fedfe TT	68	#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
5d108ac8	69
be0bd823	70	/* DDR Setup */
be0bd823 KG	71	#undef CONFIG_FSL_DDR_INTERACTIVE
	72	#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
	73	#define CONFIG_DDR_SPD
	74
	75	#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
	76	#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
	77
6d0f6bcf JCPV	78	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	79	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
be0bd823 KG	80	#define CONFIG_VERY_BIG_RAM
be0bd823 KG	81
be0bd823 KG	82	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	83	#define CONFIG_CHIP_SELECTS_PER_CTRL 2
	84
	85	/* I2C addresses of SPD EEPROMs */
562788b0	86	#define SPD_EEPROM_ADDRESS 0x50 /* CTLR 0 DIMM 0 */
5d108ac8 SP	87
	88	#define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */
	89
	90	/* Hardcoded values, to use instead of SPD */
6d0f6bcf JCPV	91	#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
	92	#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102
	93	#define CONFIG_SYS_DDR_TIMING_0 0x00260802
	94	#define CONFIG_SYS_DDR_TIMING_1 0x3935D322
	95	#define CONFIG_SYS_DDR_TIMING_2 0x14904CC8
	96	#define CONFIG_SYS_DDR_MODE 0x00480432
	97	#define CONFIG_SYS_DDR_INTERVAL 0x030C0100
	98	#define CONFIG_SYS_DDR_CONFIG_2 0x04400000
	99	#define CONFIG_SYS_DDR_CONFIG 0xC3008000
	100	#define CONFIG_SYS_DDR_CLK_CONTROL 0x03800000
	101	#define CONFIG_SYS_SDRAM_SIZE 256 /* in Megs */
5d108ac8	102
5d108ac8 SP	103	/*
	104	* Flash on the LocalBus
	105	*/
6d0f6bcf	106	#define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
5d108ac8	107
6d0f6bcf JCPV	108	#define CONFIG_SYS_FLASH0 0xFE000000
	109	#define CONFIG_SYS_FLASH1 0xFC000000
	110	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
5d108ac8	111
6d0f6bcf JCPV	112	#define CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_FLASH1 /* Localbus flash start */
6d0f6bcf JCPV	113	#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH */
5d108ac8	114
6d0f6bcf JCPV	115	#define CONFIG_SYS_BR0_PRELIM 0xfe001001 /* port size 16bit */
	116	#define CONFIG_SYS_OR0_PRELIM 0xfe000030 /* 32MB Flash */
	117	#define CONFIG_SYS_BR1_PRELIM 0xfc001001 /* port size 16bit */
	118	#define CONFIG_SYS_OR1_PRELIM 0xfe000030 /* 32MB Flash */
5d108ac8	119
6d0f6bcf	120	#define CONFIG_SYS_FLASH_CFI /* flash is CFI compat. */
00b1883a	121	#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/
5d108ac8	122
6d0f6bcf JCPV	123	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
	124	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */
	125	#undef CONFIG_SYS_FLASH_CHECKSUM
	126	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	127	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
5d108ac8	128
14d0a02a	129	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
5d108ac8	130
6d0f6bcf JCPV	131	#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
	132	#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
	133	#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
	134	#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
5d108ac8	135
6d0f6bcf JCPV	136	#define CONFIG_SYS_INIT_RAM_LOCK 1
6d0f6bcf JCPV	137	#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
553f0982	138	#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size used area in RAM*/
5d108ac8	139
25ddd1fb	140	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	141	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
5d108ac8	142
47106ce1	143	#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384KiB for Mon */
6d0f6bcf	144	#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc */
3e79b588 DZ	145
3e79b588 DZ	146	/* FPGA and NAND */
6d0f6bcf JCPV	147	#define CONFIG_SYS_FPGA_BASE 0xc0000000
	148	#define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */
	149	#define CONFIG_SYS_HMI_BASE 0xc0010000
	150	#define CONFIG_SYS_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */
	151	#define CONFIG_SYS_OR3_PRELIM 0xfff00000 /* 1 MB */
	152
	153	#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70)
	154	#define CONFIG_SYS_MAX_NAND_DEVICE 1
3e79b588	155	#define CONFIG_CMD_NAND
5d108ac8	156
e64987a8	157	/* LIME GDC */
6d0f6bcf JCPV	158	#define CONFIG_SYS_LIME_BASE 0xc8000000
	159	#define CONFIG_SYS_LIME_SIZE 0x04000000 /* 64 MB */
	160	#define CONFIG_SYS_BR2_PRELIM 0xc80018a1 /* UPMB, 32-bit */
	161	#define CONFIG_SYS_OR2_PRELIM 0xfc000000 /* 64 MB */
e64987a8	162
e64987a8	163	#define CONFIG_VIDEO_MB862xx
5d16ca87	164	#define CONFIG_VIDEO_MB862xx_ACCEL
e64987a8 AG	165	#define CONFIG_VIDEO_LOGO
e64987a8 AG	166	#define CONFIG_VIDEO_BMP_LOGO
e64987a8	167	#define VIDEO_FB_16BPP_PIXEL_SWAP
229b6dce	168	#define VIDEO_FB_16BPP_WORD_SWAP
e64987a8 AG	169	#define CONFIG_SPLASH_SCREEN
e64987a8 AG	170	#define CONFIG_VIDEO_BMP_GZIP
6d0f6bcf	171	#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */
e64987a8	172
c28d3bbe WG	173	/* SDRAM Clock frequency, 100MHz (0x0000) or 133MHz (0x10000) */
	174	#define CONFIG_SYS_MB862xx_CCF 0x10000
	175	/* SDRAM parameter */
	176	#define CONFIG_SYS_MB862xx_MMR 0x4157BA63
	177
5d108ac8 SP	178	/* Serial Port */
	179
	180	#define CONFIG_CONS_INDEX 1
6d0f6bcf JCPV	181	#define CONFIG_SYS_NS16550_SERIAL
	182	#define CONFIG_SYS_NS16550_REG_SIZE 1
	183	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
5d108ac8	184
6d0f6bcf JCPV	185	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
6d0f6bcf JCPV	186	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
5d108ac8 SP	187
	188	#define CONFIG_BAUDRATE 115200
	189
6d0f6bcf	190	#define CONFIG_SYS_BAUDRATE_TABLE \
5d108ac8 SP	191	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
	192
	193	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
5be58f5f	194	#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
5d108ac8	195
5d108ac8 SP	196	/*
	197	* I2C
	198	*/
00f792e0 HS	199	#define CONFIG_SYS_I2C
	200	#define CONFIG_SYS_I2C_FSL
	201	#define CONFIG_SYS_FSL_I2C_SPEED 102124
	202	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	203	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	204	#define CONFIG_SYS_FSL_I2C2_SPEED 102124
	205	#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
	206	#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
3e79b588	207
5d108ac8	208	/* I2C RTC */
e18575d5	209	#define CONFIG_RTC_RX8025 /* Use Epson rx8025 rtc via i2c */
6d0f6bcf	210	#define CONFIG_SYS_I2C_RTC_ADDR 0x32 /* at address 0x32 */
5d108ac8	211
e64987a8	212	/* I2C W83782G HW-Monitoring IC */
6d0f6bcf	213	#define CONFIG_SYS_I2C_W83782G_ADDR 0x28 /* W83782G address */
e64987a8	214
2f7468ae SP	215	/* I2C temp sensor */
	216	/* Socrates uses Maxim's DS75, which is compatible with LM75 */
	217	#define CONFIG_DTT_LM75 1
	218	#define CONFIG_DTT_SENSORS {4} /* Sensor addresses */
6d0f6bcf JCPV	219	#define CONFIG_SYS_DTT_MAX_TEMP 125
	220	#define CONFIG_SYS_DTT_LOW_TEMP -55
	221	#define CONFIG_SYS_DTT_HYSTERESIS 3
	222	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
2f7468ae	223
5d108ac8 SP	224	/*
	225	* General PCI
	226	* Memory space is mapped 1-1.
	227	*/
6d0f6bcf	228	#define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */
5d108ac8	229
5e1882df SP	230	/* PCI is clocked by the external source at 33 MHz */
5e1882df SP	231	#define CONFIG_PCI_CLK_FREQ 33000000
6d0f6bcf JCPV	232	#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
	233	#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
	234	#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
	235	#define CONFIG_SYS_PCI1_IO_BASE 0xE2000000
	236	#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
	237	#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */
5d108ac8 SP	238
5d108ac8 SP	239	#if defined(CONFIG_PCI)
d39e6851	240	#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
5d108ac8 SP	241	#endif /* CONFIG_PCI */
5d108ac8 SP	242
5d108ac8 SP	243	#define CONFIG_MII 1 /* MII PHY management */
	244	#define CONFIG_TSEC1 1
	245	#define CONFIG_TSEC1_NAME "TSEC0"
2f845dc2 SP	246	#define CONFIG_TSEC3 1
2f845dc2 SP	247	#define CONFIG_TSEC3_NAME "TSEC1"
5d108ac8 SP	248	#undef CONFIG_MPC85XX_FEC
	249
	250	#define TSEC1_PHY_ADDR 0
2f845dc2	251	#define TSEC3_PHY_ADDR 1
5d108ac8 SP	252
5d108ac8 SP	253	#define TSEC1_PHYIDX 0
2f845dc2	254	#define TSEC3_PHYIDX 0
5d108ac8	255	#define TSEC1_FLAGS TSEC_GIGABIT
2f845dc2	256	#define TSEC3_FLAGS TSEC_GIGABIT
5d108ac8	257
2f845dc2	258	/* Options are: TSEC[0,1] */
5d108ac8 SP	259	#define CONFIG_ETHPRIME "TSEC0"
	260	#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
	261
e18575d5 SP	262	#define CONFIG_HAS_ETH0
	263	#define CONFIG_HAS_ETH1
	264
5d108ac8 SP	265	/*
	266	* Environment
	267	*/
5a1aceb0	268	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586	269	#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
6d0f6bcf	270	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
0e8d1586 JCPV	271	#define CONFIG_ENV_SIZE 0x4000
	272	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
	273	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
5d108ac8 SP	274
5d108ac8 SP	275	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	276	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
5d108ac8 SP	277
	278	#define CONFIG_TIMESTAMP /* Print image info with ts */
	279
5d108ac8 SP	280	/*
	281	* BOOTP options
	282	*/
	283	#define CONFIG_BOOTP_BOOTFILESIZE
	284	#define CONFIG_BOOTP_BOOTPATH
	285	#define CONFIG_BOOTP_GATEWAY
	286	#define CONFIG_BOOTP_HOSTNAME
	287
5d108ac8 SP	288	/*
	289	* Command line configuration.
	290	*/
47106ce1	291	#define CONFIG_CMD_BMP
5d108ac8	292	#define CONFIG_CMD_DATE
2f7468ae	293	#define CONFIG_CMD_DTT
5d108ac8	294	#undef CONFIG_CMD_EEPROM
3e79b588	295	#define CONFIG_CMD_SDRAM
199e262e	296	#define CONFIG_CMD_REGINFO
5d108ac8 SP	297
	298	#if defined(CONFIG_PCI)
	299	#define CONFIG_CMD_PCI
	300	#endif
	301
5d108ac8 SP	302	#undef CONFIG_WATCHDOG /* watchdog disabled */
	303
	304	/*
	305	* Miscellaneous configurable options
	306	*/
6d0f6bcf JCPV	307	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	308	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
5d108ac8 SP	309
5d108ac8 SP	310	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	311	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
5d108ac8	312	#else
6d0f6bcf	313	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
5d108ac8 SP	314	#endif
5d108ac8 SP	315
6d0f6bcf JCPV	316	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buf Size */
	317	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	318	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
5d108ac8 SP	319
	320	/*
	321	* For booting Linux, the board info and command line data
	322	* have to be in the first 8 MB of memory, since this is
	323	* the maximum mapped by the Linux kernel during initialization.
	324	*/
6d0f6bcf	325	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
5d108ac8	326
5d108ac8 SP	327	#if defined(CONFIG_CMD_KGDB)
5d108ac8 SP	328	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/
5d108ac8 SP	329	#endif
5d108ac8 SP	330
5d108ac8 SP	331	#define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/
5d108ac8 SP	332
5d108ac8 SP	333
5d108ac8 SP	334	#define CONFIG_PREBOOT "echo;" \
3e79b588	335	"echo Welcome on the ABB Socrates Board;" \
5d108ac8 SP	336	"echo"
	337
	338	#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
	339
	340	#define CONFIG_EXTRA_ENV_SETTINGS \
5d108ac8 SP	341	"netdev=eth0\0" \
5d108ac8 SP	342	"consdev=ttyS0\0" \
3e79b588 DZ	343	"uboot_file=/home/tftp/syscon3/u-boot.bin\0" \
	344	"bootfile=/home/tftp/syscon3/uImage\0" \
	345	"fdt_file=/home/tftp/syscon3/socrates.dtb\0" \
	346	"initrd_file=/home/tftp/syscon3/uinitrd.gz\0" \
	347	"uboot_addr=FFFA0000\0" \
	348	"kernel_addr=FE000000\0" \
	349	"fdt_addr=FE1E0000\0" \
	350	"ramdisk_addr=FE200000\0" \
	351	"fdt_addr_r=B00000\0" \
	352	"kernel_addr_r=200000\0" \
	353	"ramdisk_addr_r=400000\0" \
	354	"rootpath=/opt/eldk/ppc_85xxDP\0" \
	355	"ramargs=setenv bootargs root=/dev/ram rw\0" \
5d108ac8 SP	356	"nfsargs=setenv bootargs root=/dev/nfs rw " \
5d108ac8 SP	357	"nfsroot=$serverip:$rootpath\0" \
3e79b588 DZ	358	"addcons=setenv bootargs $bootargs " \
3e79b588 DZ	359	"console=$consdev,$baudrate\0" \
5d108ac8 SP	360	"addip=setenv bootargs $bootargs " \
	361	"ip=$ipaddr:$serverip:$gatewayip:$netmask" \
	362	":$hostname:$netdev:off panic=1\0" \
3e79b588	363	"boot_nor=run ramargs addcons;" \
e18575d5	364	"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
e18575d5 SP	365	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
	366	"tftp ${fdt_addr_r} ${fdt_file}; " \
	367	"run nfsargs addip addcons;" \
	368	"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
3e79b588 DZ	369	"update_uboot=tftp 100000 ${uboot_file};" \
	370	"protect off fffa0000 ffffffff;" \
	371	"era fffa0000 ffffffff;" \
	372	"cp.b 100000 fffa0000 ${filesize};" \
	373	"setenv filesize;saveenv\0" \
	374	"update_kernel=tftp 100000 ${bootfile};" \
	375	"era fe000000 fe1dffff;" \
	376	"cp.b 100000 fe000000 ${filesize};" \
5d108ac8	377	"setenv filesize;saveenv\0" \
3e79b588 DZ	378	"update_fdt=tftp 100000 ${fdt_file};" \
	379	"era fe1e0000 fe1fffff;" \
	380	"cp.b 100000 fe1e0000 ${filesize};" \
	381	"setenv filesize;saveenv\0" \
	382	"update_initrd=tftp 100000 ${initrd_file};" \
	383	"era fe200000 fe9fffff;" \
	384	"cp.b 100000 fe200000 ${filesize};" \
	385	"setenv filesize;saveenv\0" \
	386	"clean_data=era fea00000 fff5ffff\0" \
	387	"usbargs=setenv bootargs root=/dev/sda1 rw\0" \
	388	"load_usb=usb start;" \
	389	"ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0" \
	390	"boot_usb=run load_usb usbargs addcons;" \
	391	"bootm ${kernel_addr_r} - ${fdt_addr};" \
	392	"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
5d108ac8	393	""
3e79b588	394	#define CONFIG_BOOTCOMMAND "run boot_nor"
5d108ac8	395
e18575d5	396	/* pass open firmware flat tree */
e18575d5	397
791e1dba SP	398	/* USB support */
	399	#define CONFIG_USB_OHCI_NEW 1
	400	#define CONFIG_PCI_OHCI 1
	401	#define CONFIG_PCI_OHCI_DEVNO 3 /* Number in PCI list */
e90fb6af	402	#define CONFIG_PCI_EHCI_DEVNO (CONFIG_PCI_OHCI_DEVNO / 2)
6d0f6bcf JCPV	403	#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
	404	#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
	405	#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
791e1dba	406	#define CONFIG_DOS_PARTITION 1
791e1dba	407
5d108ac8	408	#endif /* __CONFIG_H */