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Commit | Line | Data |
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5d108ac8 SP |
1 | /* |
2 | * (C) Copyright 2008 | |
3 | * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. | |
4 | * | |
5 | * Wolfgang Denk <wd@denx.de> | |
6 | * Copyright 2004 Freescale Semiconductor. | |
7 | * (C) Copyright 2002,2003 Motorola,Inc. | |
8 | * Xianghua Xiao <X.Xiao@motorola.com> | |
9 | * | |
3765b3e7 | 10 | * SPDX-License-Identifier: GPL-2.0+ |
5d108ac8 SP |
11 | */ |
12 | ||
13 | /* | |
14 | * Socrates | |
15 | */ | |
16 | ||
17 | #ifndef __CONFIG_H | |
18 | #define __CONFIG_H | |
19 | ||
20 | /* High Level Configuration Options */ | |
21 | #define CONFIG_BOOKE 1 /* BOOKE */ | |
22 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
5d108ac8 SP |
23 | #define CONFIG_MPC8544 1 |
24 | #define CONFIG_SOCRATES 1 | |
10865143 | 25 | #define CONFIG_DISPLAY_BOARDINFO |
5d108ac8 | 26 | |
2ae18241 WD |
27 | #define CONFIG_SYS_TEXT_BASE 0xfff80000 |
28 | ||
5d108ac8 | 29 | #define CONFIG_PCI |
842033e6 | 30 | #define CONFIG_PCI_INDIRECT_BRIDGE |
5d108ac8 SP |
31 | |
32 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
33 | ||
34 | #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ | |
3e79b588 | 35 | #define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */ |
5d108ac8 SP |
36 | |
37 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ | |
38 | ||
39 | /* | |
40 | * Only possible on E500 Version 2 or newer cores. | |
41 | */ | |
42 | #define CONFIG_ENABLE_36BIT_PHYS 1 | |
43 | ||
44 | /* | |
45 | * sysclk for MPC85xx | |
46 | * | |
47 | * Two valid values are: | |
48 | * 33000000 | |
49 | * 66000000 | |
50 | * | |
51 | * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz | |
52 | * is likely the desired value here, so that is now the default. | |
53 | * The board, however, can run at 66MHz. In any event, this value | |
54 | * must match the settings of some switches. Details can be found | |
55 | * in the README.mpc85xxads. | |
56 | */ | |
57 | ||
58 | #ifndef CONFIG_SYS_CLK_FREQ | |
59 | #define CONFIG_SYS_CLK_FREQ 66666666 | |
60 | #endif | |
61 | ||
62 | /* | |
63 | * These can be toggled for performance analysis, otherwise use default. | |
64 | */ | |
65 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
66 | #define CONFIG_BTB /* toggle branch predition */ | |
5d108ac8 | 67 | |
6d0f6bcf | 68 | #define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ |
5d108ac8 | 69 | |
6d0f6bcf JCPV |
70 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
71 | #define CONFIG_SYS_MEMTEST_START 0x00400000 | |
72 | #define CONFIG_SYS_MEMTEST_END 0x00C00000 | |
5d108ac8 | 73 | |
e46fedfe TT |
74 | #define CONFIG_SYS_CCSRBAR 0xE0000000 |
75 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
5d108ac8 | 76 | |
be0bd823 | 77 | /* DDR Setup */ |
5614e71b | 78 | #define CONFIG_SYS_FSL_DDR2 |
be0bd823 KG |
79 | #undef CONFIG_FSL_DDR_INTERACTIVE |
80 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ | |
81 | #define CONFIG_DDR_SPD | |
82 | ||
83 | #undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ | |
84 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
85 | ||
6d0f6bcf JCPV |
86 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
87 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
be0bd823 KG |
88 | #define CONFIG_VERY_BIG_RAM |
89 | ||
90 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
91 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
92 | #define CONFIG_CHIP_SELECTS_PER_CTRL 2 | |
93 | ||
94 | /* I2C addresses of SPD EEPROMs */ | |
562788b0 | 95 | #define SPD_EEPROM_ADDRESS 0x50 /* CTLR 0 DIMM 0 */ |
5d108ac8 SP |
96 | |
97 | #define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */ | |
98 | ||
99 | /* Hardcoded values, to use instead of SPD */ | |
6d0f6bcf JCPV |
100 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f |
101 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 | |
102 | #define CONFIG_SYS_DDR_TIMING_0 0x00260802 | |
103 | #define CONFIG_SYS_DDR_TIMING_1 0x3935D322 | |
104 | #define CONFIG_SYS_DDR_TIMING_2 0x14904CC8 | |
105 | #define CONFIG_SYS_DDR_MODE 0x00480432 | |
106 | #define CONFIG_SYS_DDR_INTERVAL 0x030C0100 | |
107 | #define CONFIG_SYS_DDR_CONFIG_2 0x04400000 | |
108 | #define CONFIG_SYS_DDR_CONFIG 0xC3008000 | |
109 | #define CONFIG_SYS_DDR_CLK_CONTROL 0x03800000 | |
110 | #define CONFIG_SYS_SDRAM_SIZE 256 /* in Megs */ | |
5d108ac8 | 111 | |
5d108ac8 SP |
112 | /* |
113 | * Flash on the LocalBus | |
114 | */ | |
6d0f6bcf | 115 | #define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ |
5d108ac8 | 116 | |
6d0f6bcf JCPV |
117 | #define CONFIG_SYS_FLASH0 0xFE000000 |
118 | #define CONFIG_SYS_FLASH1 0xFC000000 | |
119 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 } | |
5d108ac8 | 120 | |
6d0f6bcf JCPV |
121 | #define CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_FLASH1 /* Localbus flash start */ |
122 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH */ | |
5d108ac8 | 123 | |
6d0f6bcf JCPV |
124 | #define CONFIG_SYS_BR0_PRELIM 0xfe001001 /* port size 16bit */ |
125 | #define CONFIG_SYS_OR0_PRELIM 0xfe000030 /* 32MB Flash */ | |
126 | #define CONFIG_SYS_BR1_PRELIM 0xfc001001 /* port size 16bit */ | |
127 | #define CONFIG_SYS_OR1_PRELIM 0xfe000030 /* 32MB Flash */ | |
5d108ac8 | 128 | |
6d0f6bcf | 129 | #define CONFIG_SYS_FLASH_CFI /* flash is CFI compat. */ |
00b1883a | 130 | #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/ |
5d108ac8 | 131 | |
6d0f6bcf JCPV |
132 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
133 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */ | |
134 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
135 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
136 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
5d108ac8 | 137 | |
14d0a02a | 138 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
5d108ac8 | 139 | |
6d0f6bcf JCPV |
140 | #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ |
141 | #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ | |
142 | #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ | |
143 | #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/ | |
5d108ac8 | 144 | |
6d0f6bcf JCPV |
145 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
146 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ | |
553f0982 | 147 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size used area in RAM*/ |
5d108ac8 | 148 | |
25ddd1fb | 149 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 150 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
5d108ac8 | 151 | |
47106ce1 | 152 | #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384KiB for Mon */ |
6d0f6bcf | 153 | #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc */ |
3e79b588 DZ |
154 | |
155 | /* FPGA and NAND */ | |
6d0f6bcf JCPV |
156 | #define CONFIG_SYS_FPGA_BASE 0xc0000000 |
157 | #define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */ | |
158 | #define CONFIG_SYS_HMI_BASE 0xc0010000 | |
159 | #define CONFIG_SYS_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */ | |
160 | #define CONFIG_SYS_OR3_PRELIM 0xfff00000 /* 1 MB */ | |
161 | ||
162 | #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70) | |
163 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
3e79b588 | 164 | #define CONFIG_CMD_NAND |
5d108ac8 | 165 | |
e64987a8 | 166 | /* LIME GDC */ |
6d0f6bcf JCPV |
167 | #define CONFIG_SYS_LIME_BASE 0xc8000000 |
168 | #define CONFIG_SYS_LIME_SIZE 0x04000000 /* 64 MB */ | |
169 | #define CONFIG_SYS_BR2_PRELIM 0xc80018a1 /* UPMB, 32-bit */ | |
170 | #define CONFIG_SYS_OR2_PRELIM 0xfc000000 /* 64 MB */ | |
e64987a8 AG |
171 | |
172 | #define CONFIG_VIDEO | |
173 | #define CONFIG_VIDEO_MB862xx | |
5d16ca87 | 174 | #define CONFIG_VIDEO_MB862xx_ACCEL |
e64987a8 AG |
175 | #define CONFIG_CFB_CONSOLE |
176 | #define CONFIG_VIDEO_LOGO | |
177 | #define CONFIG_VIDEO_BMP_LOGO | |
178 | #define CONFIG_CONSOLE_EXTRA_INFO | |
179 | #define VIDEO_FB_16BPP_PIXEL_SWAP | |
229b6dce | 180 | #define VIDEO_FB_16BPP_WORD_SWAP |
e64987a8 | 181 | #define CONFIG_VGA_AS_SINGLE_DEVICE |
6d0f6bcf | 182 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV |
e64987a8 AG |
183 | #define CONFIG_VIDEO_SW_CURSOR |
184 | #define CONFIG_SPLASH_SCREEN | |
185 | #define CONFIG_VIDEO_BMP_GZIP | |
6d0f6bcf | 186 | #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */ |
e64987a8 | 187 | |
c28d3bbe WG |
188 | /* SDRAM Clock frequency, 100MHz (0x0000) or 133MHz (0x10000) */ |
189 | #define CONFIG_SYS_MB862xx_CCF 0x10000 | |
190 | /* SDRAM parameter */ | |
191 | #define CONFIG_SYS_MB862xx_MMR 0x4157BA63 | |
192 | ||
5d108ac8 SP |
193 | /* Serial Port */ |
194 | ||
195 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
196 | #define CONFIG_SYS_NS16550_SERIAL |
197 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
198 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
5d108ac8 | 199 | |
6d0f6bcf JCPV |
200 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
201 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
5d108ac8 SP |
202 | |
203 | #define CONFIG_BAUDRATE 115200 | |
204 | ||
6d0f6bcf | 205 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
5d108ac8 SP |
206 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
207 | ||
208 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
5be58f5f | 209 | #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ |
5d108ac8 SP |
210 | |
211 | ||
212 | /* | |
213 | * I2C | |
214 | */ | |
00f792e0 HS |
215 | #define CONFIG_SYS_I2C |
216 | #define CONFIG_SYS_I2C_FSL | |
217 | #define CONFIG_SYS_FSL_I2C_SPEED 102124 | |
218 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
219 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
220 | #define CONFIG_SYS_FSL_I2C2_SPEED 102124 | |
221 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
222 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
3e79b588 | 223 | |
5d108ac8 | 224 | /* I2C RTC */ |
e18575d5 | 225 | #define CONFIG_RTC_RX8025 /* Use Epson rx8025 rtc via i2c */ |
6d0f6bcf | 226 | #define CONFIG_SYS_I2C_RTC_ADDR 0x32 /* at address 0x32 */ |
5d108ac8 | 227 | |
e64987a8 | 228 | /* I2C W83782G HW-Monitoring IC */ |
6d0f6bcf | 229 | #define CONFIG_SYS_I2C_W83782G_ADDR 0x28 /* W83782G address */ |
e64987a8 | 230 | |
2f7468ae SP |
231 | /* I2C temp sensor */ |
232 | /* Socrates uses Maxim's DS75, which is compatible with LM75 */ | |
233 | #define CONFIG_DTT_LM75 1 | |
234 | #define CONFIG_DTT_SENSORS {4} /* Sensor addresses */ | |
6d0f6bcf JCPV |
235 | #define CONFIG_SYS_DTT_MAX_TEMP 125 |
236 | #define CONFIG_SYS_DTT_LOW_TEMP -55 | |
237 | #define CONFIG_SYS_DTT_HYSTERESIS 3 | |
238 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 | |
2f7468ae | 239 | |
5d108ac8 SP |
240 | /* |
241 | * General PCI | |
242 | * Memory space is mapped 1-1. | |
243 | */ | |
6d0f6bcf | 244 | #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ |
5d108ac8 | 245 | |
5e1882df SP |
246 | /* PCI is clocked by the external source at 33 MHz */ |
247 | #define CONFIG_PCI_CLK_FREQ 33000000 | |
6d0f6bcf JCPV |
248 | #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 |
249 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE | |
250 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ | |
251 | #define CONFIG_SYS_PCI1_IO_BASE 0xE2000000 | |
252 | #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE | |
253 | #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ | |
5d108ac8 SP |
254 | |
255 | #if defined(CONFIG_PCI) | |
5d108ac8 | 256 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
d39e6851 | 257 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
5d108ac8 SP |
258 | #endif /* CONFIG_PCI */ |
259 | ||
260 | ||
5d108ac8 SP |
261 | #define CONFIG_MII 1 /* MII PHY management */ |
262 | #define CONFIG_TSEC1 1 | |
263 | #define CONFIG_TSEC1_NAME "TSEC0" | |
2f845dc2 SP |
264 | #define CONFIG_TSEC3 1 |
265 | #define CONFIG_TSEC3_NAME "TSEC1" | |
5d108ac8 SP |
266 | #undef CONFIG_MPC85XX_FEC |
267 | ||
268 | #define TSEC1_PHY_ADDR 0 | |
2f845dc2 | 269 | #define TSEC3_PHY_ADDR 1 |
5d108ac8 SP |
270 | |
271 | #define TSEC1_PHYIDX 0 | |
2f845dc2 | 272 | #define TSEC3_PHYIDX 0 |
5d108ac8 | 273 | #define TSEC1_FLAGS TSEC_GIGABIT |
2f845dc2 | 274 | #define TSEC3_FLAGS TSEC_GIGABIT |
5d108ac8 | 275 | |
2f845dc2 | 276 | /* Options are: TSEC[0,1] */ |
5d108ac8 SP |
277 | #define CONFIG_ETHPRIME "TSEC0" |
278 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
279 | ||
e18575d5 SP |
280 | #define CONFIG_HAS_ETH0 |
281 | #define CONFIG_HAS_ETH1 | |
282 | ||
5d108ac8 SP |
283 | /* |
284 | * Environment | |
285 | */ | |
5a1aceb0 | 286 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 | 287 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ |
6d0f6bcf | 288 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
0e8d1586 JCPV |
289 | #define CONFIG_ENV_SIZE 0x4000 |
290 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) | |
291 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
5d108ac8 SP |
292 | |
293 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 294 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
5d108ac8 SP |
295 | |
296 | #define CONFIG_TIMESTAMP /* Print image info with ts */ | |
297 | ||
298 | ||
299 | /* | |
300 | * BOOTP options | |
301 | */ | |
302 | #define CONFIG_BOOTP_BOOTFILESIZE | |
303 | #define CONFIG_BOOTP_BOOTPATH | |
304 | #define CONFIG_BOOTP_GATEWAY | |
305 | #define CONFIG_BOOTP_HOSTNAME | |
306 | ||
307 | ||
308 | /* | |
309 | * Command line configuration. | |
310 | */ | |
47106ce1 | 311 | #define CONFIG_CMD_BMP |
5d108ac8 SP |
312 | #define CONFIG_CMD_DATE |
313 | #define CONFIG_CMD_DHCP | |
2f7468ae | 314 | #define CONFIG_CMD_DTT |
5d108ac8 | 315 | #undef CONFIG_CMD_EEPROM |
47106ce1 | 316 | #define CONFIG_CMD_EXT2 /* EXT2 Support */ |
5d108ac8 | 317 | #define CONFIG_CMD_I2C |
3e79b588 | 318 | #define CONFIG_CMD_SDRAM |
5d108ac8 | 319 | #define CONFIG_CMD_MII |
5d108ac8 | 320 | #define CONFIG_CMD_PING |
5d108ac8 | 321 | #define CONFIG_CMD_SNTP |
791e1dba | 322 | #define CONFIG_CMD_USB |
199e262e | 323 | #define CONFIG_CMD_REGINFO |
5d108ac8 SP |
324 | |
325 | #if defined(CONFIG_PCI) | |
326 | #define CONFIG_CMD_PCI | |
327 | #endif | |
328 | ||
5d108ac8 SP |
329 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
330 | ||
331 | /* | |
332 | * Miscellaneous configurable options | |
333 | */ | |
6d0f6bcf JCPV |
334 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
335 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
5d108ac8 SP |
336 | |
337 | #if defined(CONFIG_CMD_KGDB) | |
6d0f6bcf | 338 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
5d108ac8 | 339 | #else |
6d0f6bcf | 340 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
5d108ac8 SP |
341 | #endif |
342 | ||
6d0f6bcf JCPV |
343 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buf Size */ |
344 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
345 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
5d108ac8 SP |
346 | |
347 | /* | |
348 | * For booting Linux, the board info and command line data | |
349 | * have to be in the first 8 MB of memory, since this is | |
350 | * the maximum mapped by the Linux kernel during initialization. | |
351 | */ | |
6d0f6bcf | 352 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
5d108ac8 | 353 | |
5d108ac8 SP |
354 | #if defined(CONFIG_CMD_KGDB) |
355 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/ | |
5d108ac8 SP |
356 | #endif |
357 | ||
358 | ||
359 | #define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/ | |
360 | ||
3e79b588 | 361 | #define CONFIG_BOOTDELAY 1 /* -1 disables auto-boot */ |
5d108ac8 SP |
362 | |
363 | #define CONFIG_PREBOOT "echo;" \ | |
3e79b588 | 364 | "echo Welcome on the ABB Socrates Board;" \ |
5d108ac8 SP |
365 | "echo" |
366 | ||
367 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ | |
368 | ||
369 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
5d108ac8 SP |
370 | "netdev=eth0\0" \ |
371 | "consdev=ttyS0\0" \ | |
3e79b588 DZ |
372 | "uboot_file=/home/tftp/syscon3/u-boot.bin\0" \ |
373 | "bootfile=/home/tftp/syscon3/uImage\0" \ | |
374 | "fdt_file=/home/tftp/syscon3/socrates.dtb\0" \ | |
375 | "initrd_file=/home/tftp/syscon3/uinitrd.gz\0" \ | |
376 | "uboot_addr=FFFA0000\0" \ | |
377 | "kernel_addr=FE000000\0" \ | |
378 | "fdt_addr=FE1E0000\0" \ | |
379 | "ramdisk_addr=FE200000\0" \ | |
380 | "fdt_addr_r=B00000\0" \ | |
381 | "kernel_addr_r=200000\0" \ | |
382 | "ramdisk_addr_r=400000\0" \ | |
383 | "rootpath=/opt/eldk/ppc_85xxDP\0" \ | |
384 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
5d108ac8 SP |
385 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
386 | "nfsroot=$serverip:$rootpath\0" \ | |
3e79b588 DZ |
387 | "addcons=setenv bootargs $bootargs " \ |
388 | "console=$consdev,$baudrate\0" \ | |
5d108ac8 SP |
389 | "addip=setenv bootargs $bootargs " \ |
390 | "ip=$ipaddr:$serverip:$gatewayip:$netmask" \ | |
391 | ":$hostname:$netdev:off panic=1\0" \ | |
3e79b588 | 392 | "boot_nor=run ramargs addcons;" \ |
e18575d5 | 393 | "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ |
e18575d5 SP |
394 | "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ |
395 | "tftp ${fdt_addr_r} ${fdt_file}; " \ | |
396 | "run nfsargs addip addcons;" \ | |
397 | "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ | |
3e79b588 DZ |
398 | "update_uboot=tftp 100000 ${uboot_file};" \ |
399 | "protect off fffa0000 ffffffff;" \ | |
400 | "era fffa0000 ffffffff;" \ | |
401 | "cp.b 100000 fffa0000 ${filesize};" \ | |
402 | "setenv filesize;saveenv\0" \ | |
403 | "update_kernel=tftp 100000 ${bootfile};" \ | |
404 | "era fe000000 fe1dffff;" \ | |
405 | "cp.b 100000 fe000000 ${filesize};" \ | |
5d108ac8 | 406 | "setenv filesize;saveenv\0" \ |
3e79b588 DZ |
407 | "update_fdt=tftp 100000 ${fdt_file};" \ |
408 | "era fe1e0000 fe1fffff;" \ | |
409 | "cp.b 100000 fe1e0000 ${filesize};" \ | |
410 | "setenv filesize;saveenv\0" \ | |
411 | "update_initrd=tftp 100000 ${initrd_file};" \ | |
412 | "era fe200000 fe9fffff;" \ | |
413 | "cp.b 100000 fe200000 ${filesize};" \ | |
414 | "setenv filesize;saveenv\0" \ | |
415 | "clean_data=era fea00000 fff5ffff\0" \ | |
416 | "usbargs=setenv bootargs root=/dev/sda1 rw\0" \ | |
417 | "load_usb=usb start;" \ | |
418 | "ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0" \ | |
419 | "boot_usb=run load_usb usbargs addcons;" \ | |
420 | "bootm ${kernel_addr_r} - ${fdt_addr};" \ | |
421 | "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ | |
5d108ac8 | 422 | "" |
3e79b588 | 423 | #define CONFIG_BOOTCOMMAND "run boot_nor" |
5d108ac8 | 424 | |
e18575d5 | 425 | /* pass open firmware flat tree */ |
e18575d5 | 426 | |
791e1dba SP |
427 | /* USB support */ |
428 | #define CONFIG_USB_OHCI_NEW 1 | |
429 | #define CONFIG_PCI_OHCI 1 | |
430 | #define CONFIG_PCI_OHCI_DEVNO 3 /* Number in PCI list */ | |
e90fb6af | 431 | #define CONFIG_PCI_EHCI_DEVNO (CONFIG_PCI_OHCI_DEVNO / 2) |
6d0f6bcf JCPV |
432 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 |
433 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" | |
434 | #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 | |
791e1dba SP |
435 | #define CONFIG_DOS_PARTITION 1 |
436 | #define CONFIG_USB_STORAGE 1 | |
437 | ||
5d108ac8 | 438 | #endif /* __CONFIG_H */ |