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Commit | Line | Data |
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5d108ac8 SP |
1 | /* |
2 | * (C) Copyright 2008 | |
3 | * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. | |
4 | * | |
5 | * Wolfgang Denk <wd@denx.de> | |
6 | * Copyright 2004 Freescale Semiconductor. | |
7 | * (C) Copyright 2002,2003 Motorola,Inc. | |
8 | * Xianghua Xiao <X.Xiao@motorola.com> | |
9 | * | |
3765b3e7 | 10 | * SPDX-License-Identifier: GPL-2.0+ |
5d108ac8 SP |
11 | */ |
12 | ||
13 | /* | |
14 | * Socrates | |
15 | */ | |
16 | ||
17 | #ifndef __CONFIG_H | |
18 | #define __CONFIG_H | |
19 | ||
20 | /* High Level Configuration Options */ | |
21 | #define CONFIG_BOOKE 1 /* BOOKE */ | |
22 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
5d108ac8 SP |
23 | #define CONFIG_MPC8544 1 |
24 | #define CONFIG_SOCRATES 1 | |
25 | ||
2ae18241 WD |
26 | #define CONFIG_SYS_TEXT_BASE 0xfff80000 |
27 | ||
842033e6 | 28 | #define CONFIG_PCI_INDIRECT_BRIDGE |
5d108ac8 SP |
29 | |
30 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
31 | ||
32 | #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ | |
3e79b588 | 33 | #define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */ |
5d108ac8 SP |
34 | |
35 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ | |
36 | ||
37 | /* | |
38 | * Only possible on E500 Version 2 or newer cores. | |
39 | */ | |
40 | #define CONFIG_ENABLE_36BIT_PHYS 1 | |
41 | ||
42 | /* | |
43 | * sysclk for MPC85xx | |
44 | * | |
45 | * Two valid values are: | |
46 | * 33000000 | |
47 | * 66000000 | |
48 | * | |
49 | * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz | |
50 | * is likely the desired value here, so that is now the default. | |
51 | * The board, however, can run at 66MHz. In any event, this value | |
52 | * must match the settings of some switches. Details can be found | |
53 | * in the README.mpc85xxads. | |
54 | */ | |
55 | ||
56 | #ifndef CONFIG_SYS_CLK_FREQ | |
57 | #define CONFIG_SYS_CLK_FREQ 66666666 | |
58 | #endif | |
59 | ||
60 | /* | |
61 | * These can be toggled for performance analysis, otherwise use default. | |
62 | */ | |
63 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
64 | #define CONFIG_BTB /* toggle branch predition */ | |
5d108ac8 | 65 | |
6d0f6bcf | 66 | #define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ |
5d108ac8 | 67 | |
6d0f6bcf JCPV |
68 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
69 | #define CONFIG_SYS_MEMTEST_START 0x00400000 | |
70 | #define CONFIG_SYS_MEMTEST_END 0x00C00000 | |
5d108ac8 | 71 | |
e46fedfe TT |
72 | #define CONFIG_SYS_CCSRBAR 0xE0000000 |
73 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
5d108ac8 | 74 | |
be0bd823 | 75 | /* DDR Setup */ |
5614e71b | 76 | #define CONFIG_SYS_FSL_DDR2 |
be0bd823 KG |
77 | #undef CONFIG_FSL_DDR_INTERACTIVE |
78 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ | |
79 | #define CONFIG_DDR_SPD | |
80 | ||
81 | #undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ | |
82 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
83 | ||
6d0f6bcf JCPV |
84 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
85 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
be0bd823 KG |
86 | #define CONFIG_VERY_BIG_RAM |
87 | ||
88 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
89 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
90 | #define CONFIG_CHIP_SELECTS_PER_CTRL 2 | |
91 | ||
92 | /* I2C addresses of SPD EEPROMs */ | |
562788b0 | 93 | #define SPD_EEPROM_ADDRESS 0x50 /* CTLR 0 DIMM 0 */ |
5d108ac8 SP |
94 | |
95 | #define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */ | |
96 | ||
97 | /* Hardcoded values, to use instead of SPD */ | |
6d0f6bcf JCPV |
98 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f |
99 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 | |
100 | #define CONFIG_SYS_DDR_TIMING_0 0x00260802 | |
101 | #define CONFIG_SYS_DDR_TIMING_1 0x3935D322 | |
102 | #define CONFIG_SYS_DDR_TIMING_2 0x14904CC8 | |
103 | #define CONFIG_SYS_DDR_MODE 0x00480432 | |
104 | #define CONFIG_SYS_DDR_INTERVAL 0x030C0100 | |
105 | #define CONFIG_SYS_DDR_CONFIG_2 0x04400000 | |
106 | #define CONFIG_SYS_DDR_CONFIG 0xC3008000 | |
107 | #define CONFIG_SYS_DDR_CLK_CONTROL 0x03800000 | |
108 | #define CONFIG_SYS_SDRAM_SIZE 256 /* in Megs */ | |
5d108ac8 | 109 | |
5d108ac8 SP |
110 | /* |
111 | * Flash on the LocalBus | |
112 | */ | |
6d0f6bcf | 113 | #define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ |
5d108ac8 | 114 | |
6d0f6bcf JCPV |
115 | #define CONFIG_SYS_FLASH0 0xFE000000 |
116 | #define CONFIG_SYS_FLASH1 0xFC000000 | |
117 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 } | |
5d108ac8 | 118 | |
6d0f6bcf JCPV |
119 | #define CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_FLASH1 /* Localbus flash start */ |
120 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH */ | |
5d108ac8 | 121 | |
6d0f6bcf JCPV |
122 | #define CONFIG_SYS_BR0_PRELIM 0xfe001001 /* port size 16bit */ |
123 | #define CONFIG_SYS_OR0_PRELIM 0xfe000030 /* 32MB Flash */ | |
124 | #define CONFIG_SYS_BR1_PRELIM 0xfc001001 /* port size 16bit */ | |
125 | #define CONFIG_SYS_OR1_PRELIM 0xfe000030 /* 32MB Flash */ | |
5d108ac8 | 126 | |
6d0f6bcf | 127 | #define CONFIG_SYS_FLASH_CFI /* flash is CFI compat. */ |
00b1883a | 128 | #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/ |
5d108ac8 | 129 | |
6d0f6bcf JCPV |
130 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
131 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */ | |
132 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
133 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
134 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
5d108ac8 | 135 | |
14d0a02a | 136 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
5d108ac8 | 137 | |
6d0f6bcf JCPV |
138 | #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ |
139 | #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ | |
140 | #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ | |
141 | #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/ | |
5d108ac8 | 142 | |
6d0f6bcf JCPV |
143 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
144 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ | |
553f0982 | 145 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size used area in RAM*/ |
5d108ac8 | 146 | |
25ddd1fb | 147 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 148 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
5d108ac8 | 149 | |
47106ce1 | 150 | #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384KiB for Mon */ |
6d0f6bcf | 151 | #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc */ |
3e79b588 DZ |
152 | |
153 | /* FPGA and NAND */ | |
6d0f6bcf JCPV |
154 | #define CONFIG_SYS_FPGA_BASE 0xc0000000 |
155 | #define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */ | |
156 | #define CONFIG_SYS_HMI_BASE 0xc0010000 | |
157 | #define CONFIG_SYS_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */ | |
158 | #define CONFIG_SYS_OR3_PRELIM 0xfff00000 /* 1 MB */ | |
159 | ||
160 | #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70) | |
161 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
3e79b588 | 162 | #define CONFIG_CMD_NAND |
5d108ac8 | 163 | |
e64987a8 | 164 | /* LIME GDC */ |
6d0f6bcf JCPV |
165 | #define CONFIG_SYS_LIME_BASE 0xc8000000 |
166 | #define CONFIG_SYS_LIME_SIZE 0x04000000 /* 64 MB */ | |
167 | #define CONFIG_SYS_BR2_PRELIM 0xc80018a1 /* UPMB, 32-bit */ | |
168 | #define CONFIG_SYS_OR2_PRELIM 0xfc000000 /* 64 MB */ | |
e64987a8 | 169 | |
e64987a8 | 170 | #define CONFIG_VIDEO_MB862xx |
5d16ca87 | 171 | #define CONFIG_VIDEO_MB862xx_ACCEL |
e64987a8 AG |
172 | #define CONFIG_VIDEO_LOGO |
173 | #define CONFIG_VIDEO_BMP_LOGO | |
e64987a8 | 174 | #define VIDEO_FB_16BPP_PIXEL_SWAP |
229b6dce | 175 | #define VIDEO_FB_16BPP_WORD_SWAP |
e64987a8 AG |
176 | #define CONFIG_SPLASH_SCREEN |
177 | #define CONFIG_VIDEO_BMP_GZIP | |
6d0f6bcf | 178 | #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */ |
e64987a8 | 179 | |
c28d3bbe WG |
180 | /* SDRAM Clock frequency, 100MHz (0x0000) or 133MHz (0x10000) */ |
181 | #define CONFIG_SYS_MB862xx_CCF 0x10000 | |
182 | /* SDRAM parameter */ | |
183 | #define CONFIG_SYS_MB862xx_MMR 0x4157BA63 | |
184 | ||
5d108ac8 SP |
185 | /* Serial Port */ |
186 | ||
187 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
188 | #define CONFIG_SYS_NS16550_SERIAL |
189 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
190 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
5d108ac8 | 191 | |
6d0f6bcf JCPV |
192 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
193 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
5d108ac8 SP |
194 | |
195 | #define CONFIG_BAUDRATE 115200 | |
196 | ||
6d0f6bcf | 197 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
5d108ac8 SP |
198 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
199 | ||
200 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
5be58f5f | 201 | #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ |
5d108ac8 | 202 | |
5d108ac8 SP |
203 | /* |
204 | * I2C | |
205 | */ | |
00f792e0 HS |
206 | #define CONFIG_SYS_I2C |
207 | #define CONFIG_SYS_I2C_FSL | |
208 | #define CONFIG_SYS_FSL_I2C_SPEED 102124 | |
209 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
210 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
211 | #define CONFIG_SYS_FSL_I2C2_SPEED 102124 | |
212 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
213 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
3e79b588 | 214 | |
5d108ac8 | 215 | /* I2C RTC */ |
e18575d5 | 216 | #define CONFIG_RTC_RX8025 /* Use Epson rx8025 rtc via i2c */ |
6d0f6bcf | 217 | #define CONFIG_SYS_I2C_RTC_ADDR 0x32 /* at address 0x32 */ |
5d108ac8 | 218 | |
e64987a8 | 219 | /* I2C W83782G HW-Monitoring IC */ |
6d0f6bcf | 220 | #define CONFIG_SYS_I2C_W83782G_ADDR 0x28 /* W83782G address */ |
e64987a8 | 221 | |
2f7468ae SP |
222 | /* I2C temp sensor */ |
223 | /* Socrates uses Maxim's DS75, which is compatible with LM75 */ | |
224 | #define CONFIG_DTT_LM75 1 | |
225 | #define CONFIG_DTT_SENSORS {4} /* Sensor addresses */ | |
6d0f6bcf JCPV |
226 | #define CONFIG_SYS_DTT_MAX_TEMP 125 |
227 | #define CONFIG_SYS_DTT_LOW_TEMP -55 | |
228 | #define CONFIG_SYS_DTT_HYSTERESIS 3 | |
229 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 | |
2f7468ae | 230 | |
5d108ac8 SP |
231 | /* |
232 | * General PCI | |
233 | * Memory space is mapped 1-1. | |
234 | */ | |
6d0f6bcf | 235 | #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ |
5d108ac8 | 236 | |
5e1882df SP |
237 | /* PCI is clocked by the external source at 33 MHz */ |
238 | #define CONFIG_PCI_CLK_FREQ 33000000 | |
6d0f6bcf JCPV |
239 | #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 |
240 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE | |
241 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ | |
242 | #define CONFIG_SYS_PCI1_IO_BASE 0xE2000000 | |
243 | #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE | |
244 | #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ | |
5d108ac8 SP |
245 | |
246 | #if defined(CONFIG_PCI) | |
5d108ac8 | 247 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
d39e6851 | 248 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
5d108ac8 SP |
249 | #endif /* CONFIG_PCI */ |
250 | ||
5d108ac8 SP |
251 | #define CONFIG_MII 1 /* MII PHY management */ |
252 | #define CONFIG_TSEC1 1 | |
253 | #define CONFIG_TSEC1_NAME "TSEC0" | |
2f845dc2 SP |
254 | #define CONFIG_TSEC3 1 |
255 | #define CONFIG_TSEC3_NAME "TSEC1" | |
5d108ac8 SP |
256 | #undef CONFIG_MPC85XX_FEC |
257 | ||
258 | #define TSEC1_PHY_ADDR 0 | |
2f845dc2 | 259 | #define TSEC3_PHY_ADDR 1 |
5d108ac8 SP |
260 | |
261 | #define TSEC1_PHYIDX 0 | |
2f845dc2 | 262 | #define TSEC3_PHYIDX 0 |
5d108ac8 | 263 | #define TSEC1_FLAGS TSEC_GIGABIT |
2f845dc2 | 264 | #define TSEC3_FLAGS TSEC_GIGABIT |
5d108ac8 | 265 | |
2f845dc2 | 266 | /* Options are: TSEC[0,1] */ |
5d108ac8 SP |
267 | #define CONFIG_ETHPRIME "TSEC0" |
268 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
269 | ||
e18575d5 SP |
270 | #define CONFIG_HAS_ETH0 |
271 | #define CONFIG_HAS_ETH1 | |
272 | ||
5d108ac8 SP |
273 | /* |
274 | * Environment | |
275 | */ | |
5a1aceb0 | 276 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 | 277 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ |
6d0f6bcf | 278 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
0e8d1586 JCPV |
279 | #define CONFIG_ENV_SIZE 0x4000 |
280 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) | |
281 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
5d108ac8 SP |
282 | |
283 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 284 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
5d108ac8 SP |
285 | |
286 | #define CONFIG_TIMESTAMP /* Print image info with ts */ | |
287 | ||
5d108ac8 SP |
288 | /* |
289 | * BOOTP options | |
290 | */ | |
291 | #define CONFIG_BOOTP_BOOTFILESIZE | |
292 | #define CONFIG_BOOTP_BOOTPATH | |
293 | #define CONFIG_BOOTP_GATEWAY | |
294 | #define CONFIG_BOOTP_HOSTNAME | |
295 | ||
5d108ac8 SP |
296 | /* |
297 | * Command line configuration. | |
298 | */ | |
47106ce1 | 299 | #define CONFIG_CMD_BMP |
5d108ac8 | 300 | #define CONFIG_CMD_DATE |
2f7468ae | 301 | #define CONFIG_CMD_DTT |
5d108ac8 | 302 | #undef CONFIG_CMD_EEPROM |
3e79b588 | 303 | #define CONFIG_CMD_SDRAM |
199e262e | 304 | #define CONFIG_CMD_REGINFO |
5d108ac8 SP |
305 | |
306 | #if defined(CONFIG_PCI) | |
307 | #define CONFIG_CMD_PCI | |
308 | #endif | |
309 | ||
5d108ac8 SP |
310 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
311 | ||
312 | /* | |
313 | * Miscellaneous configurable options | |
314 | */ | |
6d0f6bcf JCPV |
315 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
316 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
5d108ac8 SP |
317 | |
318 | #if defined(CONFIG_CMD_KGDB) | |
6d0f6bcf | 319 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
5d108ac8 | 320 | #else |
6d0f6bcf | 321 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
5d108ac8 SP |
322 | #endif |
323 | ||
6d0f6bcf JCPV |
324 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buf Size */ |
325 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
326 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
5d108ac8 SP |
327 | |
328 | /* | |
329 | * For booting Linux, the board info and command line data | |
330 | * have to be in the first 8 MB of memory, since this is | |
331 | * the maximum mapped by the Linux kernel during initialization. | |
332 | */ | |
6d0f6bcf | 333 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
5d108ac8 | 334 | |
5d108ac8 SP |
335 | #if defined(CONFIG_CMD_KGDB) |
336 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/ | |
5d108ac8 SP |
337 | #endif |
338 | ||
5d108ac8 SP |
339 | #define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/ |
340 | ||
5d108ac8 SP |
341 | |
342 | #define CONFIG_PREBOOT "echo;" \ | |
3e79b588 | 343 | "echo Welcome on the ABB Socrates Board;" \ |
5d108ac8 SP |
344 | "echo" |
345 | ||
346 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ | |
347 | ||
348 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
5d108ac8 SP |
349 | "netdev=eth0\0" \ |
350 | "consdev=ttyS0\0" \ | |
3e79b588 DZ |
351 | "uboot_file=/home/tftp/syscon3/u-boot.bin\0" \ |
352 | "bootfile=/home/tftp/syscon3/uImage\0" \ | |
353 | "fdt_file=/home/tftp/syscon3/socrates.dtb\0" \ | |
354 | "initrd_file=/home/tftp/syscon3/uinitrd.gz\0" \ | |
355 | "uboot_addr=FFFA0000\0" \ | |
356 | "kernel_addr=FE000000\0" \ | |
357 | "fdt_addr=FE1E0000\0" \ | |
358 | "ramdisk_addr=FE200000\0" \ | |
359 | "fdt_addr_r=B00000\0" \ | |
360 | "kernel_addr_r=200000\0" \ | |
361 | "ramdisk_addr_r=400000\0" \ | |
362 | "rootpath=/opt/eldk/ppc_85xxDP\0" \ | |
363 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
5d108ac8 SP |
364 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
365 | "nfsroot=$serverip:$rootpath\0" \ | |
3e79b588 DZ |
366 | "addcons=setenv bootargs $bootargs " \ |
367 | "console=$consdev,$baudrate\0" \ | |
5d108ac8 SP |
368 | "addip=setenv bootargs $bootargs " \ |
369 | "ip=$ipaddr:$serverip:$gatewayip:$netmask" \ | |
370 | ":$hostname:$netdev:off panic=1\0" \ | |
3e79b588 | 371 | "boot_nor=run ramargs addcons;" \ |
e18575d5 | 372 | "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ |
e18575d5 SP |
373 | "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ |
374 | "tftp ${fdt_addr_r} ${fdt_file}; " \ | |
375 | "run nfsargs addip addcons;" \ | |
376 | "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ | |
3e79b588 DZ |
377 | "update_uboot=tftp 100000 ${uboot_file};" \ |
378 | "protect off fffa0000 ffffffff;" \ | |
379 | "era fffa0000 ffffffff;" \ | |
380 | "cp.b 100000 fffa0000 ${filesize};" \ | |
381 | "setenv filesize;saveenv\0" \ | |
382 | "update_kernel=tftp 100000 ${bootfile};" \ | |
383 | "era fe000000 fe1dffff;" \ | |
384 | "cp.b 100000 fe000000 ${filesize};" \ | |
5d108ac8 | 385 | "setenv filesize;saveenv\0" \ |
3e79b588 DZ |
386 | "update_fdt=tftp 100000 ${fdt_file};" \ |
387 | "era fe1e0000 fe1fffff;" \ | |
388 | "cp.b 100000 fe1e0000 ${filesize};" \ | |
389 | "setenv filesize;saveenv\0" \ | |
390 | "update_initrd=tftp 100000 ${initrd_file};" \ | |
391 | "era fe200000 fe9fffff;" \ | |
392 | "cp.b 100000 fe200000 ${filesize};" \ | |
393 | "setenv filesize;saveenv\0" \ | |
394 | "clean_data=era fea00000 fff5ffff\0" \ | |
395 | "usbargs=setenv bootargs root=/dev/sda1 rw\0" \ | |
396 | "load_usb=usb start;" \ | |
397 | "ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0" \ | |
398 | "boot_usb=run load_usb usbargs addcons;" \ | |
399 | "bootm ${kernel_addr_r} - ${fdt_addr};" \ | |
400 | "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ | |
5d108ac8 | 401 | "" |
3e79b588 | 402 | #define CONFIG_BOOTCOMMAND "run boot_nor" |
5d108ac8 | 403 | |
e18575d5 | 404 | /* pass open firmware flat tree */ |
e18575d5 | 405 | |
791e1dba SP |
406 | /* USB support */ |
407 | #define CONFIG_USB_OHCI_NEW 1 | |
408 | #define CONFIG_PCI_OHCI 1 | |
409 | #define CONFIG_PCI_OHCI_DEVNO 3 /* Number in PCI list */ | |
e90fb6af | 410 | #define CONFIG_PCI_EHCI_DEVNO (CONFIG_PCI_OHCI_DEVNO / 2) |
6d0f6bcf JCPV |
411 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 |
412 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" | |
413 | #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 | |
791e1dba | 414 | #define CONFIG_DOS_PARTITION 1 |
791e1dba | 415 | |
5d108ac8 | 416 | #endif /* __CONFIG_H */ |