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f9c6fac4 SB |
1 | /* |
2 | * Copyright (C) 2011 | |
3 | * Stefano Babic, DENX Software Engineering, sbabic@denx.de. | |
4 | * | |
5 | * Copyright (C) 2009 TechNexion Ltd. | |
6 | * | |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
f9c6fac4 SB |
8 | */ |
9 | ||
10 | #ifndef __TAM3517_H | |
11 | #define __TAM3517_H | |
12 | ||
13 | /* | |
14 | * High Level Configuration Options | |
15 | */ | |
16 | #define CONFIG_OMAP /* in a TI OMAP core */ | |
308252ad | 17 | #define CONFIG_OMAP_GPIO |
c6f90e14 NM |
18 | /* Common ARM Erratas */ |
19 | #define CONFIG_ARM_ERRATA_454179 | |
20 | #define CONFIG_ARM_ERRATA_430973 | |
21 | #define CONFIG_ARM_ERRATA_621766 | |
f9c6fac4 SB |
22 | |
23 | #define CONFIG_SYS_TEXT_BASE 0x80008000 | |
24 | ||
f9c6fac4 SB |
25 | #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ |
26 | ||
27 | #include <asm/arch/cpu.h> /* get chip and board defs */ | |
987ec585 | 28 | #include <asm/arch/omap.h> |
f9c6fac4 | 29 | |
f9c6fac4 SB |
30 | /* Clock Defines */ |
31 | #define V_OSCK 26000000 /* Clock output from T2 */ | |
32 | #define V_SCLK (V_OSCK >> 1) | |
33 | ||
f9c6fac4 SB |
34 | #define CONFIG_MISC_INIT_R |
35 | ||
36 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ | |
37 | #define CONFIG_SETUP_MEMORY_TAGS | |
38 | #define CONFIG_INITRD_TAG | |
39 | #define CONFIG_REVISION_TAG | |
40 | ||
41 | /* | |
42 | * Size of malloc() pool | |
43 | */ | |
44 | #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ | |
45 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10) + \ | |
46 | 2 * 1024 * 1024) | |
47 | /* | |
48 | * DDR related | |
49 | */ | |
50 | #define CONFIG_OMAP3_MICRON_DDR /* Micron DDR */ | |
51 | #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) | |
52 | ||
53 | /* | |
54 | * Hardware drivers | |
55 | */ | |
56 | ||
57 | /* | |
58 | * NS16550 Configuration | |
59 | */ | |
f9c6fac4 SB |
60 | #define CONFIG_SYS_NS16550_SERIAL |
61 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) | |
62 | #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ | |
63 | ||
64 | /* | |
65 | * select serial console configuration | |
66 | */ | |
67 | #define CONFIG_CONS_INDEX 1 | |
68 | #define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 | |
69 | #define CONFIG_SERIAL1 /* UART1 */ | |
70 | ||
71 | /* allow to overwrite serial and ethaddr */ | |
72 | #define CONFIG_ENV_OVERWRITE | |
73 | #define CONFIG_BAUDRATE 115200 | |
74 | #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ | |
75 | 115200} | |
f9c6fac4 SB |
76 | #define CONFIG_GENERIC_MMC |
77 | #define CONFIG_DOS_PARTITION | |
78 | ||
79 | /* EHCI */ | |
80 | #define CONFIG_OMAP3_GPIO_5 | |
81 | #define CONFIG_USB_EHCI | |
82 | #define CONFIG_USB_EHCI_OMAP | |
83 | #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25 | |
84 | #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 | |
f9c6fac4 | 85 | |
f9c6fac4 | 86 | /* commands to include */ |
f9c6fac4 | 87 | #define CONFIG_CMD_NAND /* NAND support */ |
8103c6f0 | 88 | #define CONFIG_CMD_EEPROM |
f9c6fac4 | 89 | |
f9c6fac4 | 90 | #define CONFIG_SYS_NO_FLASH |
6789e84e HS |
91 | #define CONFIG_SYS_I2C |
92 | #define CONFIG_SYS_OMAP24_I2C_SPEED 400000 | |
93 | #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 | |
94 | #define CONFIG_SYS_I2C_OMAP34XX | |
8103c6f0 SB |
95 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */ |
96 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ | |
97 | #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 | |
f9c6fac4 SB |
98 | |
99 | /* | |
100 | * Board NAND Info. | |
101 | */ | |
102 | #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ | |
103 | /* to access */ | |
104 | /* nand at CS0 */ | |
105 | ||
106 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ | |
107 | /* NAND devices */ | |
f9c6fac4 SB |
108 | |
109 | #define CONFIG_AUTO_COMPLETE | |
110 | ||
111 | /* | |
112 | * Miscellaneous configurable options | |
113 | */ | |
114 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
f9c6fac4 SB |
115 | #define CONFIG_CMDLINE_EDITING |
116 | #define CONFIG_AUTO_COMPLETE | |
117 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ | |
118 | ||
119 | /* Print Buffer Size */ | |
120 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
121 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
122 | #define CONFIG_SYS_MAXARGS 32 /* max number of command */ | |
123 | /* args */ | |
124 | /* Boot Argument Buffer Size */ | |
125 | #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) | |
126 | /* memtest works on */ | |
127 | #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) | |
128 | #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ | |
129 | 0x01F00000) /* 31MB */ | |
130 | ||
131 | #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ | |
132 | /* address */ | |
133 | ||
134 | /* | |
135 | * AM3517 has 12 GP timers, they can be driven by the system clock | |
136 | * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). | |
137 | * This rate is divided by a local divisor. | |
138 | */ | |
139 | #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 | |
140 | #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ | |
f9c6fac4 | 141 | |
f9c6fac4 SB |
142 | /* |
143 | * Physical Memory Map | |
144 | */ | |
145 | #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ | |
146 | #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 | |
f9c6fac4 SB |
147 | #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 |
148 | ||
149 | /* | |
150 | * FLASH and environment organization | |
151 | */ | |
152 | ||
153 | /* **** PISMO SUPPORT *** */ | |
0970051d | 154 | #define CONFIG_NAND |
f9c6fac4 | 155 | #define CONFIG_NAND_OMAP_GPMC |
f9c6fac4 SB |
156 | #define CONFIG_ENV_IS_IN_NAND |
157 | #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */ | |
158 | ||
159 | /* Redundant Environment */ | |
160 | #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ | |
161 | #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET | |
162 | #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET | |
163 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ | |
164 | 2 * CONFIG_SYS_ENV_SECT_SIZE) | |
165 | #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE | |
166 | ||
167 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 | |
168 | #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 | |
169 | #define CONFIG_SYS_INIT_RAM_SIZE 0x800 | |
170 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ | |
171 | CONFIG_SYS_INIT_RAM_SIZE - \ | |
172 | GENERATED_GBL_DATA_SIZE) | |
173 | ||
174 | /* | |
175 | * ethernet support, EMAC | |
176 | * | |
177 | */ | |
178 | #define CONFIG_DRIVER_TI_EMAC | |
179 | #define CONFIG_DRIVER_TI_EMAC_USE_RMII | |
180 | #define CONFIG_MII | |
181 | #define CONFIG_EMAC_MDIO_PHY_NUM 0 | |
f9c6fac4 SB |
182 | #define CONFIG_BOOTP_DNS |
183 | #define CONFIG_BOOTP_DNS2 | |
184 | #define CONFIG_BOOTP_SEND_HOSTNAME | |
185 | #define CONFIG_NET_RETRY_COUNT 10 | |
f9c6fac4 SB |
186 | |
187 | /* Defines for SPL */ | |
47f7bcae | 188 | #define CONFIG_SPL_FRAMEWORK |
d7cb93b2 | 189 | #define CONFIG_SPL_BOARD_INIT |
f9c6fac4 SB |
190 | #define CONFIG_SPL_CONSOLE |
191 | #define CONFIG_SPL_NAND_SIMPLE | |
8ad59c9a | 192 | #define CONFIG_SPL_NAND_SOFTECC |
f9c6fac4 SB |
193 | #define CONFIG_SPL_NAND_WORKSPACE 0x8f07f000 /* below BSS */ |
194 | ||
6f2f01b9 SW |
195 | #define CONFIG_SPL_NAND_BASE |
196 | #define CONFIG_SPL_NAND_DRIVERS | |
197 | #define CONFIG_SPL_NAND_ECC | |
983e3700 | 198 | #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" |
f9c6fac4 SB |
199 | |
200 | #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ | |
fa2f81b0 TR |
201 | #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ |
202 | CONFIG_SPL_TEXT_BASE) | |
f51c8a99 | 203 | #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK |
f9c6fac4 SB |
204 | |
205 | #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 | |
206 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 | |
207 | #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ | |
208 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 | |
209 | ||
f51c8a99 SB |
210 | #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 |
211 | #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" | |
212 | ||
213 | /* FAT */ | |
214 | #define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" | |
215 | #define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" | |
216 | ||
217 | /* RAW SD card / eMMC */ | |
218 | #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */ | |
219 | #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */ | |
220 | #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */ | |
221 | ||
f9c6fac4 | 222 | /* NAND boot config */ |
55f1b39f | 223 | #define CONFIG_SYS_NAND_BUSWIDTH_16BIT |
f9c6fac4 SB |
224 | #define CONFIG_SYS_NAND_PAGE_COUNT 64 |
225 | #define CONFIG_SYS_NAND_PAGE_SIZE 2048 | |
226 | #define CONFIG_SYS_NAND_OOBSIZE 64 | |
227 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
228 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE | |
229 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 | |
230 | #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ | |
231 | 48, 49, 50, 51, 52, 53, 54, 55,\ | |
232 | 56, 57, 58, 59, 60, 61, 62, 63} | |
233 | #define CONFIG_SYS_NAND_ECCSIZE 256 | |
234 | #define CONFIG_SYS_NAND_ECCBYTES 3 | |
3f719069 | 235 | #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW |
817aa32b | 236 | #define CONFIG_NAND_OMAP_GPMC_PREFETCH |
f9c6fac4 | 237 | |
f9c6fac4 SB |
238 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE |
239 | ||
240 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 | |
241 | #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 | |
242 | ||
f9c6fac4 SB |
243 | #define CONFIG_CMD_UBIFS |
244 | #define CONFIG_RBTREE | |
245 | #define CONFIG_LZO | |
246 | #define CONFIG_MTD_PARTITIONS | |
247 | #define CONFIG_MTD_DEVICE | |
248 | #define CONFIG_CMD_MTDPARTS | |
249 | ||
250 | /* Setup MTD for NAND on the SOM */ | |
251 | #define MTDIDS_DEFAULT "nand0=omap2-nand.0" | |
252 | #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \ | |
1fdabedd SB |
253 | "1m(u-boot),256k(env1)," \ |
254 | "256k(env2),6m(kernel),-(rootfs)" | |
f9c6fac4 | 255 | |
f9c6fac4 SB |
256 | #define CONFIG_TAM3517_SETTINGS \ |
257 | "netdev=eth0\0" \ | |
258 | "nandargs=setenv bootargs root=${nandroot} " \ | |
259 | "rootfstype=${nandrootfstype}\0" \ | |
260 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
261 | "nfsroot=${serverip}:${rootpath}\0" \ | |
262 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
263 | "addip_sta=setenv bootargs ${bootargs} " \ | |
264 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
265 | ":${hostname}:${netdev}:off panic=1\0" \ | |
266 | "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ | |
267 | "addip=if test -n ${ipdyn};then run addip_dyn;" \ | |
268 | "else run addip_sta;fi\0" \ | |
269 | "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ | |
270 | "addtty=setenv bootargs ${bootargs}" \ | |
271 | " console=ttyO0,${baudrate}\0" \ | |
272 | "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ | |
273 | "loadaddr=82000000\0" \ | |
274 | "kernel_addr_r=82000000\0" \ | |
93ea89f0 MV |
275 | "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \ |
276 | "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \ | |
f9c6fac4 SB |
277 | "flash_self=run ramargs addip addtty addmtd addmisc;" \ |
278 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ | |
279 | "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ | |
280 | "bootm ${kernel_addr}\0" \ | |
281 | "nandboot=run nandargs addip addtty addmtd addmisc;" \ | |
282 | "nand read ${kernel_addr_r} kernel\0" \ | |
283 | "bootm ${kernel_addr_r}\0" \ | |
284 | "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ | |
285 | "run nfsargs addip addtty addmtd addmisc;" \ | |
286 | "bootm ${kernel_addr_r}\0" \ | |
287 | "net_self=if run net_self_load;then " \ | |
288 | "run ramargs addip addtty addmtd addmisc;" \ | |
289 | "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \ | |
290 | "else echo Images not loades;fi\0" \ | |
93ea89f0 | 291 | "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \ |
f9c6fac4 SB |
292 | "load=tftp ${loadaddr} ${u-boot}\0" \ |
293 | "loadmlo=tftp ${loadaddr} ${mlo}\0" \ | |
93ea89f0 | 294 | "mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \ |
f9c6fac4 SB |
295 | "uboot_addr=0x80000\0" \ |
296 | "update=nandecc sw;nand erase ${uboot_addr} 100000;" \ | |
297 | "nand write ${loadaddr} ${uboot_addr} 80000\0" \ | |
298 | "updatemlo=nandecc hw;nand erase 0 20000;" \ | |
299 | "nand write ${loadaddr} 0 20000\0" \ | |
300 | "upd=if run load;then echo Updating u-boot;if run update;" \ | |
301 | "then echo U-Boot updated;" \ | |
302 | "else echo Error updating u-boot !;" \ | |
303 | "echo Board without bootloader !!;" \ | |
304 | "fi;" \ | |
305 | "else echo U-Boot not downloaded..exiting;fi\0" \ | |
306 | ||
8103c6f0 SB |
307 | /* |
308 | * this is common code for all TAM3517 boards. | |
309 | * MAC address is stored from manufacturer in | |
310 | * I2C EEPROM | |
311 | */ | |
312 | #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) | |
8103c6f0 SB |
313 | /* |
314 | * The I2C EEPROM on the TAM3517 contains | |
315 | * mac address and production data | |
316 | */ | |
317 | struct tam3517_module_info { | |
318 | char customer[48]; | |
319 | char product[48]; | |
320 | ||
321 | /* | |
322 | * bit 0~47 : sequence number | |
323 | * bit 48~55 : week of year, from 0. | |
324 | * bit 56~63 : year | |
325 | */ | |
326 | unsigned long long sequence_number; | |
327 | ||
328 | /* | |
329 | * bit 0~7 : revision fixed | |
330 | * bit 8~15 : revision major | |
331 | * bit 16~31 : TNxxx | |
332 | */ | |
333 | unsigned int revision; | |
334 | unsigned char eth_addr[4][8]; | |
335 | unsigned char _rev[100]; | |
336 | }; | |
337 | ||
31f5b651 SB |
338 | #define TAM3517_READ_EEPROM(info, ret) \ |
339 | do { \ | |
6789e84e | 340 | i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \ |
8103c6f0 | 341 | if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, \ |
31f5b651 SB |
342 | (void *)info, sizeof(*info))) \ |
343 | ret = 1; \ | |
344 | else \ | |
345 | ret = 0; \ | |
346 | } while (0) | |
347 | ||
348 | #define TAM3517_READ_MAC_FROM_EEPROM(info) \ | |
349 | do { \ | |
350 | char buf[80], ethname[20]; \ | |
351 | int i; \ | |
8103c6f0 | 352 | memset(buf, 0, sizeof(buf)); \ |
31f5b651 | 353 | for (i = 0 ; i < ARRAY_SIZE((info)->eth_addr); i++) { \ |
8103c6f0 | 354 | sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X", \ |
31f5b651 SB |
355 | (info)->eth_addr[i][5], \ |
356 | (info)->eth_addr[i][4], \ | |
357 | (info)->eth_addr[i][3], \ | |
358 | (info)->eth_addr[i][2], \ | |
359 | (info)->eth_addr[i][1], \ | |
360 | (info)->eth_addr[i][0]); \ | |
8103c6f0 SB |
361 | \ |
362 | if (i) \ | |
363 | sprintf(ethname, "eth%daddr", i); \ | |
364 | else \ | |
192bc694 | 365 | strcpy(ethname, "ethaddr"); \ |
8103c6f0 SB |
366 | printf("Setting %s from EEPROM with %s\n", ethname, buf);\ |
367 | setenv(ethname, buf); \ | |
368 | } \ | |
369 | } while (0) | |
31f5b651 SB |
370 | |
371 | /* The following macros are taken from Technexion's documentation */ | |
372 | #define TAM3517_sequence_number(info) \ | |
373 | ((info)->sequence_number % 0x1000000000000LL) | |
374 | #define TAM3517_week_of_year(info) (((info)->sequence_number >> 48) % 0x100) | |
375 | #define TAM3517_year(info) ((info)->sequence_number >> 56) | |
376 | #define TAM3517_revision_fixed(info) ((info)->revision % 0x100) | |
377 | #define TAM3517_revision_major(info) (((info)->revision >> 8) % 0x100) | |
378 | #define TAM3517_revision_tn(info) ((info)->revision >> 16) | |
379 | ||
380 | #define TAM3517_PRINT_SOM_INFO(info) \ | |
381 | do { \ | |
382 | printf("Vendor:%s\n", (info)->customer); \ | |
383 | printf("SOM: %s\n", (info)->product); \ | |
384 | printf("SeqNr: %02llu%02llu%012llu\n", \ | |
385 | TAM3517_year(info), \ | |
386 | TAM3517_week_of_year(info), \ | |
387 | TAM3517_sequence_number(info)); \ | |
388 | printf("Rev: TN%u %u.%u\n", \ | |
389 | TAM3517_revision_tn(info), \ | |
390 | TAM3517_revision_major(info), \ | |
391 | TAM3517_revision_fixed(info)); \ | |
392 | } while (0) | |
393 | ||
8103c6f0 SB |
394 | #endif |
395 | ||
f9c6fac4 | 396 | #endif /* __TAM3517_H */ |