[people/ms/u-boot.git] / include / configs / tam3517-common.h

/*
 * Copyright (C) 2011
 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
 *
 * Copyright (C) 2009 TechNexion Ltd.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __TAM3517_H
#define __TAM3517_H

/*
 * High Level Configuration Options
 */

#include <asm/arch/cpu.h>		/* get chip and board defs */
#include <asm/arch/omap.h>

/* Clock Defines */
#define V_OSCK			26000000	/* Clock output from T2 */
#define V_SCLK			(V_OSCK >> 1)

#define CONFIG_MISC_INIT_R

#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG

/*
 * Size of malloc() pool
 */
#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB sector */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10) + \
					2 * 1024 * 1024)
/*
 * DDR related
 */
#define CONFIG_SYS_CS0_SIZE		(256 * 1024 * 1024)

/*
 * Hardware drivers
 */

/*
 * NS16550 Configuration
 */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		48000000	/* 48MHz (APLL96/2) */

/*
 * select serial console configuration
 */
#define CONFIG_CONS_INDEX		1
#define CONFIG_SYS_NS16550_COM1		OMAP34XX_UART1
#define CONFIG_SERIAL1			/* UART1 */

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
					115200}
/* EHCI */
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO	25

#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50		/* base address */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1		/* bytes of address */
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07

/*
 * Board NAND Info.
 */
#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
							/* to access */
							/* nand at CS0 */

#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
							/* NAND devices */

#define CONFIG_AUTO_COMPLETE

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_CMDLINE_EDITING
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */

#define CONFIG_SYS_MAXARGS		32	/* max number of command */
						/* args */
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
					0x01F00000) /* 31MB */

#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
								/* address */

/*
 * AM3517 has 12 GP timers, they can be driven by the system clock
 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 * This rate is divided by a local divisor.
 */
#define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */

/*
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1

/*
 * FLASH and environment organization
 */

/* **** PISMO SUPPORT *** */

/* Redundant Environment */
#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
#define CONFIG_ENV_OFFSET		0x180000
#define CONFIG_ENV_ADDR			0x180000
#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
						2 * CONFIG_SYS_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE	0x800
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - \
					 GENERATED_GBL_DATA_SIZE)

/*
 * ethernet support, EMAC
 *
 */
#define CONFIG_DRIVER_TI_EMAC
#define CONFIG_DRIVER_TI_EMAC_USE_RMII
#define CONFIG_MII
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 10

/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_CONSOLE
#define CONFIG_SPL_NAND_SOFTECC
#define CONFIG_SPL_NAND_WORKSPACE	0x8f07f000 /* below BSS */

#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC

#define CONFIG_SPL_TEXT_BASE		0x40200000 /*CONFIG_SYS_SRAM_START*/
#define CONFIG_SPL_MAX_SIZE		(SRAM_SCRATCH_SPACE_ADDR - \
					 CONFIG_SPL_TEXT_BASE)
#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK

#define CONFIG_SYS_SPL_MALLOC_START	0x8f000000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
#define CONFIG_SPL_BSS_START_ADDR	0x8f080000 /* end of RAM */
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000

#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot.img"

/* FAT */
#define CONFIG_SPL_FS_LOAD_KERNEL_NAME		"uImage"
#define CONFIG_SPL_FS_LOAD_ARGS_NAME		"args"

/* RAW SD card / eMMC */
#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0x900	/* address 0x120000 */
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0x80	/* address 0x10000 */
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	0x80	/* 64KiB */

/* NAND boot config */
#define CONFIG_SYS_NAND_PAGE_COUNT	64
#define CONFIG_SYS_NAND_PAGE_SIZE	2048
#define CONFIG_SYS_NAND_OOBSIZE		64
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
#define CONFIG_SYS_NAND_ECCPOS		{40, 41, 42, 43, 44, 45, 46, 47,\
					 48, 49, 50, 51, 52, 53, 54, 55,\
					 56, 57, 58, 59, 60, 61, 62, 63}
#define CONFIG_SYS_NAND_ECCSIZE		256
#define CONFIG_SYS_NAND_ECCBYTES	3
#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_SW

#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE

#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x80000

#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE

/* Setup MTD for NAND on the SOM */

#define	CONFIG_TAM3517_SETTINGS						\
	"netdev=eth0\0"							\
	"nandargs=setenv bootargs root=${nandroot} "			\
		"rootfstype=${nandrootfstype}\0"			\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip_sta=setenv bootargs ${bootargs} "			\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0"		\
	"addip=if test -n ${ipdyn};then run addip_dyn;"			\
		"else run addip_sta;fi\0"				\
	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
	"addtty=setenv bootargs ${bootargs}"				\
		" console=ttyO0,${baudrate}\0"				\
	"addmisc=setenv bootargs ${bootargs} ${misc}\0"			\
	"loadaddr=82000000\0"						\
	"kernel_addr_r=82000000\0"					\
	"hostname=" __stringify(CONFIG_HOSTNAME) "\0"			\
	"bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0"		\
	"flash_self=run ramargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"flash_nfs=run nfsargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr}\0"				\
	"nandboot=run nandargs addip addtty addmtd addmisc;"		\
		"nand read ${kernel_addr_r} kernel\0"			\
		"bootm ${kernel_addr_r}\0"				\
	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
		"run nfsargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr_r}\0"				\
	"net_self=if run net_self_load;then "				\
		"run ramargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr_r} ${ramdisk_addr_r};"		\
		"else echo Images not loades;fi\0"			\
	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0"		\
	"load=tftp ${loadaddr} ${u-boot}\0"				\
	"loadmlo=tftp ${loadaddr} ${mlo}\0"				\
	"mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0"			\
	"uboot_addr=0x80000\0"						\
	"update=nandecc sw;nand erase ${uboot_addr} 100000;"		\
		"nand write ${loadaddr} ${uboot_addr} 80000\0"		\
	"updatemlo=nandecc hw;nand erase 0 20000;"			\
		"nand write ${loadaddr} 0 20000\0"			\
	"upd=if run load;then echo Updating u-boot;if run update;"	\
		"then echo U-Boot updated;"				\
			"else echo Error updating u-boot !;"		\
			"echo Board without bootloader !!;"		\
		"fi;"							\
		"else echo U-Boot not downloaded..exiting;fi\0"		\

/*
 * this is common code for all TAM3517 boards.
 * MAC address is stored from manufacturer in
 * I2C EEPROM
 */
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
/*
 * The I2C EEPROM on the TAM3517 contains
 * mac address and production data
 */
struct tam3517_module_info {
	char customer[48];
	char product[48];

	/*
	 * bit 0~47  : sequence number
	 * bit 48~55 : week of year, from 0.
	 * bit 56~63 : year
	 */
	unsigned long long sequence_number;

	/*
	 * bit 0~7   : revision fixed
	 * bit 8~15  : revision major
	 * bit 16~31 : TNxxx
	 */
	unsigned int revision;
	unsigned char eth_addr[4][8];
	unsigned char _rev[100];
};

#define TAM3517_READ_EEPROM(info, ret) \
do {								\
	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \
	if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,		\
		(void *)info, sizeof(*info)))			\
		ret = 1;					\
	else							\
		ret = 0;					\
} while (0)

#define TAM3517_READ_MAC_FROM_EEPROM(info)			\
do {								\
	char buf[80], ethname[20];				\
	int i;							\
	memset(buf, 0, sizeof(buf));				\
	for (i = 0 ; i < ARRAY_SIZE((info)->eth_addr); i++) {	\
		sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X",	\
			(info)->eth_addr[i][5],			\
			(info)->eth_addr[i][4],			\
			(info)->eth_addr[i][3],			\
			(info)->eth_addr[i][2],			\
			(info)->eth_addr[i][1],			\
			(info)->eth_addr[i][0]);			\
								\
		if (i)						\
			sprintf(ethname, "eth%daddr", i);	\
		else						\
			strcpy(ethname, "ethaddr");		\
		printf("Setting %s from EEPROM with %s\n", ethname, buf);\
		env_set(ethname, buf);				\
	}							\
} while (0)

/* The following macros are taken from Technexion's documentation */
#define TAM3517_sequence_number(info) \
	((info)->sequence_number % 0x1000000000000LL)
#define TAM3517_week_of_year(info) (((info)->sequence_number >> 48) % 0x100)
#define TAM3517_year(info) ((info)->sequence_number >> 56)
#define TAM3517_revision_fixed(info) ((info)->revision % 0x100)
#define TAM3517_revision_major(info) (((info)->revision >> 8) % 0x100)
#define TAM3517_revision_tn(info) ((info)->revision >> 16)

#define TAM3517_PRINT_SOM_INFO(info)				\
do {								\
	printf("Vendor:%s\n", (info)->customer);		\
	printf("SOM:   %s\n", (info)->product);			\
	printf("SeqNr: %02llu%02llu%012llu\n",			\
		TAM3517_year(info),				\
		TAM3517_week_of_year(info),			\
		TAM3517_sequence_number(info));			\
	printf("Rev:   TN%u %u.%u\n",				\
		TAM3517_revision_tn(info),			\
		TAM3517_revision_major(info),			\
		TAM3517_revision_fixed(info));			\
} while (0)

#endif

#endif /* __TAM3517_H */
Commit	Line	Data
f9c6fac4 SB	1	/*
	2	* Copyright (C) 2011
	3	* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
	4	*
	5	* Copyright (C) 2009 TechNexion Ltd.
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
f9c6fac4 SB	8	*/
	9
	10	#ifndef __TAM3517_H
	11	#define __TAM3517_H
	12
	13	/*
	14	* High Level Configuration Options
	15	*/
f9c6fac4	16
f9c6fac4	17	#include <asm/arch/cpu.h> /* get chip and board defs */
987ec585	18	#include <asm/arch/omap.h>
f9c6fac4	19
f9c6fac4 SB	20	/* Clock Defines */
	21	#define V_OSCK 26000000 /* Clock output from T2 */
	22	#define V_SCLK (V_OSCK >> 1)
	23
f9c6fac4 SB	24	#define CONFIG_MISC_INIT_R
	25
	26	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	27	#define CONFIG_SETUP_MEMORY_TAGS
	28	#define CONFIG_INITRD_TAG
	29	#define CONFIG_REVISION_TAG
	30
	31	/*
	32	* Size of malloc() pool
	33	*/
	34	#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
	35	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10) + \
	36	2 * 1024 * 1024)
	37	/*
	38	* DDR related
	39	*/
f9c6fac4 SB	40	#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
	41
	42	/*
	43	* Hardware drivers
	44	*/
	45
	46	/*
	47	* NS16550 Configuration
	48	*/
f9c6fac4 SB	49	#define CONFIG_SYS_NS16550_SERIAL
	50	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	51	#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
	52
	53	/*
	54	* select serial console configuration
	55	*/
	56	#define CONFIG_CONS_INDEX 1
	57	#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
	58	#define CONFIG_SERIAL1 /* UART1 */
	59
	60	/* allow to overwrite serial and ethaddr */
	61	#define CONFIG_ENV_OVERWRITE
f9c6fac4 SB	62	#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
f9c6fac4 SB	63	115200}
f9c6fac4	64	/* EHCI */
f9c6fac4	65	#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25
f9c6fac4	66
6789e84e	67	#define CONFIG_SYS_I2C
8103c6f0 SB	68	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */
	69	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
	70	#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
f9c6fac4 SB	71
	72	/*
	73	* Board NAND Info.
	74	*/
	75	#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
	76	/* to access */
	77	/* nand at CS0 */
	78
	79	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
	80	/* NAND devices */
f9c6fac4 SB	81
	82	#define CONFIG_AUTO_COMPLETE
	83
	84	/*
	85	* Miscellaneous configurable options
	86	*/
	87	#define CONFIG_SYS_LONGHELP /* undef to save memory */
f9c6fac4 SB	88	#define CONFIG_CMDLINE_EDITING
	89	#define CONFIG_AUTO_COMPLETE
	90	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
	91
f9c6fac4 SB	92	#define CONFIG_SYS_MAXARGS 32 /* max number of command */
f9c6fac4 SB	93	/* args */
f9c6fac4 SB	94	/* memtest works on */
	95	#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
	96	#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
	97	0x01F00000) /* 31MB */
	98
	99	#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
	100	/* address */
	101
	102	/*
	103	* AM3517 has 12 GP timers, they can be driven by the system clock
	104	* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
	105	* This rate is divided by a local divisor.
	106	*/
	107	#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
	108	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
f9c6fac4	109
f9c6fac4 SB	110	/*
	111	* Physical Memory Map
	112	*/
	113	#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
	114	#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
f9c6fac4 SB	115	#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
	116
	117	/*
	118	* FLASH and environment organization
	119	*/
	120
	121	/* ** PISMO SUPPORT * */
f9c6fac4 SB	122
	123	/* Redundant Environment */
	124	#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
7672d9d5 AF	125	#define CONFIG_ENV_OFFSET 0x180000
7672d9d5 AF	126	#define CONFIG_ENV_ADDR 0x180000
f9c6fac4 SB	127	#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
	128	2 * CONFIG_SYS_ENV_SECT_SIZE)
	129	#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
	130
	131	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	132	#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
	133	#define CONFIG_SYS_INIT_RAM_SIZE 0x800
	134	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	135	CONFIG_SYS_INIT_RAM_SIZE - \
	136	GENERATED_GBL_DATA_SIZE)
	137
	138	/*
	139	* ethernet support, EMAC
	140	*
	141	*/
	142	#define CONFIG_DRIVER_TI_EMAC
	143	#define CONFIG_DRIVER_TI_EMAC_USE_RMII
	144	#define CONFIG_MII
f9c6fac4 SB	145	#define CONFIG_BOOTP_DNS
	146	#define CONFIG_BOOTP_DNS2
	147	#define CONFIG_BOOTP_SEND_HOSTNAME
	148	#define CONFIG_NET_RETRY_COUNT 10
f9c6fac4 SB	149
f9c6fac4 SB	150	/* Defines for SPL */
47f7bcae	151	#define CONFIG_SPL_FRAMEWORK
f9c6fac4	152	#define CONFIG_SPL_CONSOLE
8ad59c9a	153	#define CONFIG_SPL_NAND_SOFTECC
f9c6fac4 SB	154	#define CONFIG_SPL_NAND_WORKSPACE 0x8f07f000 /* below BSS */
f9c6fac4 SB	155
6f2f01b9 SW	156	#define CONFIG_SPL_NAND_BASE
	157	#define CONFIG_SPL_NAND_DRIVERS
	158	#define CONFIG_SPL_NAND_ECC
f9c6fac4 SB	159
f9c6fac4 SB	160	#define CONFIG_SPL_TEXT_BASE 0x40200000 /CONFIG_SYS_SRAM_START/
fa2f81b0 TR	161	#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
fa2f81b0 TR	162	CONFIG_SPL_TEXT_BASE)
f51c8a99	163	#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
f9c6fac4 SB	164
	165	#define CONFIG_SYS_SPL_MALLOC_START 0x8f000000
	166	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
	167	#define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */
	168	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
	169
f51c8a99 SB	170	#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
	171	#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
	172
	173	/* FAT */
	174	#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
	175	#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args"
	176
	177	/* RAW SD card / eMMC */
	178	#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */
	179	#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */
	180	#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */
	181
f9c6fac4 SB	182	/* NAND boot config */
	183	#define CONFIG_SYS_NAND_PAGE_COUNT 64
	184	#define CONFIG_SYS_NAND_PAGE_SIZE 2048
	185	#define CONFIG_SYS_NAND_OOBSIZE 64
	186	#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
	187	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	188	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
	189	#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\
	190	48, 49, 50, 51, 52, 53, 54, 55,\
	191	56, 57, 58, 59, 60, 61, 62, 63}
	192	#define CONFIG_SYS_NAND_ECCSIZE 256
	193	#define CONFIG_SYS_NAND_ECCBYTES 3
3f719069	194	#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW
f9c6fac4	195
f9c6fac4 SB	196	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
	197
	198	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
	199	#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
	200
f9c6fac4 SB	201	#define CONFIG_MTD_PARTITIONS
f9c6fac4 SB	202	#define CONFIG_MTD_DEVICE
f9c6fac4 SB	203
f9c6fac4 SB	204	/* Setup MTD for NAND on the SOM */
f9c6fac4	205
f9c6fac4 SB	206	#define CONFIG_TAM3517_SETTINGS \
	207	"netdev=eth0\0" \
	208	"nandargs=setenv bootargs root=${nandroot} " \
	209	"rootfstype=${nandrootfstype}\0" \
	210	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	211	"nfsroot=${serverip}:${rootpath}\0" \
	212	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	213	"addip_sta=setenv bootargs ${bootargs} " \
	214	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	215	":${hostname}:${netdev}:off panic=1\0" \
	216	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
	217	"addip=if test -n ${ipdyn};then run addip_dyn;" \
	218	"else run addip_sta;fi\0" \
	219	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
	220	"addtty=setenv bootargs ${bootargs}" \
	221	" console=ttyO0,${baudrate}\0" \
	222	"addmisc=setenv bootargs ${bootargs} ${misc}\0" \
	223	"loadaddr=82000000\0" \
	224	"kernel_addr_r=82000000\0" \
93ea89f0 MV	225	"hostname=" __stringify(CONFIG_HOSTNAME) "\0" \
93ea89f0 MV	226	"bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
f9c6fac4 SB	227	"flash_self=run ramargs addip addtty addmtd addmisc;" \
	228	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
	229	"flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
	230	"bootm ${kernel_addr}\0" \
	231	"nandboot=run nandargs addip addtty addmtd addmisc;" \
	232	"nand read ${kernel_addr_r} kernel\0" \
	233	"bootm ${kernel_addr_r}\0" \
	234	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
	235	"run nfsargs addip addtty addmtd addmisc;" \
	236	"bootm ${kernel_addr_r}\0" \
	237	"net_self=if run net_self_load;then " \
	238	"run ramargs addip addtty addmtd addmisc;" \
	239	"bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
	240	"else echo Images not loades;fi\0" \
93ea89f0	241	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \
f9c6fac4 SB	242	"load=tftp ${loadaddr} ${u-boot}\0" \
f9c6fac4 SB	243	"loadmlo=tftp ${loadaddr} ${mlo}\0" \
93ea89f0	244	"mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \
f9c6fac4 SB	245	"uboot_addr=0x80000\0" \
	246	"update=nandecc sw;nand erase ${uboot_addr} 100000;" \
	247	"nand write ${loadaddr} ${uboot_addr} 80000\0" \
	248	"updatemlo=nandecc hw;nand erase 0 20000;" \
	249	"nand write ${loadaddr} 0 20000\0" \
	250	"upd=if run load;then echo Updating u-boot;if run update;" \
	251	"then echo U-Boot updated;" \
	252	"else echo Error updating u-boot !;" \
	253	"echo Board without bootloader !!;" \
	254	"fi;" \
	255	"else echo U-Boot not downloaded..exiting;fi\0" \
	256
8103c6f0 SB	257	/*
	258	* this is common code for all TAM3517 boards.
	259	* MAC address is stored from manufacturer in
	260	* I2C EEPROM
	261	*/
	262	#if !(defined(__KERNEL_STRICT_NAMES) \|\| defined(__ASSEMBLY__))
8103c6f0 SB	263	/*
	264	* The I2C EEPROM on the TAM3517 contains
	265	* mac address and production data
	266	*/
	267	struct tam3517_module_info {
	268	char customer[48];
	269	char product[48];
	270
	271	/*
	272	* bit 0~47 : sequence number
	273	* bit 48~55 : week of year, from 0.
	274	* bit 56~63 : year
	275	*/
	276	unsigned long long sequence_number;
	277
	278	/*
	279	* bit 0~7 : revision fixed
	280	* bit 8~15 : revision major
	281	* bit 16~31 : TNxxx
	282	*/
	283	unsigned int revision;
	284	unsigned char eth_addr[4][8];
	285	unsigned char _rev[100];
	286	};
	287
31f5b651 SB	288	#define TAM3517_READ_EEPROM(info, ret) \
31f5b651 SB	289	do { \
6789e84e	290	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \
8103c6f0	291	if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, \
31f5b651 SB	292	(void )info, sizeof(info))) \
	293	ret = 1; \
	294	else \
	295	ret = 0; \
	296	} while (0)
	297
	298	#define TAM3517_READ_MAC_FROM_EEPROM(info) \
	299	do { \
	300	char buf[80], ethname[20]; \
	301	int i; \
8103c6f0	302	memset(buf, 0, sizeof(buf)); \
31f5b651	303	for (i = 0 ; i < ARRAY_SIZE((info)->eth_addr); i++) { \
8103c6f0	304	sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X", \
31f5b651 SB	305	(info)->eth_addr[i][5], \
	306	(info)->eth_addr[i][4], \
	307	(info)->eth_addr[i][3], \
	308	(info)->eth_addr[i][2], \
	309	(info)->eth_addr[i][1], \
	310	(info)->eth_addr[i][0]); \
8103c6f0 SB	311	\
	312	if (i) \
	313	sprintf(ethname, "eth%daddr", i); \
	314	else \
192bc694	315	strcpy(ethname, "ethaddr"); \
8103c6f0	316	printf("Setting %s from EEPROM with %s\n", ethname, buf);\
382bee57	317	env_set(ethname, buf); \
8103c6f0 SB	318	} \
8103c6f0 SB	319	} while (0)
31f5b651 SB	320
	321	/* The following macros are taken from Technexion's documentation */
	322	#define TAM3517_sequence_number(info) \
	323	((info)->sequence_number % 0x1000000000000LL)
	324	#define TAM3517_week_of_year(info) (((info)->sequence_number >> 48) % 0x100)
	325	#define TAM3517_year(info) ((info)->sequence_number >> 56)
	326	#define TAM3517_revision_fixed(info) ((info)->revision % 0x100)
	327	#define TAM3517_revision_major(info) (((info)->revision >> 8) % 0x100)
	328	#define TAM3517_revision_tn(info) ((info)->revision >> 16)
	329
	330	#define TAM3517_PRINT_SOM_INFO(info) \
	331	do { \
	332	printf("Vendor:%s\n", (info)->customer); \
	333	printf("SOM: %s\n", (info)->product); \
	334	printf("SeqNr: %02llu%02llu%012llu\n", \
	335	TAM3517_year(info), \
	336	TAM3517_week_of_year(info), \
	337	TAM3517_sequence_number(info)); \
	338	printf("Rev: TN%u %u.%u\n", \
	339	TAM3517_revision_tn(info), \
	340	TAM3517_revision_major(info), \
	341	TAM3517_revision_fixed(info)); \
	342	} while (0)
	343
8103c6f0 SB	344	#endif
8103c6f0 SB	345
f9c6fac4	346	#endif /* __TAM3517_H */