[people/ms/u-boot.git] / include / configs / tam3517-common.h

/*
 * Copyright (C) 2011
 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
 *
 * Copyright (C) 2009 TechNexion Ltd.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __TAM3517_H
#define __TAM3517_H

/*
 * High Level Configuration Options
 */
#define CONFIG_OMAP		/* in a TI OMAP core */
#define CONFIG_OMAP_GPIO
#define CONFIG_OMAP_COMMON
/* Common ARM Erratas */
#define CONFIG_ARM_ERRATA_454179
#define CONFIG_ARM_ERRATA_430973
#define CONFIG_ARM_ERRATA_621766

#define CONFIG_SYS_TEXT_BASE 0x80008000

#define CONFIG_EMIF4	/* The chip has EMIF4 controller */

#include <asm/arch/cpu.h>		/* get chip and board defs */
#include <asm/arch/omap.h>

/*
 * Display CPU and Board information
 */
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO

/* Clock Defines */
#define V_OSCK			26000000	/* Clock output from T2 */
#define V_SCLK			(V_OSCK >> 1)

#define CONFIG_MISC_INIT_R

#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG

/*
 * Size of malloc() pool
 */
#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB sector */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10) + \
					2 * 1024 * 1024)
/*
 * DDR related
 */
#define CONFIG_OMAP3_MICRON_DDR		/* Micron DDR */
#define CONFIG_SYS_CS0_SIZE		(256 * 1024 * 1024)

/*
 * Hardware drivers
 */

/*
 * NS16550 Configuration
 */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		48000000	/* 48MHz (APLL96/2) */

/*
 * select serial console configuration
 */
#define CONFIG_CONS_INDEX		1
#define CONFIG_SYS_NS16550_COM1		OMAP34XX_UART1
#define CONFIG_SERIAL1			/* UART1 */

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
					115200}
#define CONFIG_MMC
#define CONFIG_OMAP_HSMMC
#define CONFIG_GENERIC_MMC
#define CONFIG_DOS_PARTITION

/* EHCI */
#define CONFIG_OMAP3_GPIO_5
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_OMAP
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO	25
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3

/* commands to include */
#define CONFIG_CMD_NAND		/* NAND support			*/
#define CONFIG_CMD_EEPROM

#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_I2C
#define CONFIG_SYS_OMAP24_I2C_SPEED	400000
#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
#define CONFIG_SYS_I2C_OMAP34XX
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50		/* base address */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1		/* bytes of address */
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07

/*
 * Board NAND Info.
 */
#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
							/* to access */
							/* nand at CS0 */

#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
							/* NAND devices */

#define CONFIG_AUTO_COMPLETE

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_CMDLINE_EDITING
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */

/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		32	/* max number of command */
						/* args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
					0x01F00000) /* 31MB */

#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
								/* address */

/*
 * AM3517 has 12 GP timers, they can be driven by the system clock
 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 * This rate is divided by a local divisor.
 */
#define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */

/*
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1

/*
 * FLASH and environment organization
 */

/* **** PISMO SUPPORT *** */
#define CONFIG_NAND
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_ENV_IS_IN_NAND
#define SMNAND_ENV_OFFSET		0x180000 /* environment starts here */

/* Redundant Environment */
#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
						2 * CONFIG_SYS_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE	0x800
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - \
					 GENERATED_GBL_DATA_SIZE)

/*
 * ethernet support, EMAC
 *
 */
#define CONFIG_DRIVER_TI_EMAC
#define CONFIG_DRIVER_TI_EMAC_USE_RMII
#define CONFIG_MII
#define CONFIG_EMAC_MDIO_PHY_NUM	0
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 10

/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_CONSOLE
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_NAND_SOFTECC
#define CONFIG_SPL_NAND_WORKSPACE	0x8f07f000 /* below BSS */

#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"

#define CONFIG_SPL_TEXT_BASE		0x40200000 /*CONFIG_SYS_SRAM_START*/
#define CONFIG_SPL_MAX_SIZE		(SRAM_SCRATCH_SPACE_ADDR - \
					 CONFIG_SPL_TEXT_BASE)
#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK

#define CONFIG_SYS_SPL_MALLOC_START	0x8f000000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
#define CONFIG_SPL_BSS_START_ADDR	0x8f080000 /* end of RAM */
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000

#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot.img"

/* FAT */
#define CONFIG_SPL_FS_LOAD_KERNEL_NAME		"uImage"
#define CONFIG_SPL_FS_LOAD_ARGS_NAME		"args"

/* RAW SD card / eMMC */
#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0x900	/* address 0x120000 */
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0x80	/* address 0x10000 */
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	0x80	/* 64KiB */

/* NAND boot config */
#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
#define CONFIG_SYS_NAND_PAGE_COUNT	64
#define CONFIG_SYS_NAND_PAGE_SIZE	2048
#define CONFIG_SYS_NAND_OOBSIZE		64
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
#define CONFIG_SYS_NAND_ECCPOS		{40, 41, 42, 43, 44, 45, 46, 47,\
					 48, 49, 50, 51, 52, 53, 54, 55,\
					 56, 57, 58, 59, 60, 61, 62, 63}
#define CONFIG_SYS_NAND_ECCSIZE		256
#define CONFIG_SYS_NAND_ECCBYTES	3
#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_SW
#define CONFIG_NAND_OMAP_GPMC_PREFETCH

#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE

#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x80000

#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_RBTREE
#define CONFIG_LZO
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE
#define CONFIG_CMD_MTDPARTS

/* Setup MTD for NAND on the SOM */
#define MTDIDS_DEFAULT		"nand0=omap2-nand.0"
#define MTDPARTS_DEFAULT	"mtdparts=omap2-nand.0:512k(MLO)," \
				"1m(u-boot),256k(env1)," \
				"256k(env2),6m(kernel),-(rootfs)"

#define	CONFIG_TAM3517_SETTINGS						\
	"netdev=eth0\0"							\
	"nandargs=setenv bootargs root=${nandroot} "			\
		"rootfstype=${nandrootfstype}\0"			\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip_sta=setenv bootargs ${bootargs} "			\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0"		\
	"addip=if test -n ${ipdyn};then run addip_dyn;"			\
		"else run addip_sta;fi\0"				\
	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
	"addtty=setenv bootargs ${bootargs}"				\
		" console=ttyO0,${baudrate}\0"				\
	"addmisc=setenv bootargs ${bootargs} ${misc}\0"			\
	"loadaddr=82000000\0"						\
	"kernel_addr_r=82000000\0"					\
	"hostname=" __stringify(CONFIG_HOSTNAME) "\0"			\
	"bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0"		\
	"flash_self=run ramargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"flash_nfs=run nfsargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr}\0"				\
	"nandboot=run nandargs addip addtty addmtd addmisc;"		\
		"nand read ${kernel_addr_r} kernel\0"			\
		"bootm ${kernel_addr_r}\0"				\
	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
		"run nfsargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr_r}\0"				\
	"net_self=if run net_self_load;then "				\
		"run ramargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr_r} ${ramdisk_addr_r};"		\
		"else echo Images not loades;fi\0"			\
	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0"		\
	"load=tftp ${loadaddr} ${u-boot}\0"				\
	"loadmlo=tftp ${loadaddr} ${mlo}\0"				\
	"mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0"			\
	"uboot_addr=0x80000\0"						\
	"update=nandecc sw;nand erase ${uboot_addr} 100000;"		\
		"nand write ${loadaddr} ${uboot_addr} 80000\0"		\
	"updatemlo=nandecc hw;nand erase 0 20000;"			\
		"nand write ${loadaddr} 0 20000\0"			\
	"upd=if run load;then echo Updating u-boot;if run update;"	\
		"then echo U-Boot updated;"				\
			"else echo Error updating u-boot !;"		\
			"echo Board without bootloader !!;"		\
		"fi;"							\
		"else echo U-Boot not downloaded..exiting;fi\0"		\

/*
 * this is common code for all TAM3517 boards.
 * MAC address is stored from manufacturer in
 * I2C EEPROM
 */
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
/*
 * The I2C EEPROM on the TAM3517 contains
 * mac address and production data
 */
struct tam3517_module_info {
	char customer[48];
	char product[48];

	/*
	 * bit 0~47  : sequence number
	 * bit 48~55 : week of year, from 0.
	 * bit 56~63 : year
	 */
	unsigned long long sequence_number;

	/*
	 * bit 0~7   : revision fixed
	 * bit 8~15  : revision major
	 * bit 16~31 : TNxxx
	 */
	unsigned int revision;
	unsigned char eth_addr[4][8];
	unsigned char _rev[100];
};

#define TAM3517_READ_EEPROM(info, ret) \
do {								\
	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \
	if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,		\
		(void *)info, sizeof(*info)))			\
		ret = 1;					\
	else							\
		ret = 0;					\
} while (0)

#define TAM3517_READ_MAC_FROM_EEPROM(info)			\
do {								\
	char buf[80], ethname[20];				\
	int i;							\
	memset(buf, 0, sizeof(buf));				\
	for (i = 0 ; i < ARRAY_SIZE((info)->eth_addr); i++) {	\
		sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X",	\
			(info)->eth_addr[i][5],			\
			(info)->eth_addr[i][4],			\
			(info)->eth_addr[i][3],			\
			(info)->eth_addr[i][2],			\
			(info)->eth_addr[i][1],			\
			(info)->eth_addr[i][0]);			\
								\
		if (i)						\
			sprintf(ethname, "eth%daddr", i);	\
		else						\
			strcpy(ethname, "ethaddr");		\
		printf("Setting %s from EEPROM with %s\n", ethname, buf);\
		setenv(ethname, buf);				\
	}							\
} while (0)

/* The following macros are taken from Technexion's documentation */
#define TAM3517_sequence_number(info) \
	((info)->sequence_number % 0x1000000000000LL)
#define TAM3517_week_of_year(info) (((info)->sequence_number >> 48) % 0x100)
#define TAM3517_year(info) ((info)->sequence_number >> 56)
#define TAM3517_revision_fixed(info) ((info)->revision % 0x100)
#define TAM3517_revision_major(info) (((info)->revision >> 8) % 0x100)
#define TAM3517_revision_tn(info) ((info)->revision >> 16)

#define TAM3517_PRINT_SOM_INFO(info)				\
do {								\
	printf("Vendor:%s\n", (info)->customer);		\
	printf("SOM:   %s\n", (info)->product);			\
	printf("SeqNr: %02llu%02llu%012llu\n",			\
		TAM3517_year(info),				\
		TAM3517_week_of_year(info),			\
		TAM3517_sequence_number(info));			\
	printf("Rev:   TN%u %u.%u\n",				\
		TAM3517_revision_tn(info),			\
		TAM3517_revision_major(info),			\
		TAM3517_revision_fixed(info));			\
} while (0)

#endif

#endif /* __TAM3517_H */
Commit	Line	Data
f9c6fac4 SB	1	/*
	2	* Copyright (C) 2011
	3	* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
	4	*
	5	* Copyright (C) 2009 TechNexion Ltd.
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
f9c6fac4 SB	8	*/
	9
	10	#ifndef __TAM3517_H
	11	#define __TAM3517_H
	12
	13	/*
	14	* High Level Configuration Options
	15	*/
	16	#define CONFIG_OMAP /* in a TI OMAP core */
308252ad	17	#define CONFIG_OMAP_GPIO
806d2792	18	#define CONFIG_OMAP_COMMON
c6f90e14 NM	19	/* Common ARM Erratas */
	20	#define CONFIG_ARM_ERRATA_454179
	21	#define CONFIG_ARM_ERRATA_430973
	22	#define CONFIG_ARM_ERRATA_621766
f9c6fac4 SB	23
	24	#define CONFIG_SYS_TEXT_BASE 0x80008000
	25
f9c6fac4 SB	26	#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
	27
	28	#include <asm/arch/cpu.h> /* get chip and board defs */
987ec585	29	#include <asm/arch/omap.h>
f9c6fac4 SB	30
	31	/*
	32	* Display CPU and Board information
	33	*/
	34	#define CONFIG_DISPLAY_CPUINFO
	35	#define CONFIG_DISPLAY_BOARDINFO
	36
	37	/* Clock Defines */
	38	#define V_OSCK 26000000 /* Clock output from T2 */
	39	#define V_SCLK (V_OSCK >> 1)
	40
f9c6fac4 SB	41	#define CONFIG_MISC_INIT_R
	42
	43	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	44	#define CONFIG_SETUP_MEMORY_TAGS
	45	#define CONFIG_INITRD_TAG
	46	#define CONFIG_REVISION_TAG
	47
	48	/*
	49	* Size of malloc() pool
	50	*/
	51	#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
	52	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10) + \
	53	2 * 1024 * 1024)
	54	/*
	55	* DDR related
	56	*/
	57	#define CONFIG_OMAP3_MICRON_DDR /* Micron DDR */
	58	#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
	59
	60	/*
	61	* Hardware drivers
	62	*/
	63
	64	/*
	65	* NS16550 Configuration
	66	*/
f9c6fac4 SB	67	#define CONFIG_SYS_NS16550_SERIAL
	68	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	69	#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
	70
	71	/*
	72	* select serial console configuration
	73	*/
	74	#define CONFIG_CONS_INDEX 1
	75	#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
	76	#define CONFIG_SERIAL1 /* UART1 */
	77
	78	/* allow to overwrite serial and ethaddr */
	79	#define CONFIG_ENV_OVERWRITE
	80	#define CONFIG_BAUDRATE 115200
	81	#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
	82	115200}
	83	#define CONFIG_MMC
	84	#define CONFIG_OMAP_HSMMC
	85	#define CONFIG_GENERIC_MMC
	86	#define CONFIG_DOS_PARTITION
	87
	88	/* EHCI */
	89	#define CONFIG_OMAP3_GPIO_5
	90	#define CONFIG_USB_EHCI
	91	#define CONFIG_USB_EHCI_OMAP
	92	#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25
	93	#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
f9c6fac4	94
f9c6fac4	95	/* commands to include */
f9c6fac4	96	#define CONFIG_CMD_NAND /* NAND support */
8103c6f0	97	#define CONFIG_CMD_EEPROM
f9c6fac4	98
f9c6fac4	99	#define CONFIG_SYS_NO_FLASH
6789e84e HS	100	#define CONFIG_SYS_I2C
	101	#define CONFIG_SYS_OMAP24_I2C_SPEED 400000
	102	#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
	103	#define CONFIG_SYS_I2C_OMAP34XX
8103c6f0 SB	104	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */
	105	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
	106	#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
f9c6fac4 SB	107
	108	/*
	109	* Board NAND Info.
	110	*/
	111	#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
	112	/* to access */
	113	/* nand at CS0 */
	114
	115	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
	116	/* NAND devices */
f9c6fac4 SB	117
	118	#define CONFIG_AUTO_COMPLETE
	119
	120	/*
	121	* Miscellaneous configurable options
	122	*/
	123	#define CONFIG_SYS_LONGHELP /* undef to save memory */
f9c6fac4 SB	124	#define CONFIG_CMDLINE_EDITING
	125	#define CONFIG_AUTO_COMPLETE
	126	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
	127
	128	/* Print Buffer Size */
	129	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	130	sizeof(CONFIG_SYS_PROMPT) + 16)
	131	#define CONFIG_SYS_MAXARGS 32 /* max number of command */
	132	/* args */
	133	/* Boot Argument Buffer Size */
	134	#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
	135	/* memtest works on */
	136	#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
	137	#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
	138	0x01F00000) /* 31MB */
	139
	140	#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
	141	/* address */
	142
	143	/*
	144	* AM3517 has 12 GP timers, they can be driven by the system clock
	145	* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
	146	* This rate is divided by a local divisor.
	147	*/
	148	#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
	149	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
f9c6fac4	150
f9c6fac4 SB	151	/*
	152	* Physical Memory Map
	153	*/
	154	#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
	155	#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
f9c6fac4 SB	156	#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
	157
	158	/*
	159	* FLASH and environment organization
	160	*/
	161
	162	/* ** PISMO SUPPORT * */
0970051d	163	#define CONFIG_NAND
f9c6fac4	164	#define CONFIG_NAND_OMAP_GPMC
f9c6fac4 SB	165	#define CONFIG_ENV_IS_IN_NAND
	166	#define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */
	167
	168	/* Redundant Environment */
	169	#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
	170	#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
	171	#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
	172	#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
	173	2 * CONFIG_SYS_ENV_SECT_SIZE)
	174	#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
	175
	176	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	177	#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
	178	#define CONFIG_SYS_INIT_RAM_SIZE 0x800
	179	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	180	CONFIG_SYS_INIT_RAM_SIZE - \
	181	GENERATED_GBL_DATA_SIZE)
	182
	183	/*
	184	* ethernet support, EMAC
	185	*
	186	*/
	187	#define CONFIG_DRIVER_TI_EMAC
	188	#define CONFIG_DRIVER_TI_EMAC_USE_RMII
	189	#define CONFIG_MII
	190	#define CONFIG_EMAC_MDIO_PHY_NUM 0
f9c6fac4 SB	191	#define CONFIG_BOOTP_DNS
	192	#define CONFIG_BOOTP_DNS2
	193	#define CONFIG_BOOTP_SEND_HOSTNAME
	194	#define CONFIG_NET_RETRY_COUNT 10
f9c6fac4 SB	195
f9c6fac4 SB	196	/* Defines for SPL */
47f7bcae	197	#define CONFIG_SPL_FRAMEWORK
d7cb93b2	198	#define CONFIG_SPL_BOARD_INIT
f9c6fac4 SB	199	#define CONFIG_SPL_CONSOLE
f9c6fac4 SB	200	#define CONFIG_SPL_NAND_SIMPLE
8ad59c9a	201	#define CONFIG_SPL_NAND_SOFTECC
f9c6fac4 SB	202	#define CONFIG_SPL_NAND_WORKSPACE 0x8f07f000 /* below BSS */
	203
	204	#define CONFIG_SPL_LIBCOMMON_SUPPORT
	205	#define CONFIG_SPL_LIBDISK_SUPPORT
	206	#define CONFIG_SPL_I2C_SUPPORT
f51c8a99	207	#define CONFIG_SPL_MMC_SUPPORT
f9c6fac4 SB	208	#define CONFIG_SPL_LIBGENERIC_SUPPORT
f9c6fac4 SB	209	#define CONFIG_SPL_SERIAL_SUPPORT
16e41c85	210	#define CONFIG_SPL_GPIO_SUPPORT
f9c6fac4 SB	211	#define CONFIG_SPL_POWER_SUPPORT
f9c6fac4 SB	212	#define CONFIG_SPL_NAND_SUPPORT
6f2f01b9 SW	213	#define CONFIG_SPL_NAND_BASE
	214	#define CONFIG_SPL_NAND_DRIVERS
	215	#define CONFIG_SPL_NAND_ECC
f9c6fac4 SB	216	#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
	217
	218	#define CONFIG_SPL_TEXT_BASE 0x40200000 /CONFIG_SYS_SRAM_START/
fa2f81b0 TR	219	#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
fa2f81b0 TR	220	CONFIG_SPL_TEXT_BASE)
f51c8a99	221	#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
f9c6fac4 SB	222
	223	#define CONFIG_SYS_SPL_MALLOC_START 0x8f000000
	224	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
	225	#define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */
	226	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
	227
f51c8a99 SB	228	#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
	229	#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
	230	#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
	231
	232	/* FAT */
	233	#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
	234	#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args"
	235
	236	/* RAW SD card / eMMC */
	237	#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */
	238	#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */
	239	#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */
	240
f9c6fac4	241	/* NAND boot config */
55f1b39f	242	#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
f9c6fac4 SB	243	#define CONFIG_SYS_NAND_PAGE_COUNT 64
	244	#define CONFIG_SYS_NAND_PAGE_SIZE 2048
	245	#define CONFIG_SYS_NAND_OOBSIZE 64
	246	#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
	247	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	248	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
	249	#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\
	250	48, 49, 50, 51, 52, 53, 54, 55,\
	251	56, 57, 58, 59, 60, 61, 62, 63}
	252	#define CONFIG_SYS_NAND_ECCSIZE 256
	253	#define CONFIG_SYS_NAND_ECCBYTES 3
3f719069	254	#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW
817aa32b	255	#define CONFIG_NAND_OMAP_GPMC_PREFETCH
f9c6fac4	256
f9c6fac4 SB	257	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
	258
	259	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
	260	#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
	261
f9c6fac4 SB	262	#define CONFIG_CMD_UBI
	263	#define CONFIG_CMD_UBIFS
	264	#define CONFIG_RBTREE
	265	#define CONFIG_LZO
	266	#define CONFIG_MTD_PARTITIONS
	267	#define CONFIG_MTD_DEVICE
	268	#define CONFIG_CMD_MTDPARTS
	269
	270	/* Setup MTD for NAND on the SOM */
	271	#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
	272	#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \
1fdabedd SB	273	"1m(u-boot),256k(env1)," \
1fdabedd SB	274	"256k(env2),6m(kernel),-(rootfs)"
f9c6fac4	275
f9c6fac4 SB	276	#define CONFIG_TAM3517_SETTINGS \
	277	"netdev=eth0\0" \
	278	"nandargs=setenv bootargs root=${nandroot} " \
	279	"rootfstype=${nandrootfstype}\0" \
	280	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	281	"nfsroot=${serverip}:${rootpath}\0" \
	282	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	283	"addip_sta=setenv bootargs ${bootargs} " \
	284	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	285	":${hostname}:${netdev}:off panic=1\0" \
	286	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
	287	"addip=if test -n ${ipdyn};then run addip_dyn;" \
	288	"else run addip_sta;fi\0" \
	289	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
	290	"addtty=setenv bootargs ${bootargs}" \
	291	" console=ttyO0,${baudrate}\0" \
	292	"addmisc=setenv bootargs ${bootargs} ${misc}\0" \
	293	"loadaddr=82000000\0" \
	294	"kernel_addr_r=82000000\0" \
93ea89f0 MV	295	"hostname=" __stringify(CONFIG_HOSTNAME) "\0" \
93ea89f0 MV	296	"bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
f9c6fac4 SB	297	"flash_self=run ramargs addip addtty addmtd addmisc;" \
	298	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
	299	"flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
	300	"bootm ${kernel_addr}\0" \
	301	"nandboot=run nandargs addip addtty addmtd addmisc;" \
	302	"nand read ${kernel_addr_r} kernel\0" \
	303	"bootm ${kernel_addr_r}\0" \
	304	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
	305	"run nfsargs addip addtty addmtd addmisc;" \
	306	"bootm ${kernel_addr_r}\0" \
	307	"net_self=if run net_self_load;then " \
	308	"run ramargs addip addtty addmtd addmisc;" \
	309	"bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
	310	"else echo Images not loades;fi\0" \
93ea89f0	311	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \
f9c6fac4 SB	312	"load=tftp ${loadaddr} ${u-boot}\0" \
f9c6fac4 SB	313	"loadmlo=tftp ${loadaddr} ${mlo}\0" \
93ea89f0	314	"mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \
f9c6fac4 SB	315	"uboot_addr=0x80000\0" \
	316	"update=nandecc sw;nand erase ${uboot_addr} 100000;" \
	317	"nand write ${loadaddr} ${uboot_addr} 80000\0" \
	318	"updatemlo=nandecc hw;nand erase 0 20000;" \
	319	"nand write ${loadaddr} 0 20000\0" \
	320	"upd=if run load;then echo Updating u-boot;if run update;" \
	321	"then echo U-Boot updated;" \
	322	"else echo Error updating u-boot !;" \
	323	"echo Board without bootloader !!;" \
	324	"fi;" \
	325	"else echo U-Boot not downloaded..exiting;fi\0" \
	326
8103c6f0 SB	327	/*
	328	* this is common code for all TAM3517 boards.
	329	* MAC address is stored from manufacturer in
	330	* I2C EEPROM
	331	*/
	332	#if !(defined(__KERNEL_STRICT_NAMES) \|\| defined(__ASSEMBLY__))
8103c6f0 SB	333	/*
	334	* The I2C EEPROM on the TAM3517 contains
	335	* mac address and production data
	336	*/
	337	struct tam3517_module_info {
	338	char customer[48];
	339	char product[48];
	340
	341	/*
	342	* bit 0~47 : sequence number
	343	* bit 48~55 : week of year, from 0.
	344	* bit 56~63 : year
	345	*/
	346	unsigned long long sequence_number;
	347
	348	/*
	349	* bit 0~7 : revision fixed
	350	* bit 8~15 : revision major
	351	* bit 16~31 : TNxxx
	352	*/
	353	unsigned int revision;
	354	unsigned char eth_addr[4][8];
	355	unsigned char _rev[100];
	356	};
	357
31f5b651 SB	358	#define TAM3517_READ_EEPROM(info, ret) \
31f5b651 SB	359	do { \
6789e84e	360	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \
8103c6f0	361	if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, \
31f5b651 SB	362	(void )info, sizeof(info))) \
	363	ret = 1; \
	364	else \
	365	ret = 0; \
	366	} while (0)
	367
	368	#define TAM3517_READ_MAC_FROM_EEPROM(info) \
	369	do { \
	370	char buf[80], ethname[20]; \
	371	int i; \
8103c6f0	372	memset(buf, 0, sizeof(buf)); \
31f5b651	373	for (i = 0 ; i < ARRAY_SIZE((info)->eth_addr); i++) { \
8103c6f0	374	sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X", \
31f5b651 SB	375	(info)->eth_addr[i][5], \
	376	(info)->eth_addr[i][4], \
	377	(info)->eth_addr[i][3], \
	378	(info)->eth_addr[i][2], \
	379	(info)->eth_addr[i][1], \
	380	(info)->eth_addr[i][0]); \
8103c6f0 SB	381	\
	382	if (i) \
	383	sprintf(ethname, "eth%daddr", i); \
	384	else \
192bc694	385	strcpy(ethname, "ethaddr"); \
8103c6f0 SB	386	printf("Setting %s from EEPROM with %s\n", ethname, buf);\
	387	setenv(ethname, buf); \
	388	} \
	389	} while (0)
31f5b651 SB	390
	391	/* The following macros are taken from Technexion's documentation */
	392	#define TAM3517_sequence_number(info) \
	393	((info)->sequence_number % 0x1000000000000LL)
	394	#define TAM3517_week_of_year(info) (((info)->sequence_number >> 48) % 0x100)
	395	#define TAM3517_year(info) ((info)->sequence_number >> 56)
	396	#define TAM3517_revision_fixed(info) ((info)->revision % 0x100)
	397	#define TAM3517_revision_major(info) (((info)->revision >> 8) % 0x100)
	398	#define TAM3517_revision_tn(info) ((info)->revision >> 16)
	399
	400	#define TAM3517_PRINT_SOM_INFO(info) \
	401	do { \
	402	printf("Vendor:%s\n", (info)->customer); \
	403	printf("SOM: %s\n", (info)->product); \
	404	printf("SeqNr: %02llu%02llu%012llu\n", \
	405	TAM3517_year(info), \
	406	TAM3517_week_of_year(info), \
	407	TAM3517_sequence_number(info)); \
	408	printf("Rev: TN%u %u.%u\n", \
	409	TAM3517_revision_tn(info), \
	410	TAM3517_revision_major(info), \
	411	TAM3517_revision_fixed(info)); \
	412	} while (0)
	413
8103c6f0 SB	414	#endif
8103c6f0 SB	415
f9c6fac4	416	#endif /* __TAM3517_H */