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f01b631f TW |
1 | /* |
2 | * (C) Copyright 2010-2012 | |
3 | * NVIDIA Corporation <www.nvidia.com> | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
f01b631f TW |
6 | */ |
7 | ||
bfcf46db TW |
8 | #ifndef _TEGRA_COMMON_H_ |
9 | #define _TEGRA_COMMON_H_ | |
1ace4022 | 10 | #include <linux/sizes.h> |
f01b631f TW |
11 | #include <linux/stringify.h> |
12 | ||
13 | /* | |
14 | * High Level Configuration Options | |
15 | */ | |
f01b631f TW |
16 | #define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */ |
17 | ||
f01b631f TW |
18 | #include <asm/arch/tegra.h> /* get chip and board defs */ |
19 | ||
f41f0a19 TR |
20 | /* Use the Tegra US timer on ARMv7, but the architected timer on ARMv8. */ |
21 | #ifndef CONFIG_ARM64 | |
31df9893 RH |
22 | #define CONFIG_SYS_TIMER_RATE 1000000 |
23 | #define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE | |
f41f0a19 | 24 | #endif |
31df9893 | 25 | |
f01b631f | 26 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
f01b631f TW |
27 | |
28 | /* Environment */ | |
f01b631f TW |
29 | #define CONFIG_ENV_SIZE 0x2000 /* Total Size Environment */ |
30 | ||
f01b631f | 31 | /* |
bfcf46db | 32 | * NS16550 Configuration |
f01b631f | 33 | */ |
1874626b | 34 | #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK |
f01b631f | 35 | |
f175603f SW |
36 | /* |
37 | * Common HW configuration. | |
38 | * If this varies between SoCs later, move to tegraNN-common.h | |
39 | * Note: This is number of devices, not max device ID. | |
40 | */ | |
41 | #define CONFIG_SYS_MMC_MAX_DEVICE 4 | |
42 | ||
f01b631f TW |
43 | /* |
44 | * select serial console configuration | |
45 | */ | |
46 | #define CONFIG_CONS_INDEX 1 | |
47 | ||
48 | /* allow to overwrite serial and ethaddr */ | |
49 | #define CONFIG_ENV_OVERWRITE | |
f01b631f | 50 | |
f01b631f | 51 | /* turn on command-line edit/hist/auto */ |
f01b631f | 52 | |
f01b631f TW |
53 | /* |
54 | * Increasing the size of the IO buffer as default nfsargs size is more | |
55 | * than 256 and so it is not possible to edit it | |
56 | */ | |
64a4fe74 | 57 | #define CONFIG_SYS_CBSIZE (1024 * 2) /* Console I/O Buffer Size */ |
f01b631f | 58 | /* Print Buffer Size */ |
64a4fe74 BW |
59 | #define CONFIG_SYS_MAXARGS 64 /* max number of command args */ |
60 | ||
f01b631f TW |
61 | /* Boot Argument Buffer Size */ |
62 | #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) | |
63 | ||
64 | #define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000) | |
65 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000) | |
66 | ||
f01b631f TW |
67 | /*----------------------------------------------------------------------- |
68 | * Physical Memory Map | |
69 | */ | |
bbc1b99e | 70 | #define CONFIG_NR_DRAM_BANKS 2 |
f01b631f TW |
71 | #define PHYS_SDRAM_1 NV_PA_SDRC_CS0 |
72 | #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */ | |
73 | ||
74 | #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE | |
75 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 | |
76 | ||
77 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ | |
78 | ||
f097532d | 79 | #ifndef CONFIG_ARM64 |
f01b631f TW |
80 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE |
81 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN | |
82 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ | |
83 | CONFIG_SYS_INIT_RAM_SIZE - \ | |
84 | GENERATED_GBL_DATA_SIZE) | |
f097532d | 85 | #endif |
f01b631f | 86 | |
0d1bd150 | 87 | #ifndef CONFIG_ARM64 |
f01b631f | 88 | /* Defines for SPL */ |
6ebc3461 | 89 | #define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_TEXT_BASE - \ |
f01b631f TW |
90 | CONFIG_SPL_TEXT_BASE) |
91 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000 | |
0d1bd150 | 92 | #endif |
f01b631f | 93 | |
a885f852 SW |
94 | /* Misc utility code */ |
95 | #define CONFIG_BOUNCE_BUFFER | |
dd7f65f6 | 96 | |
f01b631f | 97 | #endif /* _TEGRA_COMMON_H_ */ |