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f01b631f TW |
1 | /* |
2 | * (C) Copyright 2010-2012 | |
3 | * NVIDIA Corporation <www.nvidia.com> | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
f01b631f TW |
6 | */ |
7 | ||
bfcf46db TW |
8 | #ifndef _TEGRA_COMMON_H_ |
9 | #define _TEGRA_COMMON_H_ | |
1ace4022 | 10 | #include <linux/sizes.h> |
f01b631f TW |
11 | #include <linux/stringify.h> |
12 | ||
13 | /* | |
14 | * High Level Configuration Options | |
15 | */ | |
16 | #define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */ | |
f01b631f TW |
17 | #define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */ |
18 | ||
f01b631f TW |
19 | #include <asm/arch/tegra.h> /* get chip and board defs */ |
20 | ||
f41f0a19 TR |
21 | /* Use the Tegra US timer on ARMv7, but the architected timer on ARMv8. */ |
22 | #ifndef CONFIG_ARM64 | |
31df9893 RH |
23 | #define CONFIG_SYS_TIMER_RATE 1000000 |
24 | #define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE | |
f41f0a19 | 25 | #endif |
31df9893 | 26 | |
f01b631f TW |
27 | /* |
28 | * Display CPU and Board information | |
29 | */ | |
30 | #define CONFIG_DISPLAY_CPUINFO | |
31 | #define CONFIG_DISPLAY_BOARDINFO | |
32 | ||
33 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ | |
f01b631f TW |
34 | |
35 | /* Environment */ | |
36 | #define CONFIG_ENV_VARS_UBOOT_CONFIG | |
37 | #define CONFIG_ENV_SIZE 0x2000 /* Total Size Environment */ | |
38 | ||
39 | /* | |
40 | * Size of malloc() pool | |
41 | */ | |
52a7c98a PM |
42 | #ifdef CONFIG_DFU_MMC |
43 | #define CONFIG_SYS_MALLOC_LEN ((4 << 20) + \ | |
44 | CONFIG_SYS_DFU_DATA_BUF_SIZE) | |
45 | #else | |
f01b631f | 46 | #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */ |
52a7c98a | 47 | #endif |
d1e5b406 | 48 | |
6527268d | 49 | #ifndef CONFIG_ARM64 |
d1e5b406 | 50 | #define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */ |
6527268d | 51 | #endif |
f01b631f TW |
52 | |
53 | /* | |
bfcf46db | 54 | * NS16550 Configuration |
f01b631f | 55 | */ |
858530a8 | 56 | #define CONFIG_TEGRA_SERIAL |
858530a8 | 57 | #define CONFIG_SYS_NS16550 |
f01b631f | 58 | |
f175603f SW |
59 | /* |
60 | * Common HW configuration. | |
61 | * If this varies between SoCs later, move to tegraNN-common.h | |
62 | * Note: This is number of devices, not max device ID. | |
63 | */ | |
64 | #define CONFIG_SYS_MMC_MAX_DEVICE 4 | |
65 | ||
f01b631f TW |
66 | /* |
67 | * select serial console configuration | |
68 | */ | |
69 | #define CONFIG_CONS_INDEX 1 | |
70 | ||
71 | /* allow to overwrite serial and ethaddr */ | |
72 | #define CONFIG_ENV_OVERWRITE | |
73 | #define CONFIG_BAUDRATE 115200 | |
74 | ||
f01b631f | 75 | /* turn on command-line edit/hist/auto */ |
f01b631f | 76 | #define CONFIG_COMMAND_HISTORY |
f01b631f | 77 | |
11d9c030 | 78 | /* turn on commonly used storage-related commands */ |
11d9c030 | 79 | #define CONFIG_PARTITION_UUIDS |
11d9c030 SW |
80 | #define CONFIG_CMD_PART |
81 | ||
f01b631f TW |
82 | #define CONFIG_SYS_NO_FLASH |
83 | ||
84 | #define CONFIG_CONSOLE_MUX | |
85 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV | |
86bd20b0 SW |
86 | #ifndef CONFIG_SPL_BUILD |
87 | #define CONFIG_SYS_STDIO_DEREGISTER | |
88 | #endif | |
f01b631f | 89 | |
f01b631f TW |
90 | /* |
91 | * Increasing the size of the IO buffer as default nfsargs size is more | |
92 | * than 256 and so it is not possible to edit it | |
93 | */ | |
94 | #define CONFIG_SYS_CBSIZE (256 * 2) /* Console I/O Buffer Size */ | |
95 | /* Print Buffer Size */ | |
96 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
97 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
0859b49d | 98 | #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ |
f01b631f TW |
99 | /* Boot Argument Buffer Size */ |
100 | #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) | |
101 | ||
102 | #define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000) | |
103 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000) | |
104 | ||
6527268d | 105 | #ifndef CONFIG_ARM64 |
9dacbb27 | 106 | #ifndef CONFIG_SPL_BUILD |
4270d5af | 107 | #define CONFIG_USE_ARCH_MEMCPY |
9dacbb27 | 108 | #endif |
6527268d | 109 | #endif |
4270d5af | 110 | |
f01b631f TW |
111 | /*----------------------------------------------------------------------- |
112 | * Physical Memory Map | |
113 | */ | |
114 | #define CONFIG_NR_DRAM_BANKS 1 | |
115 | #define PHYS_SDRAM_1 NV_PA_SDRC_CS0 | |
116 | #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */ | |
117 | ||
118 | #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE | |
119 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 | |
120 | ||
121 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ | |
122 | ||
123 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE | |
124 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN | |
125 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ | |
126 | CONFIG_SYS_INIT_RAM_SIZE - \ | |
127 | GENERATED_GBL_DATA_SIZE) | |
128 | ||
129 | #define CONFIG_TEGRA_GPIO | |
130 | #define CONFIG_CMD_GPIO | |
131 | #define CONFIG_CMD_ENTERRCM | |
f01b631f TW |
132 | |
133 | /* Defines for SPL */ | |
f01b631f TW |
134 | #define CONFIG_SPL_FRAMEWORK |
135 | #define CONFIG_SPL_RAM_DEVICE | |
136 | #define CONFIG_SPL_BOARD_INIT | |
137 | #define CONFIG_SPL_NAND_SIMPLE | |
6ebc3461 | 138 | #define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_TEXT_BASE - \ |
f01b631f TW |
139 | CONFIG_SPL_TEXT_BASE) |
140 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000 | |
141 | ||
142 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | |
143 | #define CONFIG_SPL_LIBGENERIC_SUPPORT | |
144 | #define CONFIG_SPL_SERIAL_SUPPORT | |
145 | #define CONFIG_SPL_GPIO_SUPPORT | |
146 | ||
dd7f65f6 | 147 | #define CONFIG_SYS_GENERIC_BOARD |
026baff7 SW |
148 | #define CONFIG_BOARD_EARLY_INIT_F |
149 | #define CONFIG_BOARD_LATE_INIT | |
3efff99f | 150 | |
a885f852 SW |
151 | /* Misc utility code */ |
152 | #define CONFIG_BOUNCE_BUFFER | |
3efff99f | 153 | #define CONFIG_CRC32_VERIFY |
dd7f65f6 | 154 | |
68cf64db SW |
155 | #ifndef CONFIG_SPL_BUILD |
156 | #include <config_distro_defaults.h> | |
157 | #endif | |
158 | ||
f01b631f | 159 | #endif /* _TEGRA_COMMON_H_ */ |