[people/ms/u-boot.git] / include / configs / vexpress_aemv8a.h

/*
 * Configuration for Versatile Express. Parts were derived from other ARM
 *   configurations.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __VEXPRESS_AEMV8A_H
#define __VEXPRESS_AEMV8A_H

/* We use generic board and device manager for v8 Versatile Express */
#define CONFIG_SYS_GENERIC_BOARD

#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
#ifndef CONFIG_SEMIHOSTING
#error CONFIG_TARGET_VEXPRESS64_BASE_FVP requires CONFIG_SEMIHOSTING
#endif
#define CONFIG_ARMV8_SWITCH_TO_EL1
#endif

#define CONFIG_REMAKE_ELF

#define CONFIG_SUPPORT_RAW_INITRD

/* Cache Definitions */
#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_SYS_ICACHE_OFF

#define CONFIG_IDENT_STRING		" vexpress_aemv8a"
#define CONFIG_BOOTP_VCI_STRING		"U-boot.armv8.vexpress_aemv8a"

/* Link Definitions */
#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
/* ATF loads u-boot here for BASE_FVP model */
#define CONFIG_SYS_TEXT_BASE		0x88000000
#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
#elif CONFIG_TARGET_VEXPRESS64_JUNO
#define CONFIG_SYS_TEXT_BASE		0xe0000000
#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
#else
#error "Unknown board variant"
#endif

/* Flat Device Tree Definitions */
#define CONFIG_OF_LIBFDT

/* CS register bases for the original memory map. */
#define V2M_PA_CS0			0x00000000
#define V2M_PA_CS1			0x14000000
#define V2M_PA_CS2			0x18000000
#define V2M_PA_CS3			0x1c000000
#define V2M_PA_CS4			0x0c000000
#define V2M_PA_CS5			0x10000000

#define V2M_PERIPH_OFFSET(x)		(x << 16)
#define V2M_SYSREGS			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(1))
#define V2M_SYSCTL			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(2))
#define V2M_SERIAL_BUS_PCI		(V2M_PA_CS3 + V2M_PERIPH_OFFSET(3))

#define V2M_BASE			0x80000000

/* Common peripherals relative to CS7. */
#define V2M_AACI			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(4))
#define V2M_MMCI			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(5))
#define V2M_KMI0			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(6))
#define V2M_KMI1			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(7))

#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
#define V2M_UART0			0x7ff80000
#define V2M_UART1			0x7ff70000
#else /* Not Juno */
#define V2M_UART0			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(9))
#define V2M_UART1			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(10))
#define V2M_UART2			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(11))
#define V2M_UART3			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(12))
#endif

#define V2M_WDT				(V2M_PA_CS3 + V2M_PERIPH_OFFSET(15))

#define V2M_TIMER01			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(17))
#define V2M_TIMER23			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(18))

#define V2M_SERIAL_BUS_DVI		(V2M_PA_CS3 + V2M_PERIPH_OFFSET(22))
#define V2M_RTC				(V2M_PA_CS3 + V2M_PERIPH_OFFSET(23))

#define V2M_CF				(V2M_PA_CS3 + V2M_PERIPH_OFFSET(26))

#define V2M_CLCD			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(31))

/* System register offsets. */
#define V2M_SYS_CFGDATA			(V2M_SYSREGS + 0x0a0)
#define V2M_SYS_CFGCTRL			(V2M_SYSREGS + 0x0a4)
#define V2M_SYS_CFGSTAT			(V2M_SYSREGS + 0x0a8)

/* Generic Timer Definitions */
#define COUNTER_FREQUENCY		(0x1800000)	/* 24MHz */

/* Generic Interrupt Controller Definitions */
#ifdef CONFIG_GICV3
#define GICD_BASE			(0x2f000000)
#define GICR_BASE			(0x2f100000)
#else

#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
#define GICD_BASE			(0x2f000000)
#define GICC_BASE			(0x2c000000)
#elif CONFIG_TARGET_VEXPRESS64_JUNO
#define GICD_BASE			(0x2C010000)
#define GICC_BASE			(0x2C02f000)
#else
#error "Unknown board variant"
#endif
#endif /* !CONFIG_GICV3 */

/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (8 << 20))

/* Ethernet Configuration */
#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
/* The real hardware Versatile express uses SMSC9118 */
#define CONFIG_SMC911X			1
#define CONFIG_SMC911X_32_BIT		1
#define CONFIG_SMC911X_BASE		(0x018000000)
#else
/* The Vexpress64 simulators use SMSC91C111 */
#define CONFIG_SMC91111			1
#define CONFIG_SMC91111_BASE		(0x01A000000)
#endif

/* PL011 Serial Configuration */
#define CONFIG_BAUDRATE			115200
#define CONFIG_CONS_INDEX		0
#define CONFIG_PL01X_SERIAL
#define CONFIG_PL011_SERIAL
#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
#define CONFIG_PL011_CLOCK		7273800
#else
#define CONFIG_PL011_CLOCK		24000000
#endif

/* Command line configuration */
#define CONFIG_MENU
/*#define CONFIG_MENU_SHOW*/
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_BOOTI
#define CONFIG_CMD_UNZIP
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PXE
#define CONFIG_CMD_ENV
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION

/* BOOTP options */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_PXE
#define CONFIG_BOOTP_PXE_CLIENTARCH	0x100

/* Miscellaneous configurable options */
#define CONFIG_SYS_LOAD_ADDR		(V2M_BASE + 0x10000000)

/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS		1
#define PHYS_SDRAM_1			(V2M_BASE)	/* SDRAM Bank #1 */
/* Top 16MB reserved for secure world use */
#define DRAM_SEC_SIZE		0x01000000
#define PHYS_SDRAM_1_SIZE	0x80000000 - DRAM_SEC_SIZE
#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_1

/* Enable memtest */
#define CONFIG_CMD_MEMTEST
#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)

/* Initial environment variables */
#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
/*
 * Defines where the kernel and FDT exist in NOR flash and where it will
 * be copied into DRAM
 */
#define CONFIG_EXTRA_ENV_SETTINGS	\
				"kernel_name=Image\0"	\
				"kernel_addr=0x80000000\0" \
				"fdt_name=juno\0" \
				"fdt_addr=0x83000000\0" \
				"fdt_high=0xffffffffffffffff\0" \
				"initrd_high=0xffffffffffffffff\0" \

/* Assume we boot with root on the first partition of a USB stick */
#define CONFIG_BOOTARGS		"console=ttyAMA0,115200n8 " \
				"root=/dev/sda1 rw " \
				"rootwait "\
				"earlyprintk=pl011,0x7ff80000 debug "\
				"user_debug=31 "\
				"loglevel=9"

/* Copy the kernel and FDT to DRAM memory and boot */
#define CONFIG_BOOTCOMMAND	"afs load ${kernel_name} ${kernel_addr} ; " \
				"afs load  ${fdt_name} ${fdt_addr} ; " \
				"fdt addr ${fdt_addr}; fdt resize; " \
				"booti ${kernel_addr} - ${fdt_addr}"

#define CONFIG_BOOTDELAY		1

#elif CONFIG_TARGET_VEXPRESS64_BASE_FVP
#define CONFIG_EXTRA_ENV_SETTINGS	\
				"kernel_name=Image\0"		\
				"kernel_addr=0x80000000\0"	\
				"initrd_name=ramdisk.img\0"	\
				"initrd_addr=0x88000000\0"	\
				"fdt_name=devtree.dtb\0"	\
				"fdt_addr=0x83000000\0"		\
				"fdt_high=0xffffffffffffffff\0"	\
				"initrd_high=0xffffffffffffffff\0"

#define CONFIG_BOOTARGS		"console=ttyAMA0 earlyprintk=pl011,"\
				"0x1c090000 debug user_debug=31 "\
				"loglevel=9"

#define CONFIG_BOOTCOMMAND	"smhload ${kernel_name} ${kernel_addr}; " \
				"smhload ${fdt_name} ${fdt_addr}; " \
				"smhload ${initrd_name} ${initrd_addr} "\
				"initrd_end; " \
				"fdt addr ${fdt_addr}; fdt resize; " \
				"fdt chosen ${initrd_addr} ${initrd_end}; " \
				"booti $kernel_addr - $fdt_addr"

#define CONFIG_BOOTDELAY		1

#else
#error "Unknown board variant"
#endif

/* Do not preserve environment */
#define CONFIG_ENV_IS_NOWHERE		1
#define CONFIG_ENV_SIZE			0x1000

/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_MAXARGS		64	/* max command args */

/* Flash memory is available on the Juno board only */
#ifndef CONFIG_TARGET_VEXPRESS64_JUNO
#define CONFIG_SYS_NO_FLASH
#else
#define CONFIG_CMD_ARMFLASH
#define CONFIG_SYS_FLASH_CFI		1
#define CONFIG_FLASH_CFI_DRIVER		1
#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_32BIT
#define CONFIG_SYS_FLASH_BASE		0x08000000
#define CONFIG_SYS_FLASH_SIZE		0x04000000 /* 64 MiB */
#define CONFIG_SYS_MAX_FLASH_BANKS	2

/* Timeout values in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(2 * CONFIG_SYS_HZ) /* Erase Timeout */
#define CONFIG_SYS_FLASH_WRITE_TOUT	(2 * CONFIG_SYS_HZ) /* Write Timeout */

/* 255 0x40000 sectors + first or last sector may have 4 erase regions = 259 */
#define CONFIG_SYS_MAX_FLASH_SECT	259		/* Max sectors */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */
#define CONFIG_SYS_FLASH_PROTECTION	/* The devices have real protection */
#define CONFIG_SYS_FLASH_EMPTY_INFO	/* flinfo indicates empty blocks */

#endif

#endif /* __VEXPRESS_AEMV8A_H */
Commit	Line	Data
12916829 DF	1	/*
	2	* Configuration for Versatile Express. Parts were derived from other ARM
	3	* configurations.
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#ifndef __VEXPRESS_AEMV8A_H
	9	#define __VEXPRESS_AEMV8A_H
	10
d280ea00	11	/* We use generic board and device manager for v8 Versatile Express */
03ca6a39 LW	12	#define CONFIG_SYS_GENERIC_BOARD
03ca6a39 LW	13
f91afc4d	14	#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
261d2760	15	#ifndef CONFIG_SEMIHOSTING
f91afc4d	16	#error CONFIG_TARGET_VEXPRESS64_BASE_FVP requires CONFIG_SEMIHOSTING
261d2760	17	#endif
261d2760 DR	18	#define CONFIG_ARMV8_SWITCH_TO_EL1
	19	#endif
	20
12916829 DF	21	#define CONFIG_REMAKE_ELF
12916829 DF	22
12916829 DF	23	#define CONFIG_SUPPORT_RAW_INITRD
	24
	25	/* Cache Definitions */
	26	#define CONFIG_SYS_DCACHE_OFF
	27	#define CONFIG_SYS_ICACHE_OFF
	28
	29	#define CONFIG_IDENT_STRING " vexpress_aemv8a"
	30	#define CONFIG_BOOTP_VCI_STRING "U-boot.armv8.vexpress_aemv8a"
	31
	32	/* Link Definitions */
f91afc4d	33	#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
261d2760 DR	34	/* ATF loads u-boot here for BASE_FVP model */
	35	#define CONFIG_SYS_TEXT_BASE 0x88000000
	36	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
ffc10373 LW	37	#elif CONFIG_TARGET_VEXPRESS64_JUNO
	38	#define CONFIG_SYS_TEXT_BASE 0xe0000000
	39	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
261d2760	40	#else
03314f0e	41	#error "Unknown board variant"
261d2760	42	#endif
12916829 DF	43
	44	/* Flat Device Tree Definitions */
	45	#define CONFIG_OF_LIBFDT
	46
12916829 DF	47	/* CS register bases for the original memory map. */
	48	#define V2M_PA_CS0 0x00000000
	49	#define V2M_PA_CS1 0x14000000
	50	#define V2M_PA_CS2 0x18000000
	51	#define V2M_PA_CS3 0x1c000000
	52	#define V2M_PA_CS4 0x0c000000
	53	#define V2M_PA_CS5 0x10000000
	54
	55	#define V2M_PERIPH_OFFSET(x) (x << 16)
	56	#define V2M_SYSREGS (V2M_PA_CS3 + V2M_PERIPH_OFFSET(1))
	57	#define V2M_SYSCTL (V2M_PA_CS3 + V2M_PERIPH_OFFSET(2))
	58	#define V2M_SERIAL_BUS_PCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(3))
	59
	60	#define V2M_BASE 0x80000000
	61
12916829 DF	62	/* Common peripherals relative to CS7. */
	63	#define V2M_AACI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4))
	64	#define V2M_MMCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5))
	65	#define V2M_KMI0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(6))
	66	#define V2M_KMI1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(7))
	67
ffc10373 LW	68	#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
	69	#define V2M_UART0 0x7ff80000
	70	#define V2M_UART1 0x7ff70000
	71	#else /* Not Juno */
12916829 DF	72	#define V2M_UART0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(9))
	73	#define V2M_UART1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(10))
	74	#define V2M_UART2 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(11))
	75	#define V2M_UART3 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(12))
ffc10373	76	#endif
12916829 DF	77
	78	#define V2M_WDT (V2M_PA_CS3 + V2M_PERIPH_OFFSET(15))
	79
	80	#define V2M_TIMER01 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(17))
	81	#define V2M_TIMER23 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(18))
	82
	83	#define V2M_SERIAL_BUS_DVI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(22))
	84	#define V2M_RTC (V2M_PA_CS3 + V2M_PERIPH_OFFSET(23))
	85
	86	#define V2M_CF (V2M_PA_CS3 + V2M_PERIPH_OFFSET(26))
	87
	88	#define V2M_CLCD (V2M_PA_CS3 + V2M_PERIPH_OFFSET(31))
	89
	90	/* System register offsets. */
	91	#define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0)
	92	#define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4)
	93	#define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8)
	94
	95	/* Generic Timer Definitions */
	96	#define COUNTER_FREQUENCY (0x1800000) /* 24MHz */
	97
	98	/* Generic Interrupt Controller Definitions */
c71645ad DF	99	#ifdef CONFIG_GICV3
	100	#define GICD_BASE (0x2f000000)
	101	#define GICR_BASE (0x2f100000)
	102	#else
261d2760	103
f91afc4d	104	#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
261d2760 DR	105	#define GICD_BASE (0x2f000000)
261d2760 DR	106	#define GICC_BASE (0x2c000000)
ffc10373 LW	107	#elif CONFIG_TARGET_VEXPRESS64_JUNO
	108	#define GICD_BASE (0x2C010000)
	109	#define GICC_BASE (0x2C02f000)
261d2760	110	#else
03314f0e	111	#error "Unknown board variant"
261d2760	112	#endif
03314f0e	113	#endif /* !CONFIG_GICV3 */
12916829	114
12916829	115	/* Size of malloc() pool */
5bcae13e	116	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20))
12916829	117
b31f9d7a LW	118	/* Ethernet Configuration */
	119	#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
	120	/* The real hardware Versatile express uses SMSC9118 */
	121	#define CONFIG_SMC911X 1
	122	#define CONFIG_SMC911X_32_BIT 1
	123	#define CONFIG_SMC911X_BASE (0x018000000)
	124	#else
	125	/* The Vexpress64 simulators use SMSC91C111 */
3865ceb7 BS	126	#define CONFIG_SMC91111 1
3865ceb7 BS	127	#define CONFIG_SMC91111_BASE (0x01A000000)
b31f9d7a	128	#endif
12916829 DF	129
12916829 DF	130	/* PL011 Serial Configuration */
d280ea00	131	#define CONFIG_BAUDRATE 115200
d8bafe13	132	#define CONFIG_CONS_INDEX 0
d280ea00	133	#define CONFIG_PL01X_SERIAL
12916829	134	#define CONFIG_PL011_SERIAL
ffc10373 LW	135	#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
	136	#define CONFIG_PL011_CLOCK 7273800
	137	#else
12916829	138	#define CONFIG_PL011_CLOCK 24000000
ffc10373	139	#endif
12916829 DF	140
	141	/* Command line configuration */
	142	#define CONFIG_MENU
	143	/#define CONFIG_MENU_SHOW/
	144	#define CONFIG_CMD_CACHE
67172528 TR	145	#define CONFIG_CMD_BOOTI
67172528 TR	146	#define CONFIG_CMD_UNZIP
12916829 DF	147	#define CONFIG_CMD_DHCP
	148	#define CONFIG_CMD_PXE
	149	#define CONFIG_CMD_ENV
12916829	150	#define CONFIG_CMD_MII
12916829	151	#define CONFIG_CMD_PING
12916829 DF	152	#define CONFIG_CMD_FAT
	153	#define CONFIG_DOS_PARTITION
	154
	155	/* BOOTP options */
	156	#define CONFIG_BOOTP_BOOTFILESIZE
	157	#define CONFIG_BOOTP_BOOTPATH
	158	#define CONFIG_BOOTP_GATEWAY
	159	#define CONFIG_BOOTP_HOSTNAME
	160	#define CONFIG_BOOTP_PXE
	161	#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100
	162
	163	/* Miscellaneous configurable options */
	164	#define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x10000000)
	165
	166	/* Physical Memory Map */
	167	#define CONFIG_NR_DRAM_BANKS 1
	168	#define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */
30355708 LW	169	/* Top 16MB reserved for secure world use */
	170	#define DRAM_SEC_SIZE 0x01000000
	171	#define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE
	172	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	173
	174	/* Enable memtest */
	175	#define CONFIG_CMD_MEMTEST
	176	#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
	177	#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
12916829 DF	178
12916829 DF	179	/* Initial environment variables */
10d1491b LW	180	#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
	181	/*
	182	* Defines where the kernel and FDT exist in NOR flash and where it will
	183	* be copied into DRAM
	184	*/
	185	#define CONFIG_EXTRA_ENV_SETTINGS \
	186	"kernel_name=Image\0" \
	187	"kernel_addr=0x80000000\0" \
	188	"fdt_name=juno\0" \
	189	"fdt_addr=0x83000000\0" \
	190	"fdt_high=0xffffffffffffffff\0" \
	191	"initrd_high=0xffffffffffffffff\0" \
	192
	193	/* Assume we boot with root on the first partition of a USB stick */
	194	#define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 " \
	195	"root=/dev/sda1 rw " \
33665f7c	196	"rootwait "\
c0ae9703 RH	197	"earlyprintk=pl011,0x7ff80000 debug "\
c0ae9703 RH	198	"user_debug=31 "\
10d1491b LW	199	"loglevel=9"
	200
	201	/* Copy the kernel and FDT to DRAM memory and boot */
	202	#define CONFIG_BOOTCOMMAND "afs load ${kernel_name} ${kernel_addr} ; " \
	203	"afs load ${fdt_name} ${fdt_addr} ; " \
	204	"fdt addr ${fdt_addr}; fdt resize; " \
	205	"booti ${kernel_addr} - ${fdt_addr}"
	206
	207	#define CONFIG_BOOTDELAY 1
	208
	209	#elif CONFIG_TARGET_VEXPRESS64_BASE_FVP
261d2760	210	#define CONFIG_EXTRA_ENV_SETTINGS \
1fd0f92e	211	"kernel_name=Image\0" \
49995ffe	212	"kernel_addr=0x80000000\0" \
261d2760	213	"initrd_name=ramdisk.img\0" \
49995ffe LW	214	"initrd_addr=0x88000000\0" \
	215	"fdt_name=devtree.dtb\0" \
	216	"fdt_addr=0x83000000\0" \
261d2760 DR	217	"fdt_high=0xffffffffffffffff\0" \
	218	"initrd_high=0xffffffffffffffff\0"
	219
	220	#define CONFIG_BOOTARGS "console=ttyAMA0 earlyprintk=pl011,"\
	221	"0x1c090000 debug user_debug=31 "\
	222	"loglevel=9"
	223
49995ffe	224	#define CONFIG_BOOTCOMMAND "smhload ${kernel_name} ${kernel_addr}; " \
1fd0f92e	225	"smhload ${fdt_name} ${fdt_addr}; " \
c0ae9703 RH	226	"smhload ${initrd_name} ${initrd_addr} "\
c0ae9703 RH	227	"initrd_end; " \
1fd0f92e LW	228	"fdt addr ${fdt_addr}; fdt resize; " \
	229	"fdt chosen ${initrd_addr} ${initrd_end}; " \
	230	"booti $kernel_addr - $fdt_addr"
261d2760 DR	231
	232	#define CONFIG_BOOTDELAY 1
	233
	234	#else
03314f0e	235	#error "Unknown board variant"
261d2760	236	#endif
12916829 DF	237
	238	/* Do not preserve environment */
	239	#define CONFIG_ENV_IS_NOWHERE 1
	240	#define CONFIG_ENV_SIZE 0x1000
	241
	242	/* Monitor Command Prompt */
	243	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
12916829 DF	244	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	245	sizeof(CONFIG_SYS_PROMPT) + 16)
	246	#define CONFIG_SYS_HUSH_PARSER
12916829 DF	247	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
12916829 DF	248	#define CONFIG_SYS_LONGHELP
5bcae13e	249	#define CONFIG_CMDLINE_EDITING
12916829 DF	250	#define CONFIG_SYS_MAXARGS 64 /* max command args */
12916829 DF	251
14f264e6 LW	252	/* Flash memory is available on the Juno board only */
	253	#ifndef CONFIG_TARGET_VEXPRESS64_JUNO
	254	#define CONFIG_SYS_NO_FLASH
	255	#else
10d1491b	256	#define CONFIG_CMD_ARMFLASH
14f264e6 LW	257	#define CONFIG_SYS_FLASH_CFI 1
14f264e6 LW	258	#define CONFIG_FLASH_CFI_DRIVER 1
f19f389f	259	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
14f264e6 LW	260	#define CONFIG_SYS_FLASH_BASE 0x08000000
	261	#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MiB */
	262	#define CONFIG_SYS_MAX_FLASH_BANKS 2
	263
	264	/* Timeout values in ticks */
	265	#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */
	266	#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */
	267
	268	/* 255 0x40000 sectors + first or last sector may have 4 erase regions = 259 */
	269	#define CONFIG_SYS_MAX_FLASH_SECT 259 /* Max sectors */
	270	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */
	271	#define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */
	272	#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
	273
	274	#endif
	275
12916829	276	#endif /* __VEXPRESS_AEMV8A_H */