[people/ms/u-boot.git] / include / configs / yosemite.h

/*
 * (C) Copyright 2005-2007
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/************************************************************************
 * yosemite.h - configuration for Yosemite & Yellowstone boards
 ***********************************************************************/
#ifndef __CONFIG_H
#define __CONFIG_H

/*-----------------------------------------------------------------------
 * High Level Configuration Options
 *----------------------------------------------------------------------*/
/* This config file is used for Yosemite (440EP) and Yellowstone (440GR)*/
#ifndef CONFIG_YELLOWSTONE
#define CONFIG_440EP		1	/* Specific PPC440EP support	*/
#define CONFIG_HOSTNAME		yosemite
#else
#define CONFIG_440GR		1	/* Specific PPC440GR support	*/
#define CONFIG_HOSTNAME		yellowstone
#endif
#define CONFIG_440		1	/* ... PPC440 family		*/
#define CONFIG_SYS_CLK_FREQ	66666666    /* external freq to pll	*/

#define	CONFIG_SYS_TEXT_BASE	0xFFF80000

/*
 * Include common defines/options for all AMCC eval boards
 */
#include "amcc-common.h"

#define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f	*/
#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
#define CONFIG_BOARD_RESET	1	/* call board_reset()		*/

/*-----------------------------------------------------------------------
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_FLASH_BASE	        0xfc000000	    /* start of FLASH	*/
#define CONFIG_SYS_PCI_MEMBASE	        0xa0000000	    /* mapped pci memory*/
#define CONFIG_SYS_PCI_MEMBASE1        CONFIG_SYS_PCI_MEMBASE  + 0x10000000
#define CONFIG_SYS_PCI_MEMBASE2        CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
#define CONFIG_SYS_PCI_MEMBASE3        CONFIG_SYS_PCI_MEMBASE2 + 0x10000000

/*Don't change either of these*/
#define CONFIG_SYS_PCI_BASE	        0xe0000000	    /* internal PCI regs*/
/*Don't change either of these*/

#define CONFIG_SYS_USB_DEVICE          0x50000000
#define CONFIG_SYS_NVRAM_BASE_ADDR     0x80000000
#define CONFIG_SYS_BCSR_BASE	        (CONFIG_SYS_NVRAM_BASE_ADDR | 0x2000)
#define CONFIG_SYS_BOOT_BASE_ADDR      0xf0000000

/*-----------------------------------------------------------------------
 * Initial RAM & stack pointer (placed in SDRAM)
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_INIT_RAM_DCACHE	1		/* d-cache as init ram	*/
#define CONFIG_SYS_INIT_RAM_ADDR	0x70000000		/* DCache       */
#define CONFIG_SYS_INIT_RAM_SIZE	(4 << 10)
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Serial Port
 *----------------------------------------------------------------------*/
#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
#define CONFIG_SYS_EXT_SERIAL_CLOCK	11059200 /* use external 11.059MHz clk	*/

/*-----------------------------------------------------------------------
 * Environment
 *----------------------------------------------------------------------*/
/*
 * Define here the location of the environment variables (FLASH or EEPROM).
 * Note: DENX encourages to use redundant environment in FLASH.
 */
#if 1
#define CONFIG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
#else
#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars	*/
#endif

/*-----------------------------------------------------------------------
 * FLASH related
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_FLASH_CFI				/* The flash is CFI compatible	*/
#define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/
#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1		/* AMD RESET for STM 29W320DB!	*/

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/

#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */

#ifdef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector		*/
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
#endif /* CONFIG_ENV_IS_IN_FLASH */

/*-----------------------------------------------------------------------
 * DDR SDRAM
 *----------------------------------------------------------------------*/
#undef CONFIG_SPD_EEPROM	       /* Don't use SPD EEPROM for setup    */
#define CONFIG_SYS_KBYTES_SDRAM        (128 * 1024)    /* 128MB		    */
#define CONFIG_SYS_SDRAM_BANKS	        (2)

/*-----------------------------------------------------------------------
 * I2C
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000

#define CONFIG_SYS_I2C_EEPROM_ADDR	(0xa8>>1)
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10

#ifdef CONFIG_ENV_IS_IN_EEPROM
#define CONFIG_ENV_SIZE		0x200	    /* Size of Environment vars */
#define CONFIG_ENV_OFFSET		0x0
#endif /* CONFIG_ENV_IS_IN_EEPROM */

/* I2C SYSMON (LM75, AD7414 is almost compatible)			*/
#define CONFIG_DTT_LM75		1		/* ON Semi's LM75	*/
#define CONFIG_DTT_AD7414	1		/* use AD7414		*/
#define CONFIG_DTT_SENSORS	{0}		/* Sensor addresses	*/
#define CONFIG_SYS_DTT_MAX_TEMP	70
#define CONFIG_SYS_DTT_LOW_TEMP	-30
#define CONFIG_SYS_DTT_HYSTERESIS	3

/*
 * Default environment variables
 */
#define	CONFIG_EXTRA_ENV_SETTINGS					\
	CONFIG_AMCC_DEF_ENV						\
	CONFIG_AMCC_DEF_ENV_POWERPC					\
	CONFIG_AMCC_DEF_ENV_PPC_OLD					\
	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
	"kernel_addr=fc000000\0"					\
	"ramdisk_addr=fc180000\0"					\
	""

#define CONFIG_HAS_ETH0		1	/* add support for "ethaddr"	*/
#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
#define CONFIG_PHY_ADDR		1	/* PHY address, See schematics	*/
#define CONFIG_PHY1_ADDR        3

/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION

#ifdef CONFIG_440EP
/* USB */
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_OHCI_BE_CONTROLLER

#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
#define CONFIG_SYS_USB_OHCI_CPU_INIT	1
#define CONFIG_SYS_USB_OHCI_REGS_BASE	(CONFIG_SYS_PERIPHERAL_BASE | 0x1000)
#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"ppc440"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15

/* Comment this out to enable USB 1.1 device */
#define USB_2_0_DEVICE

#define CONFIG_SUPPORT_VFAT
#endif /* CONFIG_440EP */

#ifdef DEBUG
#define CONFIG_PANIC_HANG
#else
#define CONFIG_HW_WATCHDOG			/* watchdog */
#endif

/*
 * Commands additional to the ones defined in amcc-common.h
 */
#define CONFIG_CMD_DTT
#define CONFIG_CMD_PCI

#ifdef CONFIG_440EP
#endif

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
/* General PCI */
#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
#undef  CONFIG_PCI_PNP			/* do (not) pci plug-and-play   */
#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
#define CONFIG_SYS_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/

/* Board-specific PCI */
#define CONFIG_SYS_PCI_TARGET_INIT
#define CONFIG_SYS_PCI_MASTER_INIT

#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
#define CONFIG_SYS_PCI_SUBSYS_ID       0xcafe	/* Whatever */

/*-----------------------------------------------------------------------
 * External Bus Controller (EBC) Setup
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_FLASH		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CPLD		0x80000000

/* Memory Bank 0 (NOR-FLASH) initialization					*/
#define CONFIG_SYS_EBC_PB0AP		0x03017300
#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_FLASH | 0xda000)

/* Memory Bank 2 (CPLD) initialization						*/
#define CONFIG_SYS_EBC_PB2AP		0x04814500
#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_CPLD | 0x18000)

#define CONFIG_SYS_BCSR5_PCI66EN	0x80

#endif	/* __CONFIG_H */
Commit	Line	Data
c157d8e2	1	/*
700200c6	2	* (C) Copyright 2005-2007
84286386	3	* Stefan Roese, DENX Software Engineering, sr@denx.de.
c157d8e2	4	*
3765b3e7	5	* SPDX-License-Identifier: GPL-2.0+
c157d8e2 SR	6	*/
	7
	8	/************************************************************************
700200c6	9	* yosemite.h - configuration for Yosemite & Yellowstone boards
c157d8e2 SR	10	***********************************************************************/
	11	#ifndef __CONFIG_H
	12	#define __CONFIG_H
	13
	14	/*-----------------------------------------------------------------------
	15	* High Level Configuration Options
	16	----------------------------------------------------------------------/
700200c6 SR	17	/* This config file is used for Yosemite (440EP) and Yellowstone (440GR)*/
700200c6 SR	18	#ifndef CONFIG_YELLOWSTONE
700200c6 SR	19	#define CONFIG_440EP 1 /* Specific PPC440EP support */
	20	#define CONFIG_HOSTNAME yosemite
	21	#else
	22	#define CONFIG_440GR 1 /* Specific PPC440GR support */
	23	#define CONFIG_HOSTNAME yellowstone
	24	#endif
efa35cf1	25	#define CONFIG_440 1 /* ... PPC440 family */
c157d8e2 SR	26	#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
c157d8e2 SR	27
2ae18241 WD	28	#define CONFIG_SYS_TEXT_BASE 0xFFF80000
2ae18241 WD	29
72675dc6 SR	30	/*
	31	* Include common defines/options for all AMCC eval boards
	32	*/
	33	#include "amcc-common.h"
	34
84286386 SR	35	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
84286386 SR	36	#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
f3443867	37	#define CONFIG_BOARD_RESET 1 /* call board_reset() */
84286386	38
c157d8e2 SR	39	/*-----------------------------------------------------------------------
	40	* Base addresses -- Note these are effective addresses where the
	41	* actual resources get mapped (not physical addresses)
	42	----------------------------------------------------------------------/
6d0f6bcf JCPV	43	#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */
	44	#define CONFIG_SYS_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/
	45	#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
	46	#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
	47	#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
c157d8e2 SR	48
c157d8e2 SR	49	/Don't change either of these/
6d0f6bcf	50	#define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs*/
c157d8e2 SR	51	/Don't change either of these/
c157d8e2 SR	52
6d0f6bcf JCPV	53	#define CONFIG_SYS_USB_DEVICE 0x50000000
	54	#define CONFIG_SYS_NVRAM_BASE_ADDR 0x80000000
	55	#define CONFIG_SYS_BCSR_BASE (CONFIG_SYS_NVRAM_BASE_ADDR \| 0x2000)
	56	#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
c157d8e2 SR	57
	58	/*-----------------------------------------------------------------------
	59	* Initial RAM & stack pointer (placed in SDRAM)
	60	----------------------------------------------------------------------/
6d0f6bcf JCPV	61	#define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */
6d0f6bcf JCPV	62	#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */
553f0982	63	#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
25ddd1fb	64	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	65	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
c157d8e2	66
c157d8e2 SR	67	/*-----------------------------------------------------------------------
	68	* Serial Port
	69	----------------------------------------------------------------------/
550650dd	70	#define CONFIG_CONS_INDEX 1 /* Use UART0 */
6d0f6bcf	71	#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */
c157d8e2	72
c157d8e2	73	/*-----------------------------------------------------------------------
84286386	74	* Environment
c157d8e2	75	----------------------------------------------------------------------/
84286386 SR	76	/*
	77	* Define here the location of the environment variables (FLASH or EEPROM).
	78	* Note: DENX encourages to use redundant environment in FLASH.
	79	*/
	80	#if 1
5a1aceb0	81	#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
84286386	82	#else
bb1f8b4f	83	#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
84286386	84	#endif
c157d8e2 SR	85
	86	/*-----------------------------------------------------------------------
	87	* FLASH related
	88	----------------------------------------------------------------------/
6d0f6bcf	89	#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
00b1883a	90	#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
6d0f6bcf	91	#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */
c157d8e2	92
6d0f6bcf JCPV	93	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
6d0f6bcf JCPV	94	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
c157d8e2	95
6d0f6bcf JCPV	96	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	97	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
c157d8e2	98
6d0f6bcf	99	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
278bc4b3	100
6d0f6bcf	101	#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
84286386	102
5a1aceb0	103	#ifdef CONFIG_ENV_IS_IN_FLASH
0e8d1586	104	#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
6d0f6bcf	105	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
0e8d1586	106	#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
84286386 SR	107
84286386 SR	108	/* Address and size of Redundant Environment Sector */
0e8d1586 JCPV	109	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
0e8d1586 JCPV	110	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
5a1aceb0	111	#endif /* CONFIG_ENV_IS_IN_FLASH */
c157d8e2 SR	112
	113	/*-----------------------------------------------------------------------
	114	* DDR SDRAM
	115	----------------------------------------------------------------------/
095b8a37	116	#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */
6d0f6bcf JCPV	117	#define CONFIG_SYS_KBYTES_SDRAM (128 * 1024) /* 128MB */
6d0f6bcf JCPV	118	#define CONFIG_SYS_SDRAM_BANKS (2)
84286386	119
c157d8e2 SR	120	/*-----------------------------------------------------------------------
	121	* I2C
	122	----------------------------------------------------------------------/
880540de	123	#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
c157d8e2	124
6d0f6bcf JCPV	125	#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
	126	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	127	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	128	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
c157d8e2	129
bb1f8b4f	130	#ifdef CONFIG_ENV_IS_IN_EEPROM
0e8d1586 JCPV	131	#define CONFIG_ENV_SIZE 0x200 /* Size of Environment vars */
0e8d1586 JCPV	132	#define CONFIG_ENV_OFFSET 0x0
bb1f8b4f	133	#endif /* CONFIG_ENV_IS_IN_EEPROM */
84286386	134
a90921f7 SR	135	/* I2C SYSMON (LM75, AD7414 is almost compatible) */
	136	#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
	137	#define CONFIG_DTT_AD7414 1 /* use AD7414 */
	138	#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
6d0f6bcf JCPV	139	#define CONFIG_SYS_DTT_MAX_TEMP 70
	140	#define CONFIG_SYS_DTT_LOW_TEMP -30
	141	#define CONFIG_SYS_DTT_HYSTERESIS 3
a90921f7	142
72675dc6 SR	143	/*
	144	* Default environment variables
	145	*/
84286386	146	#define CONFIG_EXTRA_ENV_SETTINGS \
72675dc6 SR	147	CONFIG_AMCC_DEF_ENV \
	148	CONFIG_AMCC_DEF_ENV_POWERPC \
	149	CONFIG_AMCC_DEF_ENV_PPC_OLD \
	150	CONFIG_AMCC_DEF_ENV_NOR_UPD \
84286386	151	"kernel_addr=fc000000\0" \
56ced709	152	"ramdisk_addr=fc180000\0" \
84286386	153	""
c157d8e2	154
4adb3023	155	#define CONFIG_HAS_ETH0 1 /* add support for "ethaddr" */
c157d8e2 SR	156	#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
c157d8e2 SR	157	#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
72675dc6	158	#define CONFIG_PHY1_ADDR 3
c157d8e2 SR	159
	160	/* Partitions */
	161	#define CONFIG_MAC_PARTITION
	162	#define CONFIG_DOS_PARTITION
	163	#define CONFIG_ISO_PARTITION
	164
846b0dd2	165	#ifdef CONFIG_440EP
c157d8e2	166	/* USB */
7b59b3c7	167	#define CONFIG_USB_OHCI_NEW
6d0f6bcf	168	#define CONFIG_SYS_OHCI_BE_CONTROLLER
c157d8e2	169
6d0f6bcf JCPV	170	#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
	171	#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
	172	#define CONFIG_SYS_USB_OHCI_REGS_BASE (CONFIG_SYS_PERIPHERAL_BASE \| 0x1000)
	173	#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440"
	174	#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
53e336e9	175
700200c6	176	/* Comment this out to enable USB 1.1 device */
c157d8e2	177	#define USB_2_0_DEVICE
700200c6	178
700200c6	179	#define CONFIG_SUPPORT_VFAT
700200c6	180	#endif /* CONFIG_440EP */
c157d8e2 SR	181
	182	#ifdef DEBUG
	183	#define CONFIG_PANIC_HANG
	184	#else
	185	#define CONFIG_HW_WATCHDOG /* watchdog */
	186	#endif
	187
079a136c	188	/*
72675dc6	189	* Commands additional to the ones defined in amcc-common.h
079a136c	190	*/
a90921f7	191	#define CONFIG_CMD_DTT
dca3b3d6	192	#define CONFIG_CMD_PCI
dca3b3d6 JL	193
dca3b3d6 JL	194	#ifdef CONFIG_440EP
dca3b3d6 JL	195	#endif
dca3b3d6 JL	196
c157d8e2 SR	197	/*-----------------------------------------------------------------------
	198	* PCI stuff
	199	*-----------------------------------------------------------------------
	200	*/
	201	/* General PCI */
842033e6	202	#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
84286386 SR	203	#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
84286386 SR	204	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
6d0f6bcf	205	#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
c157d8e2 SR	206
c157d8e2 SR	207	/* Board-specific PCI */
6d0f6bcf JCPV	208	#define CONFIG_SYS_PCI_TARGET_INIT
6d0f6bcf JCPV	209	#define CONFIG_SYS_PCI_MASTER_INIT
c157d8e2	210
6d0f6bcf JCPV	211	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
6d0f6bcf JCPV	212	#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */
c157d8e2	213
36adff36 SR	214	/*-----------------------------------------------------------------------
	215	* External Bus Controller (EBC) Setup
	216	----------------------------------------------------------------------/
6d0f6bcf JCPV	217	#define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE
6d0f6bcf JCPV	218	#define CONFIG_SYS_CPLD 0x80000000
36adff36 SR	219
36adff36 SR	220	/* Memory Bank 0 (NOR-FLASH) initialization */
6d0f6bcf JCPV	221	#define CONFIG_SYS_EBC_PB0AP 0x03017300
6d0f6bcf JCPV	222	#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH \| 0xda000)
36adff36 SR	223
36adff36 SR	224	/* Memory Bank 2 (CPLD) initialization */
6d0f6bcf JCPV	225	#define CONFIG_SYS_EBC_PB2AP 0x04814500
6d0f6bcf JCPV	226	#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_CPLD \| 0x18000)
36adff36	227
6d0f6bcf	228	#define CONFIG_SYS_BCSR5_PCI66EN 0x80
5a5958b7	229
c157d8e2	230	#endif /* __CONFIG_H */