]>
Commit | Line | Data |
---|---|---|
71f95118 | 1 | /* |
4a6ee172 | 2 | * Copyright 2008,2010 Freescale Semiconductor, Inc |
272cc70b AF |
3 | * Andy Fleming |
4 | * | |
5 | * Based (loosely) on the Linux code | |
71f95118 | 6 | * |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
71f95118 WD |
8 | */ |
9 | ||
10 | #ifndef _MMC_H_ | |
11 | #define _MMC_H_ | |
71f95118 | 12 | |
272cc70b | 13 | #include <linux/list.h> |
3697e599 | 14 | #include <linux/sizes.h> |
0d986e61 | 15 | #include <linux/compiler.h> |
07a2d42c | 16 | #include <part.h> |
272cc70b | 17 | |
f99c2efe JJH |
18 | #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) |
19 | #define MMC_SUPPORTS_TUNING | |
20 | #endif | |
21 | #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) | |
22 | #define MMC_SUPPORTS_TUNING | |
23 | #endif | |
24 | ||
4b7cee53 PA |
25 | /* SD/MMC version bits; 8 flags, 8 major, 8 minor, 8 change */ |
26 | #define SD_VERSION_SD (1U << 31) | |
27 | #define MMC_VERSION_MMC (1U << 30) | |
28 | ||
29 | #define MAKE_SDMMC_VERSION(a, b, c) \ | |
30 | ((((u32)(a)) << 16) | ((u32)(b) << 8) | (u32)(c)) | |
31 | #define MAKE_SD_VERSION(a, b, c) \ | |
32 | (SD_VERSION_SD | MAKE_SDMMC_VERSION(a, b, c)) | |
33 | #define MAKE_MMC_VERSION(a, b, c) \ | |
34 | (MMC_VERSION_MMC | MAKE_SDMMC_VERSION(a, b, c)) | |
35 | ||
36 | #define EXTRACT_SDMMC_MAJOR_VERSION(x) \ | |
37 | (((u32)(x) >> 16) & 0xff) | |
38 | #define EXTRACT_SDMMC_MINOR_VERSION(x) \ | |
39 | (((u32)(x) >> 8) & 0xff) | |
40 | #define EXTRACT_SDMMC_CHANGE_VERSION(x) \ | |
41 | ((u32)(x) & 0xff) | |
42 | ||
43 | #define SD_VERSION_3 MAKE_SD_VERSION(3, 0, 0) | |
44 | #define SD_VERSION_2 MAKE_SD_VERSION(2, 0, 0) | |
45 | #define SD_VERSION_1_0 MAKE_SD_VERSION(1, 0, 0) | |
46 | #define SD_VERSION_1_10 MAKE_SD_VERSION(1, 10, 0) | |
47 | ||
48 | #define MMC_VERSION_UNKNOWN MAKE_MMC_VERSION(0, 0, 0) | |
49 | #define MMC_VERSION_1_2 MAKE_MMC_VERSION(1, 2, 0) | |
50 | #define MMC_VERSION_1_4 MAKE_MMC_VERSION(1, 4, 0) | |
51 | #define MMC_VERSION_2_2 MAKE_MMC_VERSION(2, 2, 0) | |
52 | #define MMC_VERSION_3 MAKE_MMC_VERSION(3, 0, 0) | |
53 | #define MMC_VERSION_4 MAKE_MMC_VERSION(4, 0, 0) | |
54 | #define MMC_VERSION_4_1 MAKE_MMC_VERSION(4, 1, 0) | |
55 | #define MMC_VERSION_4_2 MAKE_MMC_VERSION(4, 2, 0) | |
56 | #define MMC_VERSION_4_3 MAKE_MMC_VERSION(4, 3, 0) | |
57 | #define MMC_VERSION_4_41 MAKE_MMC_VERSION(4, 4, 1) | |
58 | #define MMC_VERSION_4_5 MAKE_MMC_VERSION(4, 5, 0) | |
59 | #define MMC_VERSION_5_0 MAKE_MMC_VERSION(5, 0, 0) | |
1a3619cf | 60 | #define MMC_VERSION_5_1 MAKE_MMC_VERSION(5, 1, 0) |
272cc70b | 61 | |
35f9e196 JJH |
62 | #define MMC_CAP(mode) (1 << mode) |
63 | #define MMC_MODE_HS (MMC_CAP(MMC_HS) | MMC_CAP(SD_HS)) | |
64 | #define MMC_MODE_HS_52MHz MMC_CAP(MMC_HS_52) | |
65 | #define MMC_MODE_DDR_52MHz MMC_CAP(MMC_DDR_52) | |
634d4849 | 66 | #define MMC_MODE_HS200 MMC_CAP(MMC_HS_200) |
35f9e196 JJH |
67 | |
68 | #define MMC_MODE_8BIT BIT(30) | |
69 | #define MMC_MODE_4BIT BIT(29) | |
d0c221fe | 70 | #define MMC_MODE_1BIT BIT(28) |
35f9e196 JJH |
71 | #define MMC_MODE_SPI BIT(27) |
72 | ||
62722036 | 73 | |
272cc70b AF |
74 | #define SD_DATA_4BIT 0x00040000 |
75 | ||
4b7cee53 | 76 | #define IS_SD(x) ((x)->version & SD_VERSION_SD) |
3f2da751 | 77 | #define IS_MMC(x) ((x)->version & MMC_VERSION_MMC) |
272cc70b AF |
78 | |
79 | #define MMC_DATA_READ 1 | |
80 | #define MMC_DATA_WRITE 2 | |
81 | ||
341188b9 HS |
82 | #define MMC_CMD_GO_IDLE_STATE 0 |
83 | #define MMC_CMD_SEND_OP_COND 1 | |
84 | #define MMC_CMD_ALL_SEND_CID 2 | |
85 | #define MMC_CMD_SET_RELATIVE_ADDR 3 | |
86 | #define MMC_CMD_SET_DSR 4 | |
272cc70b | 87 | #define MMC_CMD_SWITCH 6 |
341188b9 | 88 | #define MMC_CMD_SELECT_CARD 7 |
272cc70b | 89 | #define MMC_CMD_SEND_EXT_CSD 8 |
341188b9 HS |
90 | #define MMC_CMD_SEND_CSD 9 |
91 | #define MMC_CMD_SEND_CID 10 | |
272cc70b | 92 | #define MMC_CMD_STOP_TRANSMISSION 12 |
341188b9 HS |
93 | #define MMC_CMD_SEND_STATUS 13 |
94 | #define MMC_CMD_SET_BLOCKLEN 16 | |
95 | #define MMC_CMD_READ_SINGLE_BLOCK 17 | |
96 | #define MMC_CMD_READ_MULTIPLE_BLOCK 18 | |
c10b85d6 | 97 | #define MMC_CMD_SEND_TUNING_BLOCK 19 |
634d4849 | 98 | #define MMC_CMD_SEND_TUNING_BLOCK_HS200 21 |
91fdabc6 | 99 | #define MMC_CMD_SET_BLOCK_COUNT 23 |
272cc70b AF |
100 | #define MMC_CMD_WRITE_SINGLE_BLOCK 24 |
101 | #define MMC_CMD_WRITE_MULTIPLE_BLOCK 25 | |
e6f99a56 LW |
102 | #define MMC_CMD_ERASE_GROUP_START 35 |
103 | #define MMC_CMD_ERASE_GROUP_END 36 | |
104 | #define MMC_CMD_ERASE 38 | |
341188b9 | 105 | #define MMC_CMD_APP_CMD 55 |
d52ebf10 TC |
106 | #define MMC_CMD_SPI_READ_OCR 58 |
107 | #define MMC_CMD_SPI_CRC_ON_OFF 59 | |
3690d6d6 A |
108 | #define MMC_CMD_RES_MAN 62 |
109 | ||
110 | #define MMC_CMD62_ARG1 0xefac62ec | |
111 | #define MMC_CMD62_ARG2 0xcbaea7 | |
112 | ||
341188b9 | 113 | |
341188b9 | 114 | #define SD_CMD_SEND_RELATIVE_ADDR 3 |
272cc70b | 115 | #define SD_CMD_SWITCH_FUNC 6 |
341188b9 | 116 | #define SD_CMD_SEND_IF_COND 8 |
f022d36e | 117 | #define SD_CMD_SWITCH_UHS18V 11 |
341188b9 HS |
118 | |
119 | #define SD_CMD_APP_SET_BUS_WIDTH 6 | |
3697e599 | 120 | #define SD_CMD_APP_SD_STATUS 13 |
e6f99a56 LW |
121 | #define SD_CMD_ERASE_WR_BLK_START 32 |
122 | #define SD_CMD_ERASE_WR_BLK_END 33 | |
341188b9 | 123 | #define SD_CMD_APP_SEND_OP_COND 41 |
272cc70b AF |
124 | #define SD_CMD_APP_SEND_SCR 51 |
125 | ||
634d4849 KVA |
126 | static inline bool mmc_is_tuning_cmd(uint cmdidx) |
127 | { | |
c10b85d6 JJH |
128 | if ((cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) || |
129 | (cmdidx == MMC_CMD_SEND_TUNING_BLOCK)) | |
634d4849 KVA |
130 | return true; |
131 | return false; | |
132 | } | |
133 | ||
272cc70b AF |
134 | /* SCR definitions in different words */ |
135 | #define SD_HIGHSPEED_BUSY 0x00020000 | |
136 | #define SD_HIGHSPEED_SUPPORTED 0x00020000 | |
137 | ||
c10b85d6 JJH |
138 | #define UHS_SDR12_BUS_SPEED 0 |
139 | #define HIGH_SPEED_BUS_SPEED 1 | |
140 | #define UHS_SDR25_BUS_SPEED 1 | |
141 | #define UHS_SDR50_BUS_SPEED 2 | |
142 | #define UHS_SDR104_BUS_SPEED 3 | |
143 | #define UHS_DDR50_BUS_SPEED 4 | |
144 | ||
145 | #define SD_MODE_UHS_SDR12 BIT(UHS_SDR12_BUS_SPEED) | |
146 | #define SD_MODE_UHS_SDR25 BIT(UHS_SDR25_BUS_SPEED) | |
147 | #define SD_MODE_UHS_SDR50 BIT(UHS_SDR50_BUS_SPEED) | |
148 | #define SD_MODE_UHS_SDR104 BIT(UHS_SDR104_BUS_SPEED) | |
149 | #define SD_MODE_UHS_DDR50 BIT(UHS_DDR50_BUS_SPEED) | |
150 | ||
abe2c93f TC |
151 | #define OCR_BUSY 0x80000000 |
152 | #define OCR_HCS 0x40000000 | |
c10b85d6 | 153 | #define OCR_S18R 0x1000000 |
31cacbab RR |
154 | #define OCR_VOLTAGE_MASK 0x007FFF80 |
155 | #define OCR_ACCESS_MODE 0x60000000 | |
272cc70b | 156 | |
1aa2d074 EN |
157 | #define MMC_ERASE_ARG 0x00000000 |
158 | #define MMC_SECURE_ERASE_ARG 0x80000000 | |
159 | #define MMC_TRIM_ARG 0x00000001 | |
160 | #define MMC_DISCARD_ARG 0x00000003 | |
161 | #define MMC_SECURE_TRIM1_ARG 0x80000001 | |
162 | #define MMC_SECURE_TRIM2_ARG 0x80008000 | |
e6f99a56 | 163 | |
5d4fc8d9 | 164 | #define MMC_STATUS_MASK (~0x0206BF7F) |
6b2221b0 | 165 | #define MMC_STATUS_SWITCH_ERROR (1 << 7) |
abe2c93f TC |
166 | #define MMC_STATUS_RDY_FOR_DATA (1 << 8) |
167 | #define MMC_STATUS_CURR_STATE (0xf << 9) | |
ed018b21 | 168 | #define MMC_STATUS_ERROR (1 << 19) |
5d4fc8d9 | 169 | |
d617c426 JK |
170 | #define MMC_STATE_PRG (7 << 9) |
171 | ||
272cc70b AF |
172 | #define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */ |
173 | #define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */ | |
174 | #define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */ | |
175 | #define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */ | |
176 | #define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */ | |
177 | #define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */ | |
178 | #define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */ | |
179 | #define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */ | |
180 | #define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */ | |
181 | #define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */ | |
182 | #define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */ | |
183 | #define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */ | |
184 | #define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */ | |
185 | #define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */ | |
186 | #define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */ | |
187 | #define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */ | |
188 | #define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */ | |
189 | ||
190 | #define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */ | |
191 | #define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte | |
192 | addressed by index which are | |
193 | 1 in value field */ | |
194 | #define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte | |
195 | addressed by index, which are | |
196 | 1 in value field */ | |
197 | #define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */ | |
198 | ||
199 | #define SD_SWITCH_CHECK 0 | |
200 | #define SD_SWITCH_SWITCH 1 | |
201 | ||
202 | /* | |
203 | * EXT_CSD fields | |
204 | */ | |
a7f852b6 DSC |
205 | #define EXT_CSD_ENH_START_ADDR 136 /* R/W */ |
206 | #define EXT_CSD_ENH_SIZE_MULT 140 /* R/W */ | |
f866a46d | 207 | #define EXT_CSD_GP_SIZE_MULT 143 /* R/W */ |
d7b29129 | 208 | #define EXT_CSD_PARTITION_SETTING 155 /* R/W */ |
1937e5aa | 209 | #define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */ |
ac9da0e0 | 210 | #define EXT_CSD_MAX_ENH_SIZE_MULT 157 /* R */ |
0560db18 | 211 | #define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */ |
33ace362 | 212 | #define EXT_CSD_RST_N_FUNCTION 162 /* R/W */ |
cd3d4880 | 213 | #define EXT_CSD_BKOPS_EN 163 /* R/W & R/W/E */ |
8dda5b0e DSC |
214 | #define EXT_CSD_WR_REL_PARAM 166 /* R */ |
215 | #define EXT_CSD_WR_REL_SET 167 /* R/W */ | |
f866a46d | 216 | #define EXT_CSD_RPMB_MULT 168 /* RO */ |
0560db18 | 217 | #define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */ |
3690d6d6 | 218 | #define EXT_CSD_BOOT_BUS_WIDTH 177 |
0560db18 LW |
219 | #define EXT_CSD_PART_CONF 179 /* R/W */ |
220 | #define EXT_CSD_BUS_WIDTH 183 /* R/W */ | |
221 | #define EXT_CSD_HS_TIMING 185 /* R/W */ | |
222 | #define EXT_CSD_REV 192 /* RO */ | |
223 | #define EXT_CSD_CARD_TYPE 196 /* RO */ | |
224 | #define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */ | |
f866a46d | 225 | #define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */ |
0560db18 | 226 | #define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */ |
8948ea83 | 227 | #define EXT_CSD_BOOT_MULT 226 /* RO */ |
cd3d4880 | 228 | #define EXT_CSD_BKOPS_SUPPORT 502 /* RO */ |
272cc70b AF |
229 | |
230 | /* | |
231 | * EXT_CSD field definitions | |
232 | */ | |
233 | ||
abe2c93f TC |
234 | #define EXT_CSD_CMD_SET_NORMAL (1 << 0) |
235 | #define EXT_CSD_CMD_SET_SECURE (1 << 1) | |
236 | #define EXT_CSD_CMD_SET_CPSECURE (1 << 2) | |
272cc70b | 237 | |
abe2c93f TC |
238 | #define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */ |
239 | #define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */ | |
d22e3d46 JC |
240 | #define EXT_CSD_CARD_TYPE_DDR_1_8V (1 << 2) |
241 | #define EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3) | |
242 | #define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \ | |
243 | | EXT_CSD_CARD_TYPE_DDR_1_2V) | |
272cc70b | 244 | |
634d4849 KVA |
245 | #define EXT_CSD_CARD_TYPE_HS200_1_8V BIT(4) /* Card can run at 200MHz */ |
246 | /* SDR mode @1.8V I/O */ | |
247 | #define EXT_CSD_CARD_TYPE_HS200_1_2V BIT(5) /* Card can run at 200MHz */ | |
248 | /* SDR mode @1.2V I/O */ | |
249 | #define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \ | |
250 | EXT_CSD_CARD_TYPE_HS200_1_2V) | |
251 | ||
272cc70b AF |
252 | #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ |
253 | #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ | |
254 | #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */ | |
d22e3d46 JC |
255 | #define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */ |
256 | #define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */ | |
3862b854 | 257 | #define EXT_CSD_DDR_FLAG BIT(2) /* Flag for DDR mode */ |
341188b9 | 258 | |
3862b854 JJH |
259 | #define EXT_CSD_TIMING_LEGACY 0 /* no high speed */ |
260 | #define EXT_CSD_TIMING_HS 1 /* HS */ | |
634d4849 KVA |
261 | #define EXT_CSD_TIMING_HS200 2 /* HS200 */ |
262 | ||
3690d6d6 A |
263 | #define EXT_CSD_BOOT_ACK_ENABLE (1 << 6) |
264 | #define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3) | |
265 | #define EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0) | |
266 | #define EXT_CSD_PARTITION_ACCESS_DISABLE (0 << 0) | |
267 | ||
268 | #define EXT_CSD_BOOT_ACK(x) (x << 6) | |
269 | #define EXT_CSD_BOOT_PART_NUM(x) (x << 3) | |
270 | #define EXT_CSD_PARTITION_ACCESS(x) (x << 0) | |
271 | ||
bdb60996 AD |
272 | #define EXT_CSD_EXTRACT_BOOT_ACK(x) (((x) >> 6) & 0x1) |
273 | #define EXT_CSD_EXTRACT_BOOT_PART(x) (((x) >> 3) & 0x7) | |
274 | #define EXT_CSD_EXTRACT_PARTITION_ACCESS(x) ((x) & 0x7) | |
275 | ||
5a99b9de TR |
276 | #define EXT_CSD_BOOT_BUS_WIDTH_MODE(x) (x << 3) |
277 | #define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2) | |
278 | #define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x) | |
3690d6d6 | 279 | |
d7b29129 MN |
280 | #define EXT_CSD_PARTITION_SETTING_COMPLETED (1 << 0) |
281 | ||
c3dbb4f9 DSC |
282 | #define EXT_CSD_ENH_USR (1 << 0) /* user data area is enhanced */ |
283 | #define EXT_CSD_ENH_GP(x) (1 << ((x)+1)) /* GP part (x+1) is enhanced */ | |
284 | ||
8dda5b0e DSC |
285 | #define EXT_CSD_HS_CTRL_REL (1 << 0) /* host controlled WR_REL_SET */ |
286 | ||
287 | #define EXT_CSD_WR_DATA_REL_USR (1 << 0) /* user data area WR_REL */ | |
288 | #define EXT_CSD_WR_DATA_REL_GP(x) (1 << ((x)+1)) /* GP part (x+1) WR_REL */ | |
289 | ||
1de97f98 AF |
290 | #define R1_ILLEGAL_COMMAND (1 << 22) |
291 | #define R1_APP_CMD (1 << 5) | |
292 | ||
272cc70b | 293 | #define MMC_RSP_PRESENT (1 << 0) |
abe2c93f TC |
294 | #define MMC_RSP_136 (1 << 1) /* 136 bit response */ |
295 | #define MMC_RSP_CRC (1 << 2) /* expect valid crc */ | |
296 | #define MMC_RSP_BUSY (1 << 3) /* card may send busy */ | |
297 | #define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */ | |
272cc70b | 298 | |
abe2c93f TC |
299 | #define MMC_RSP_NONE (0) |
300 | #define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) | |
272cc70b AF |
301 | #define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \ |
302 | MMC_RSP_BUSY) | |
abe2c93f TC |
303 | #define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC) |
304 | #define MMC_RSP_R3 (MMC_RSP_PRESENT) | |
305 | #define MMC_RSP_R4 (MMC_RSP_PRESENT) | |
306 | #define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) | |
307 | #define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) | |
308 | #define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) | |
272cc70b | 309 | |
bc897b1d LW |
310 | #define MMCPART_NOAVAILABLE (0xff) |
311 | #define PART_ACCESS_MASK (0x7) | |
312 | #define PART_SUPPORT (0x1) | |
c3dbb4f9 | 313 | #define ENHNCD_SUPPORT (0x2) |
1937e5aa | 314 | #define PART_ENH_ATTRIB (0x1f) |
71f95118 | 315 | |
83dc4227 KVA |
316 | #define MMC_QUIRK_RETRY_SEND_CID BIT(0) |
317 | #define MMC_QUIRK_RETRY_SET_BLOCKLEN BIT(1) | |
318 | ||
aff5d3c8 KVA |
319 | enum mmc_voltage { |
320 | MMC_SIGNAL_VOLTAGE_000 = 0, | |
bc1e3272 JJH |
321 | MMC_SIGNAL_VOLTAGE_120 = 1, |
322 | MMC_SIGNAL_VOLTAGE_180 = 2, | |
323 | MMC_SIGNAL_VOLTAGE_330 = 4, | |
aff5d3c8 KVA |
324 | }; |
325 | ||
bc1e3272 JJH |
326 | #define MMC_ALL_SIGNAL_VOLTAGE (MMC_SIGNAL_VOLTAGE_120 |\ |
327 | MMC_SIGNAL_VOLTAGE_180 |\ | |
328 | MMC_SIGNAL_VOLTAGE_330) | |
329 | ||
8bfa195e SG |
330 | /* Maximum block size for MMC */ |
331 | #define MMC_MAX_BLOCK_LEN 512 | |
332 | ||
3690d6d6 A |
333 | /* The number of MMC physical partitions. These consist of: |
334 | * boot partitions (2), general purpose partitions (4) in MMC v4.4. | |
335 | */ | |
336 | #define MMC_NUM_BOOT_PARTITION 2 | |
91fdabc6 | 337 | #define MMC_PART_RPMB 3 /* RPMB partition number */ |
3690d6d6 | 338 | |
e7ecf7cb SG |
339 | /* Driver model support */ |
340 | ||
341 | /** | |
342 | * struct mmc_uclass_priv - Holds information about a device used by the uclass | |
343 | */ | |
344 | struct mmc_uclass_priv { | |
345 | struct mmc *mmc; | |
346 | }; | |
347 | ||
348 | /** | |
349 | * mmc_get_mmc_dev() - get the MMC struct pointer for a device | |
350 | * | |
351 | * Provided that the device is already probed and ready for use, this value | |
352 | * will be available. | |
353 | * | |
354 | * @dev: Device | |
355 | * @return associated mmc struct pointer if available, else NULL | |
356 | */ | |
357 | struct mmc *mmc_get_mmc_dev(struct udevice *dev); | |
358 | ||
359 | /* End of driver model support */ | |
360 | ||
1de97f98 AF |
361 | struct mmc_cid { |
362 | unsigned long psn; | |
363 | unsigned short oid; | |
364 | unsigned char mid; | |
365 | unsigned char prv; | |
366 | unsigned char mdt; | |
367 | char pnm[7]; | |
368 | }; | |
369 | ||
272cc70b AF |
370 | struct mmc_cmd { |
371 | ushort cmdidx; | |
372 | uint resp_type; | |
373 | uint cmdarg; | |
0b453ffe | 374 | uint response[4]; |
272cc70b AF |
375 | }; |
376 | ||
377 | struct mmc_data { | |
378 | union { | |
379 | char *dest; | |
380 | const char *src; /* src buffers don't get written to */ | |
381 | }; | |
382 | uint flags; | |
383 | uint blocks; | |
384 | uint blocksize; | |
385 | }; | |
386 | ||
ab769f22 PA |
387 | /* forward decl. */ |
388 | struct mmc; | |
389 | ||
e7881d85 | 390 | #if CONFIG_IS_ENABLED(DM_MMC) |
8ca51e51 SG |
391 | struct dm_mmc_ops { |
392 | /** | |
393 | * send_cmd() - Send a command to the MMC device | |
394 | * | |
395 | * @dev: Device to receive the command | |
396 | * @cmd: Command to send | |
397 | * @data: Additional data to send/receive | |
398 | * @return 0 if OK, -ve on error | |
399 | */ | |
400 | int (*send_cmd)(struct udevice *dev, struct mmc_cmd *cmd, | |
401 | struct mmc_data *data); | |
402 | ||
403 | /** | |
404 | * set_ios() - Set the I/O speed/width for an MMC device | |
405 | * | |
406 | * @dev: Device to update | |
407 | * @return 0 if OK, -ve on error | |
408 | */ | |
409 | int (*set_ios)(struct udevice *dev); | |
410 | ||
318a7a57 JJH |
411 | /** |
412 | * send_init_stream() - send the initialization stream: 74 clock cycles | |
413 | * This is used after power up before sending the first command | |
414 | * | |
415 | * @dev: Device to update | |
416 | */ | |
417 | void (*send_init_stream)(struct udevice *dev); | |
418 | ||
8ca51e51 SG |
419 | /** |
420 | * get_cd() - See whether a card is present | |
421 | * | |
422 | * @dev: Device to check | |
423 | * @return 0 if not present, 1 if present, -ve on error | |
424 | */ | |
425 | int (*get_cd)(struct udevice *dev); | |
426 | ||
427 | /** | |
428 | * get_wp() - See whether a card has write-protect enabled | |
429 | * | |
430 | * @dev: Device to check | |
431 | * @return 0 if write-enabled, 1 if write-protected, -ve on error | |
432 | */ | |
433 | int (*get_wp)(struct udevice *dev); | |
ec841209 | 434 | |
f99c2efe | 435 | #ifdef MMC_SUPPORTS_TUNING |
ec841209 KVA |
436 | /** |
437 | * execute_tuning() - Start the tuning process | |
438 | * | |
439 | * @dev: Device to start the tuning | |
440 | * @opcode: Command opcode to send | |
441 | * @return 0 if OK, -ve on error | |
442 | */ | |
443 | int (*execute_tuning)(struct udevice *dev, uint opcode); | |
f99c2efe | 444 | #endif |
c10b85d6 | 445 | |
f99c2efe | 446 | #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) |
c10b85d6 JJH |
447 | /** |
448 | * wait_dat0() - wait until dat0 is in the target state | |
449 | * (CLK must be running during the wait) | |
450 | * | |
451 | * @dev: Device to check | |
452 | * @state: target state | |
453 | * @timeout: timeout in us | |
454 | * @return 0 if dat0 is in the target state, -ve on error | |
455 | */ | |
456 | int (*wait_dat0)(struct udevice *dev, int state, int timeout); | |
f99c2efe | 457 | #endif |
8ca51e51 SG |
458 | }; |
459 | ||
460 | #define mmc_get_ops(dev) ((struct dm_mmc_ops *)(dev)->driver->ops) | |
461 | ||
462 | int dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, | |
463 | struct mmc_data *data); | |
464 | int dm_mmc_set_ios(struct udevice *dev); | |
318a7a57 | 465 | void dm_mmc_send_init_stream(struct udevice *dev); |
8ca51e51 SG |
466 | int dm_mmc_get_cd(struct udevice *dev); |
467 | int dm_mmc_get_wp(struct udevice *dev); | |
ec841209 | 468 | int dm_mmc_execute_tuning(struct udevice *dev, uint opcode); |
c10b85d6 | 469 | int dm_mmc_wait_dat0(struct udevice *dev, int state, int timeout); |
8ca51e51 SG |
470 | |
471 | /* Transition functions for compatibility */ | |
472 | int mmc_set_ios(struct mmc *mmc); | |
318a7a57 | 473 | void mmc_send_init_stream(struct mmc *mmc); |
8ca51e51 SG |
474 | int mmc_getcd(struct mmc *mmc); |
475 | int mmc_getwp(struct mmc *mmc); | |
ec841209 | 476 | int mmc_execute_tuning(struct mmc *mmc, uint opcode); |
c10b85d6 | 477 | int mmc_wait_dat0(struct mmc *mmc, int state, int timeout); |
8ca51e51 SG |
478 | |
479 | #else | |
ab769f22 PA |
480 | struct mmc_ops { |
481 | int (*send_cmd)(struct mmc *mmc, | |
482 | struct mmc_cmd *cmd, struct mmc_data *data); | |
07b0b9c0 | 483 | int (*set_ios)(struct mmc *mmc); |
ab769f22 PA |
484 | int (*init)(struct mmc *mmc); |
485 | int (*getcd)(struct mmc *mmc); | |
486 | int (*getwp)(struct mmc *mmc); | |
487 | }; | |
8ca51e51 | 488 | #endif |
ab769f22 | 489 | |
93bfd616 PA |
490 | struct mmc_config { |
491 | const char *name; | |
e7881d85 | 492 | #if !CONFIG_IS_ENABLED(DM_MMC) |
93bfd616 | 493 | const struct mmc_ops *ops; |
8ca51e51 | 494 | #endif |
93bfd616 PA |
495 | uint host_caps; |
496 | uint voltages; | |
497 | uint f_min; | |
498 | uint f_max; | |
499 | uint b_max; | |
500 | unsigned char part_type; | |
501 | }; | |
502 | ||
3697e599 PF |
503 | struct sd_ssr { |
504 | unsigned int au; /* In sectors */ | |
505 | unsigned int erase_timeout; /* In milliseconds */ | |
506 | unsigned int erase_offset; /* In milliseconds */ | |
507 | }; | |
508 | ||
35f9e196 JJH |
509 | enum bus_mode { |
510 | MMC_LEGACY, | |
511 | SD_LEGACY, | |
512 | MMC_HS, | |
513 | SD_HS, | |
f99c2efe JJH |
514 | MMC_HS_52, |
515 | MMC_DDR_52, | |
35f9e196 JJH |
516 | UHS_SDR12, |
517 | UHS_SDR25, | |
518 | UHS_SDR50, | |
35f9e196 | 519 | UHS_DDR50, |
f99c2efe | 520 | UHS_SDR104, |
35f9e196 JJH |
521 | MMC_HS_200, |
522 | MMC_MODES_END | |
523 | }; | |
524 | ||
525 | const char *mmc_mode_name(enum bus_mode mode); | |
4c9d2aaa | 526 | void mmc_dump_capabilities(const char *text, uint caps); |
35f9e196 | 527 | |
3862b854 JJH |
528 | static inline bool mmc_is_mode_ddr(enum bus_mode mode) |
529 | { | |
f99c2efe JJH |
530 | if (mode == MMC_DDR_52) |
531 | return true; | |
532 | #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) | |
533 | else if (mode == UHS_DDR50) | |
3862b854 | 534 | return true; |
f99c2efe | 535 | #endif |
3862b854 JJH |
536 | else |
537 | return false; | |
538 | } | |
539 | ||
c10b85d6 JJH |
540 | #define UHS_CAPS (MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25) | \ |
541 | MMC_CAP(UHS_SDR50) | MMC_CAP(UHS_SDR104) | \ | |
542 | MMC_CAP(UHS_DDR50)) | |
543 | ||
544 | static inline bool supports_uhs(uint caps) | |
545 | { | |
f99c2efe | 546 | #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) |
c10b85d6 | 547 | return (caps & UHS_CAPS) ? true : false; |
f99c2efe JJH |
548 | #else |
549 | return false; | |
550 | #endif | |
c10b85d6 JJH |
551 | } |
552 | ||
8ca51e51 SG |
553 | /* |
554 | * With CONFIG_DM_MMC enabled, struct mmc can be accessed from the MMC device | |
555 | * with mmc_get_mmc_dev(). | |
556 | * | |
557 | * TODO struct mmc should be in mmc_private but it's hard to fix right now | |
558 | */ | |
272cc70b | 559 | struct mmc { |
c4d660d4 | 560 | #if !CONFIG_IS_ENABLED(BLK) |
272cc70b | 561 | struct list_head link; |
33fb211d | 562 | #endif |
93bfd616 | 563 | const struct mmc_config *cfg; /* provided configuration */ |
272cc70b | 564 | uint version; |
93bfd616 | 565 | void *priv; |
bc897b1d | 566 | uint has_init; |
272cc70b | 567 | int high_capacity; |
35f67820 | 568 | bool clk_disable; /* true if the clock can be turned off */ |
272cc70b AF |
569 | uint bus_width; |
570 | uint clock; | |
aff5d3c8 | 571 | enum mmc_voltage signal_voltage; |
272cc70b | 572 | uint card_caps; |
04a2ea24 | 573 | uint host_caps; |
272cc70b | 574 | uint ocr; |
ab71188c MN |
575 | uint dsr; |
576 | uint dsr_imp; | |
272cc70b AF |
577 | uint scr[2]; |
578 | uint csd[4]; | |
0b453ffe | 579 | uint cid[4]; |
272cc70b | 580 | ushort rca; |
c3dbb4f9 DSC |
581 | u8 part_support; |
582 | u8 part_attr; | |
9e41a00b | 583 | u8 wr_rel_set; |
7ca0d3dd | 584 | u8 part_config; |
272cc70b | 585 | uint tran_speed; |
35f9e196 | 586 | uint legacy_speed; /* speed for the legacy mode provided by the card */ |
272cc70b | 587 | uint read_bl_len; |
e6fa5a54 | 588 | #if CONFIG_IS_ENABLED(MMC_WRITE) |
272cc70b | 589 | uint write_bl_len; |
a4ff9f83 | 590 | uint erase_grp_size; /* in 512-byte sectors */ |
e6fa5a54 | 591 | #endif |
b7a6e2c9 | 592 | #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING) |
037dc0ab | 593 | uint hc_wp_grp_size; /* in 512-byte sectors */ |
b7a6e2c9 | 594 | #endif |
5b2e72f3 | 595 | #if CONFIG_IS_ENABLED(MMC_WRITE) |
3697e599 | 596 | struct sd_ssr ssr; /* SD status register */ |
5b2e72f3 | 597 | #endif |
272cc70b | 598 | u64 capacity; |
f866a46d SW |
599 | u64 capacity_user; |
600 | u64 capacity_boot; | |
601 | u64 capacity_rpmb; | |
602 | u64 capacity_gp[4]; | |
173c06df | 603 | #ifndef CONFIG_SPL_BUILD |
a7f852b6 DSC |
604 | u64 enh_user_start; |
605 | u64 enh_user_size; | |
173c06df | 606 | #endif |
c4d660d4 | 607 | #if !CONFIG_IS_ENABLED(BLK) |
4101f687 | 608 | struct blk_desc block_dev; |
33fb211d | 609 | #endif |
e9550449 CLC |
610 | char op_cond_pending; /* 1 if we are waiting on an op_cond command */ |
611 | char init_in_progress; /* 1 if we have done mmc_start_init() */ | |
612 | char preinit; /* start init as early as possible */ | |
786e8f81 | 613 | int ddr_mode; |
c4d660d4 | 614 | #if CONFIG_IS_ENABLED(DM_MMC) |
cffe5d86 | 615 | struct udevice *dev; /* Device for this MMC controller */ |
06ec045f JJH |
616 | #if CONFIG_IS_ENABLED(DM_REGULATOR) |
617 | struct udevice *vmmc_supply; /* Main voltage regulator (Vcc)*/ | |
618 | struct udevice *vqmmc_supply; /* IO voltage regulator (Vccq)*/ | |
619 | #endif | |
cffe5d86 | 620 | #endif |
dfda9d88 | 621 | u8 *ext_csd; |
bc1e3272 JJH |
622 | u32 cardtype; /* cardtype read from the MMC */ |
623 | enum mmc_voltage current_voltage; | |
01298da3 JJH |
624 | enum bus_mode selected_mode; /* mode currently used */ |
625 | enum bus_mode best_mode; /* best mode is the supported mode with the | |
626 | * highest bandwidth. It may not always be the | |
627 | * operating mode due to limitations when | |
628 | * accessing the boot partitions | |
629 | */ | |
83dc4227 | 630 | u32 quirks; |
272cc70b AF |
631 | }; |
632 | ||
ac9da0e0 DSC |
633 | struct mmc_hwpart_conf { |
634 | struct { | |
635 | uint enh_start; /* in 512-byte sectors */ | |
636 | uint enh_size; /* in 512-byte sectors, if 0 no enh area */ | |
8dda5b0e DSC |
637 | unsigned wr_rel_change : 1; |
638 | unsigned wr_rel_set : 1; | |
ac9da0e0 DSC |
639 | } user; |
640 | struct { | |
641 | uint size; /* in 512-byte sectors */ | |
8dda5b0e DSC |
642 | unsigned enhanced : 1; |
643 | unsigned wr_rel_change : 1; | |
644 | unsigned wr_rel_set : 1; | |
ac9da0e0 DSC |
645 | } gp_part[4]; |
646 | }; | |
647 | ||
648 | enum mmc_hwpart_conf_mode { | |
649 | MMC_HWPART_CONF_CHECK, | |
650 | MMC_HWPART_CONF_SET, | |
651 | MMC_HWPART_CONF_COMPLETE, | |
652 | }; | |
653 | ||
93bfd616 | 654 | struct mmc *mmc_create(const struct mmc_config *cfg, void *priv); |
ad27dd5e SG |
655 | |
656 | /** | |
657 | * mmc_bind() - Set up a new MMC device ready for probing | |
658 | * | |
659 | * A child block device is bound with the IF_TYPE_MMC interface type. This | |
660 | * allows the device to be used with CONFIG_BLK | |
661 | * | |
662 | * @dev: MMC device to set up | |
663 | * @mmc: MMC struct | |
664 | * @cfg: MMC configuration | |
665 | * @return 0 if OK, -ve on error | |
666 | */ | |
667 | int mmc_bind(struct udevice *dev, struct mmc *mmc, | |
668 | const struct mmc_config *cfg); | |
93bfd616 | 669 | void mmc_destroy(struct mmc *mmc); |
ad27dd5e SG |
670 | |
671 | /** | |
672 | * mmc_unbind() - Unbind a MMC device's child block device | |
673 | * | |
674 | * @dev: MMC device | |
675 | * @return 0 if OK, -ve on error | |
676 | */ | |
677 | int mmc_unbind(struct udevice *dev); | |
272cc70b AF |
678 | int mmc_initialize(bd_t *bis); |
679 | int mmc_init(struct mmc *mmc); | |
9815e3ba | 680 | int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error); |
7abff2c3 JJH |
681 | |
682 | /** | |
683 | * mmc_of_parse() - Parse the device tree to get the capabilities of the host | |
684 | * | |
685 | * @dev: MMC device | |
686 | * @cfg: MMC configuration | |
687 | * @return 0 if OK, -ve on error | |
688 | */ | |
689 | int mmc_of_parse(struct udevice *dev, struct mmc_config *cfg); | |
690 | ||
272cc70b | 691 | int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size); |
35f67820 | 692 | |
bc1e3272 JJH |
693 | /** |
694 | * mmc_voltage_to_mv() - Convert a mmc_voltage in mV | |
695 | * | |
696 | * @voltage: The mmc_voltage to convert | |
697 | * @return the value in mV if OK, -EINVAL on error (invalid mmc_voltage value) | |
698 | */ | |
699 | int mmc_voltage_to_mv(enum mmc_voltage voltage); | |
700 | ||
35f67820 KVA |
701 | /** |
702 | * mmc_set_clock() - change the bus clock | |
703 | * @mmc: MMC struct | |
704 | * @clock: bus frequency in Hz | |
705 | * @disable: flag indicating if the clock must on or off | |
706 | * @return 0 if OK, -ve on error | |
707 | */ | |
708 | int mmc_set_clock(struct mmc *mmc, uint clock, bool disable); | |
709 | ||
272cc70b | 710 | struct mmc *find_mmc_device(int dev_num); |
89716964 | 711 | int mmc_set_dev(int dev_num); |
272cc70b | 712 | void print_mmc_devices(char separator); |
46683f3d KY |
713 | |
714 | /** | |
715 | * get_mmc_num() - get the total MMC device number | |
716 | * | |
717 | * @return 0 if there is no MMC device, else the number of devices | |
718 | */ | |
ea6ebe21 | 719 | int get_mmc_num(void); |
b5b838f1 | 720 | int mmc_switch_part(struct mmc *mmc, unsigned int part_num); |
ac9da0e0 DSC |
721 | int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf, |
722 | enum mmc_hwpart_conf_mode mode); | |
8ca51e51 | 723 | |
e7881d85 | 724 | #if !CONFIG_IS_ENABLED(DM_MMC) |
48972d90 | 725 | int mmc_getcd(struct mmc *mmc); |
750121c3 | 726 | int board_mmc_getcd(struct mmc *mmc); |
d23d8d7e | 727 | int mmc_getwp(struct mmc *mmc); |
750121c3 | 728 | int board_mmc_getwp(struct mmc *mmc); |
8ca51e51 SG |
729 | #endif |
730 | ||
ab71188c | 731 | int mmc_set_dsr(struct mmc *mmc, u16 val); |
3690d6d6 A |
732 | /* Function to change the size of boot partition and rpmb partitions */ |
733 | int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, | |
734 | unsigned long rpmbsize); | |
792970b0 TR |
735 | /* Function to modify the PARTITION_CONFIG field of EXT_CSD */ |
736 | int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access); | |
5a99b9de TR |
737 | /* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */ |
738 | int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode); | |
33ace362 TR |
739 | /* Function to modify the RST_n_FUNCTION field of EXT_CSD */ |
740 | int mmc_set_rst_n_function(struct mmc *mmc, u8 enable); | |
91fdabc6 PA |
741 | /* Functions to read / write the RPMB partition */ |
742 | int mmc_rpmb_set_key(struct mmc *mmc, void *key); | |
743 | int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter); | |
744 | int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk, | |
745 | unsigned short cnt, unsigned char *key); | |
746 | int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk, | |
747 | unsigned short cnt, unsigned char *key); | |
cd3d4880 TM |
748 | #ifdef CONFIG_CMD_BKOPS_ENABLE |
749 | int mmc_set_bkops_enable(struct mmc *mmc); | |
750 | #endif | |
751 | ||
e9550449 CLC |
752 | /** |
753 | * Start device initialization and return immediately; it does not block on | |
754 | * polling OCR (operation condition register) status. Then you should call | |
755 | * mmc_init, which would block on polling OCR status and complete the device | |
756 | * initializatin. | |
757 | * | |
758 | * @param mmc Pointer to a MMC device struct | |
759 | * @return 0 on success, IN_PROGRESS on waiting for OCR status, <0 on error. | |
760 | */ | |
761 | int mmc_start_init(struct mmc *mmc); | |
762 | ||
763 | /** | |
764 | * Set preinit flag of mmc device. | |
765 | * | |
766 | * This will cause the device to be pre-inited during mmc_initialize(), | |
767 | * which may save boot time if the device is not accessed until later. | |
768 | * Some eMMC devices take 200-300ms to init, but unfortunately they | |
769 | * must be sent a series of commands to even get them to start preparing | |
770 | * for operation. | |
771 | * | |
772 | * @param mmc Pointer to a MMC device struct | |
773 | * @param preinit preinit flag value | |
774 | */ | |
775 | void mmc_set_preinit(struct mmc *mmc, int preinit); | |
776 | ||
8687d5c8 | 777 | #ifdef CONFIG_MMC_SPI |
0b2da7e2 | 778 | #define mmc_host_is_spi(mmc) ((mmc)->cfg->host_caps & MMC_MODE_SPI) |
8687d5c8 PB |
779 | #else |
780 | #define mmc_host_is_spi(mmc) 0 | |
781 | #endif | |
d52ebf10 | 782 | struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode); |
1592ef85 | 783 | |
95de9ab2 | 784 | void board_mmc_power_init(void); |
3c7ca967 | 785 | int board_mmc_init(bd_t *bis); |
750121c3 | 786 | int cpu_mmc_init(bd_t *bis); |
aeb80555 | 787 | int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr); |
aa844fe1 | 788 | int mmc_get_env_dev(void); |
3c7ca967 | 789 | |
93bfd616 PA |
790 | /* Set block count limit because of 16 bit register limit on some hardware*/ |
791 | #ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT | |
792 | #define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535 | |
793 | #endif | |
794 | ||
cb5ec33d SG |
795 | /** |
796 | * mmc_get_blk_desc() - Get the block descriptor for an MMC device | |
797 | * | |
798 | * @mmc: MMC device | |
799 | * @return block device if found, else NULL | |
800 | */ | |
801 | struct blk_desc *mmc_get_blk_desc(struct mmc *mmc); | |
802 | ||
71f95118 | 803 | #endif /* _MMC_H_ */ |