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71f95118 1/*
4a6ee172 2 * Copyright 2008,2010 Freescale Semiconductor, Inc
272cc70b
AF
3 * Andy Fleming
4 *
5 * Based (loosely) on the Linux code
71f95118 6 *
1a459660 7 * SPDX-License-Identifier: GPL-2.0+
71f95118
WD
8 */
9
10#ifndef _MMC_H_
11#define _MMC_H_
71f95118 12
272cc70b 13#include <linux/list.h>
0d986e61 14#include <linux/compiler.h>
07a2d42c 15#include <part.h>
272cc70b 16
4b7cee53
PA
17/* SD/MMC version bits; 8 flags, 8 major, 8 minor, 8 change */
18#define SD_VERSION_SD (1U << 31)
19#define MMC_VERSION_MMC (1U << 30)
20
21#define MAKE_SDMMC_VERSION(a, b, c) \
22 ((((u32)(a)) << 16) | ((u32)(b) << 8) | (u32)(c))
23#define MAKE_SD_VERSION(a, b, c) \
24 (SD_VERSION_SD | MAKE_SDMMC_VERSION(a, b, c))
25#define MAKE_MMC_VERSION(a, b, c) \
26 (MMC_VERSION_MMC | MAKE_SDMMC_VERSION(a, b, c))
27
28#define EXTRACT_SDMMC_MAJOR_VERSION(x) \
29 (((u32)(x) >> 16) & 0xff)
30#define EXTRACT_SDMMC_MINOR_VERSION(x) \
31 (((u32)(x) >> 8) & 0xff)
32#define EXTRACT_SDMMC_CHANGE_VERSION(x) \
33 ((u32)(x) & 0xff)
34
35#define SD_VERSION_3 MAKE_SD_VERSION(3, 0, 0)
36#define SD_VERSION_2 MAKE_SD_VERSION(2, 0, 0)
37#define SD_VERSION_1_0 MAKE_SD_VERSION(1, 0, 0)
38#define SD_VERSION_1_10 MAKE_SD_VERSION(1, 10, 0)
39
40#define MMC_VERSION_UNKNOWN MAKE_MMC_VERSION(0, 0, 0)
41#define MMC_VERSION_1_2 MAKE_MMC_VERSION(1, 2, 0)
42#define MMC_VERSION_1_4 MAKE_MMC_VERSION(1, 4, 0)
43#define MMC_VERSION_2_2 MAKE_MMC_VERSION(2, 2, 0)
44#define MMC_VERSION_3 MAKE_MMC_VERSION(3, 0, 0)
45#define MMC_VERSION_4 MAKE_MMC_VERSION(4, 0, 0)
46#define MMC_VERSION_4_1 MAKE_MMC_VERSION(4, 1, 0)
47#define MMC_VERSION_4_2 MAKE_MMC_VERSION(4, 2, 0)
48#define MMC_VERSION_4_3 MAKE_MMC_VERSION(4, 3, 0)
49#define MMC_VERSION_4_41 MAKE_MMC_VERSION(4, 4, 1)
50#define MMC_VERSION_4_5 MAKE_MMC_VERSION(4, 5, 0)
51#define MMC_VERSION_5_0 MAKE_MMC_VERSION(5, 0, 0)
272cc70b 52
8caf46d1
JC
53#define MMC_MODE_HS (1 << 0)
54#define MMC_MODE_HS_52MHz (1 << 1)
55#define MMC_MODE_4BIT (1 << 2)
56#define MMC_MODE_8BIT (1 << 3)
57#define MMC_MODE_SPI (1 << 4)
5a20397b 58#define MMC_MODE_DDR_52MHz (1 << 5)
62722036 59
272cc70b
AF
60#define SD_DATA_4BIT 0x00040000
61
4b7cee53 62#define IS_SD(x) ((x)->version & SD_VERSION_SD)
3f2da751 63#define IS_MMC(x) ((x)->version & MMC_VERSION_MMC)
272cc70b
AF
64
65#define MMC_DATA_READ 1
66#define MMC_DATA_WRITE 2
67
68#define NO_CARD_ERR -16 /* No SD/MMC card inserted */
69#define UNUSABLE_ERR -17 /* Unusable Card */
70#define COMM_ERR -18 /* Communications Error */
71#define TIMEOUT -19
bd47c135 72#define SWITCH_ERR -20 /* Card reports failure to switch mode */
272cc70b 73
341188b9
HS
74#define MMC_CMD_GO_IDLE_STATE 0
75#define MMC_CMD_SEND_OP_COND 1
76#define MMC_CMD_ALL_SEND_CID 2
77#define MMC_CMD_SET_RELATIVE_ADDR 3
78#define MMC_CMD_SET_DSR 4
272cc70b 79#define MMC_CMD_SWITCH 6
341188b9 80#define MMC_CMD_SELECT_CARD 7
272cc70b 81#define MMC_CMD_SEND_EXT_CSD 8
341188b9
HS
82#define MMC_CMD_SEND_CSD 9
83#define MMC_CMD_SEND_CID 10
272cc70b 84#define MMC_CMD_STOP_TRANSMISSION 12
341188b9
HS
85#define MMC_CMD_SEND_STATUS 13
86#define MMC_CMD_SET_BLOCKLEN 16
87#define MMC_CMD_READ_SINGLE_BLOCK 17
88#define MMC_CMD_READ_MULTIPLE_BLOCK 18
91fdabc6 89#define MMC_CMD_SET_BLOCK_COUNT 23
272cc70b
AF
90#define MMC_CMD_WRITE_SINGLE_BLOCK 24
91#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
e6f99a56
LW
92#define MMC_CMD_ERASE_GROUP_START 35
93#define MMC_CMD_ERASE_GROUP_END 36
94#define MMC_CMD_ERASE 38
341188b9 95#define MMC_CMD_APP_CMD 55
d52ebf10
TC
96#define MMC_CMD_SPI_READ_OCR 58
97#define MMC_CMD_SPI_CRC_ON_OFF 59
3690d6d6
A
98#define MMC_CMD_RES_MAN 62
99
100#define MMC_CMD62_ARG1 0xefac62ec
101#define MMC_CMD62_ARG2 0xcbaea7
102
341188b9 103
341188b9 104#define SD_CMD_SEND_RELATIVE_ADDR 3
272cc70b 105#define SD_CMD_SWITCH_FUNC 6
341188b9 106#define SD_CMD_SEND_IF_COND 8
f022d36e 107#define SD_CMD_SWITCH_UHS18V 11
341188b9
HS
108
109#define SD_CMD_APP_SET_BUS_WIDTH 6
e6f99a56
LW
110#define SD_CMD_ERASE_WR_BLK_START 32
111#define SD_CMD_ERASE_WR_BLK_END 33
341188b9 112#define SD_CMD_APP_SEND_OP_COND 41
272cc70b
AF
113#define SD_CMD_APP_SEND_SCR 51
114
115/* SCR definitions in different words */
116#define SD_HIGHSPEED_BUSY 0x00020000
117#define SD_HIGHSPEED_SUPPORTED 0x00020000
118
abe2c93f
TC
119#define OCR_BUSY 0x80000000
120#define OCR_HCS 0x40000000
31cacbab
RR
121#define OCR_VOLTAGE_MASK 0x007FFF80
122#define OCR_ACCESS_MODE 0x60000000
272cc70b 123
e6f99a56
LW
124#define SECURE_ERASE 0x80000000
125
5d4fc8d9 126#define MMC_STATUS_MASK (~0x0206BF7F)
6b2221b0 127#define MMC_STATUS_SWITCH_ERROR (1 << 7)
abe2c93f
TC
128#define MMC_STATUS_RDY_FOR_DATA (1 << 8)
129#define MMC_STATUS_CURR_STATE (0xf << 9)
ed018b21 130#define MMC_STATUS_ERROR (1 << 19)
5d4fc8d9 131
d617c426
JK
132#define MMC_STATE_PRG (7 << 9)
133
272cc70b
AF
134#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
135#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
136#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
137#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
138#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
139#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
140#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
141#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
142#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
143#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
144#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
145#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
146#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
147#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
148#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
149#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
150#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
151
152#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
153#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte
154 addressed by index which are
155 1 in value field */
156#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte
157 addressed by index, which are
158 1 in value field */
159#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */
160
161#define SD_SWITCH_CHECK 0
162#define SD_SWITCH_SWITCH 1
163
164/*
165 * EXT_CSD fields
166 */
a7f852b6
DSC
167#define EXT_CSD_ENH_START_ADDR 136 /* R/W */
168#define EXT_CSD_ENH_SIZE_MULT 140 /* R/W */
f866a46d 169#define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
d7b29129 170#define EXT_CSD_PARTITION_SETTING 155 /* R/W */
1937e5aa 171#define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */
ac9da0e0 172#define EXT_CSD_MAX_ENH_SIZE_MULT 157 /* R */
0560db18 173#define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */
33ace362 174#define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
8dda5b0e
DSC
175#define EXT_CSD_WR_REL_PARAM 166 /* R */
176#define EXT_CSD_WR_REL_SET 167 /* R/W */
f866a46d 177#define EXT_CSD_RPMB_MULT 168 /* RO */
0560db18 178#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
3690d6d6 179#define EXT_CSD_BOOT_BUS_WIDTH 177
0560db18
LW
180#define EXT_CSD_PART_CONF 179 /* R/W */
181#define EXT_CSD_BUS_WIDTH 183 /* R/W */
182#define EXT_CSD_HS_TIMING 185 /* R/W */
183#define EXT_CSD_REV 192 /* RO */
184#define EXT_CSD_CARD_TYPE 196 /* RO */
185#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
f866a46d 186#define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
0560db18 187#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
8948ea83 188#define EXT_CSD_BOOT_MULT 226 /* RO */
272cc70b
AF
189
190/*
191 * EXT_CSD field definitions
192 */
193
abe2c93f
TC
194#define EXT_CSD_CMD_SET_NORMAL (1 << 0)
195#define EXT_CSD_CMD_SET_SECURE (1 << 1)
196#define EXT_CSD_CMD_SET_CPSECURE (1 << 2)
272cc70b 197
abe2c93f
TC
198#define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */
199#define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */
d22e3d46
JC
200#define EXT_CSD_CARD_TYPE_DDR_1_8V (1 << 2)
201#define EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3)
202#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
203 | EXT_CSD_CARD_TYPE_DDR_1_2V)
272cc70b
AF
204
205#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
206#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
207#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
d22e3d46
JC
208#define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
209#define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
341188b9 210
3690d6d6
A
211#define EXT_CSD_BOOT_ACK_ENABLE (1 << 6)
212#define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3)
213#define EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0)
214#define EXT_CSD_PARTITION_ACCESS_DISABLE (0 << 0)
215
216#define EXT_CSD_BOOT_ACK(x) (x << 6)
217#define EXT_CSD_BOOT_PART_NUM(x) (x << 3)
218#define EXT_CSD_PARTITION_ACCESS(x) (x << 0)
219
5a99b9de
TR
220#define EXT_CSD_BOOT_BUS_WIDTH_MODE(x) (x << 3)
221#define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2)
222#define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x)
3690d6d6 223
d7b29129
MN
224#define EXT_CSD_PARTITION_SETTING_COMPLETED (1 << 0)
225
c3dbb4f9
DSC
226#define EXT_CSD_ENH_USR (1 << 0) /* user data area is enhanced */
227#define EXT_CSD_ENH_GP(x) (1 << ((x)+1)) /* GP part (x+1) is enhanced */
228
8dda5b0e
DSC
229#define EXT_CSD_HS_CTRL_REL (1 << 0) /* host controlled WR_REL_SET */
230
231#define EXT_CSD_WR_DATA_REL_USR (1 << 0) /* user data area WR_REL */
232#define EXT_CSD_WR_DATA_REL_GP(x) (1 << ((x)+1)) /* GP part (x+1) WR_REL */
233
1de97f98
AF
234#define R1_ILLEGAL_COMMAND (1 << 22)
235#define R1_APP_CMD (1 << 5)
236
272cc70b 237#define MMC_RSP_PRESENT (1 << 0)
abe2c93f
TC
238#define MMC_RSP_136 (1 << 1) /* 136 bit response */
239#define MMC_RSP_CRC (1 << 2) /* expect valid crc */
240#define MMC_RSP_BUSY (1 << 3) /* card may send busy */
241#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
272cc70b 242
abe2c93f
TC
243#define MMC_RSP_NONE (0)
244#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
272cc70b
AF
245#define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
246 MMC_RSP_BUSY)
abe2c93f
TC
247#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
248#define MMC_RSP_R3 (MMC_RSP_PRESENT)
249#define MMC_RSP_R4 (MMC_RSP_PRESENT)
250#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
251#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
252#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
272cc70b 253
bc897b1d
LW
254#define MMCPART_NOAVAILABLE (0xff)
255#define PART_ACCESS_MASK (0x7)
256#define PART_SUPPORT (0x1)
c3dbb4f9 257#define ENHNCD_SUPPORT (0x2)
1937e5aa 258#define PART_ENH_ATTRIB (0x1f)
71f95118 259
8bfa195e
SG
260/* Maximum block size for MMC */
261#define MMC_MAX_BLOCK_LEN 512
262
3690d6d6
A
263/* The number of MMC physical partitions. These consist of:
264 * boot partitions (2), general purpose partitions (4) in MMC v4.4.
265 */
266#define MMC_NUM_BOOT_PARTITION 2
91fdabc6 267#define MMC_PART_RPMB 3 /* RPMB partition number */
3690d6d6 268
1de97f98
AF
269struct mmc_cid {
270 unsigned long psn;
271 unsigned short oid;
272 unsigned char mid;
273 unsigned char prv;
274 unsigned char mdt;
275 char pnm[7];
276};
277
272cc70b
AF
278struct mmc_cmd {
279 ushort cmdidx;
280 uint resp_type;
281 uint cmdarg;
0b453ffe 282 uint response[4];
272cc70b
AF
283};
284
285struct mmc_data {
286 union {
287 char *dest;
288 const char *src; /* src buffers don't get written to */
289 };
290 uint flags;
291 uint blocks;
292 uint blocksize;
293};
294
ab769f22
PA
295/* forward decl. */
296struct mmc;
297
298struct mmc_ops {
299 int (*send_cmd)(struct mmc *mmc,
300 struct mmc_cmd *cmd, struct mmc_data *data);
301 void (*set_ios)(struct mmc *mmc);
302 int (*init)(struct mmc *mmc);
303 int (*getcd)(struct mmc *mmc);
304 int (*getwp)(struct mmc *mmc);
305};
306
93bfd616
PA
307struct mmc_config {
308 const char *name;
309 const struct mmc_ops *ops;
310 uint host_caps;
311 uint voltages;
312 uint f_min;
313 uint f_max;
314 uint b_max;
315 unsigned char part_type;
316};
317
318/* TODO struct mmc should be in mmc_private but it's hard to fix right now */
272cc70b
AF
319struct mmc {
320 struct list_head link;
93bfd616 321 const struct mmc_config *cfg; /* provided configuration */
272cc70b 322 uint version;
93bfd616 323 void *priv;
bc897b1d 324 uint has_init;
272cc70b
AF
325 int high_capacity;
326 uint bus_width;
327 uint clock;
328 uint card_caps;
272cc70b 329 uint ocr;
ab71188c
MN
330 uint dsr;
331 uint dsr_imp;
272cc70b
AF
332 uint scr[2];
333 uint csd[4];
0b453ffe 334 uint cid[4];
272cc70b 335 ushort rca;
c3dbb4f9
DSC
336 u8 part_support;
337 u8 part_attr;
9e41a00b 338 u8 wr_rel_set;
bc897b1d
LW
339 char part_config;
340 char part_num;
272cc70b
AF
341 uint tran_speed;
342 uint read_bl_len;
343 uint write_bl_len;
a4ff9f83 344 uint erase_grp_size; /* in 512-byte sectors */
037dc0ab 345 uint hc_wp_grp_size; /* in 512-byte sectors */
272cc70b 346 u64 capacity;
f866a46d
SW
347 u64 capacity_user;
348 u64 capacity_boot;
349 u64 capacity_rpmb;
350 u64 capacity_gp[4];
a7f852b6
DSC
351 u64 enh_user_start;
352 u64 enh_user_size;
272cc70b 353 block_dev_desc_t block_dev;
e9550449
CLC
354 char op_cond_pending; /* 1 if we are waiting on an op_cond command */
355 char init_in_progress; /* 1 if we have done mmc_start_init() */
356 char preinit; /* start init as early as possible */
786e8f81 357 int ddr_mode;
272cc70b
AF
358};
359
ac9da0e0
DSC
360struct mmc_hwpart_conf {
361 struct {
362 uint enh_start; /* in 512-byte sectors */
363 uint enh_size; /* in 512-byte sectors, if 0 no enh area */
8dda5b0e
DSC
364 unsigned wr_rel_change : 1;
365 unsigned wr_rel_set : 1;
ac9da0e0
DSC
366 } user;
367 struct {
368 uint size; /* in 512-byte sectors */
8dda5b0e
DSC
369 unsigned enhanced : 1;
370 unsigned wr_rel_change : 1;
371 unsigned wr_rel_set : 1;
ac9da0e0
DSC
372 } gp_part[4];
373};
374
375enum mmc_hwpart_conf_mode {
376 MMC_HWPART_CONF_CHECK,
377 MMC_HWPART_CONF_SET,
378 MMC_HWPART_CONF_COMPLETE,
379};
380
272cc70b 381int mmc_register(struct mmc *mmc);
93bfd616
PA
382struct mmc *mmc_create(const struct mmc_config *cfg, void *priv);
383void mmc_destroy(struct mmc *mmc);
272cc70b
AF
384int mmc_initialize(bd_t *bis);
385int mmc_init(struct mmc *mmc);
386int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
4a6ee172 387void mmc_set_clock(struct mmc *mmc, uint clock);
272cc70b 388struct mmc *find_mmc_device(int dev_num);
89716964 389int mmc_set_dev(int dev_num);
272cc70b 390void print_mmc_devices(char separator);
ea6ebe21 391int get_mmc_num(void);
bc897b1d 392int mmc_switch_part(int dev_num, unsigned int part_num);
ac9da0e0
DSC
393int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf,
394 enum mmc_hwpart_conf_mode mode);
48972d90 395int mmc_getcd(struct mmc *mmc);
750121c3 396int board_mmc_getcd(struct mmc *mmc);
d23d8d7e 397int mmc_getwp(struct mmc *mmc);
750121c3 398int board_mmc_getwp(struct mmc *mmc);
ab71188c 399int mmc_set_dsr(struct mmc *mmc, u16 val);
3690d6d6
A
400/* Function to change the size of boot partition and rpmb partitions */
401int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
402 unsigned long rpmbsize);
792970b0
TR
403/* Function to modify the PARTITION_CONFIG field of EXT_CSD */
404int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access);
5a99b9de
TR
405/* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */
406int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode);
33ace362
TR
407/* Function to modify the RST_n_FUNCTION field of EXT_CSD */
408int mmc_set_rst_n_function(struct mmc *mmc, u8 enable);
91fdabc6
PA
409/* Functions to read / write the RPMB partition */
410int mmc_rpmb_set_key(struct mmc *mmc, void *key);
411int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter);
412int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk,
413 unsigned short cnt, unsigned char *key);
414int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk,
415 unsigned short cnt, unsigned char *key);
e9550449
CLC
416/**
417 * Start device initialization and return immediately; it does not block on
418 * polling OCR (operation condition register) status. Then you should call
419 * mmc_init, which would block on polling OCR status and complete the device
420 * initializatin.
421 *
422 * @param mmc Pointer to a MMC device struct
423 * @return 0 on success, IN_PROGRESS on waiting for OCR status, <0 on error.
424 */
425int mmc_start_init(struct mmc *mmc);
426
427/**
428 * Set preinit flag of mmc device.
429 *
430 * This will cause the device to be pre-inited during mmc_initialize(),
431 * which may save boot time if the device is not accessed until later.
432 * Some eMMC devices take 200-300ms to init, but unfortunately they
433 * must be sent a series of commands to even get them to start preparing
434 * for operation.
435 *
436 * @param mmc Pointer to a MMC device struct
437 * @param preinit preinit flag value
438 */
439void mmc_set_preinit(struct mmc *mmc, int preinit);
440
1592ef85 441#ifdef CONFIG_GENERIC_MMC
8687d5c8 442#ifdef CONFIG_MMC_SPI
0b2da7e2 443#define mmc_host_is_spi(mmc) ((mmc)->cfg->host_caps & MMC_MODE_SPI)
8687d5c8
PB
444#else
445#define mmc_host_is_spi(mmc) 0
446#endif
d52ebf10 447struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode);
1592ef85 448#else
272cc70b
AF
449int mmc_legacy_init(int verbose);
450#endif
1592ef85 451
95de9ab2 452void board_mmc_power_init(void);
3c7ca967 453int board_mmc_init(bd_t *bis);
750121c3 454int cpu_mmc_init(bd_t *bis);
aeb80555 455int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
3c7ca967 456
91785f70
SG
457struct pci_device_id;
458
459/**
460 * pci_mmc_init() - set up PCI MMC devices
461 *
462 * This finds all the matching PCI IDs and sets them up as MMC devices.
463 *
464 * @name: Name to use for devices
465 * @mmc_supported: PCI IDs to search for
466 * @num_ids: Number of elements in @mmc_supported
467 */
468int pci_mmc_init(const char *name, struct pci_device_id *mmc_supported,
469 int num_ids);
470
93bfd616
PA
471/* Set block count limit because of 16 bit register limit on some hardware*/
472#ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
473#define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
474#endif
475
71f95118 476#endif /* _MMC_H_ */