[people/ms/u-boot.git] / nand_spl / nand_boot.c

/*
 * (C) Copyright 2006-2008
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <nand.h>
#include <asm/io.h>

static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;

#define ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE / \
					CONFIG_SYS_NAND_ECCSIZE)
#define ECCTOTAL	(ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)


#if (CONFIG_SYS_NAND_PAGE_SIZE <= 512)
/*
 * NAND command for small page NAND devices (512)
 */
static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd)
{
	struct nand_chip *this = mtd->priv;
	int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;

	while (!this->dev_ready(mtd))
		;

	/* Begin command latch cycle */
	this->cmd_ctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
	/* Set ALE and clear CLE to start address cycle */
	/* Column address */
	this->cmd_ctrl(mtd, offs, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
	this->cmd_ctrl(mtd, page_addr & 0xff, NAND_CTRL_ALE); /* A[16:9] */
	this->cmd_ctrl(mtd, (page_addr >> 8) & 0xff,
		       NAND_CTRL_ALE); /* A[24:17] */
#ifdef CONFIG_SYS_NAND_4_ADDR_CYCLE
	/* One more address cycle for devices > 32MiB */
	this->cmd_ctrl(mtd, (page_addr >> 16) & 0x0f,
		       NAND_CTRL_ALE); /* A[28:25] */
#endif
	/* Latch in address */
	this->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);

	/*
	 * Wait a while for the data to be ready
	 */
	while (!this->dev_ready(mtd))
		;

	return 0;
}
#else
/*
 * NAND command for large page NAND devices (2k)
 */
static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd)
{
	struct nand_chip *this = mtd->priv;
	int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
	void (*hwctrl)(struct mtd_info *mtd, int cmd,
			unsigned int ctrl) = this->cmd_ctrl;

	while (!this->dev_ready(mtd))
		;

	/* Emulate NAND_CMD_READOOB */
	if (cmd == NAND_CMD_READOOB) {
		offs += CONFIG_SYS_NAND_PAGE_SIZE;
		cmd = NAND_CMD_READ0;
	}

	/* Shift the offset from byte addressing to word addressing. */
	if (this->options & NAND_BUSWIDTH_16)
		offs >>= 1;

	/* Begin command latch cycle */
	hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
	/* Set ALE and clear CLE to start address cycle */
	/* Column address */
	hwctrl(mtd, offs & 0xff,
		       NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
	hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
	/* Row address */
	hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
	hwctrl(mtd, ((page_addr >> 8) & 0xff),
		       NAND_CTRL_ALE); /* A[27:20] */
#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
	/* One more address cycle for devices > 128MiB */
	hwctrl(mtd, (page_addr >> 16) & 0x0f,
		       NAND_CTRL_ALE); /* A[31:28] */
#endif
	/* Latch in address */
	hwctrl(mtd, NAND_CMD_READSTART,
		       NAND_CTRL_CLE | NAND_CTRL_CHANGE);
	hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);

	/*
	 * Wait a while for the data to be ready
	 */
	while (!this->dev_ready(mtd))
		;

	return 0;
}
#endif

static int nand_is_bad_block(struct mtd_info *mtd, int block)
{
	struct nand_chip *this = mtd->priv;

	nand_command(mtd, block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);

	/*
	 * Read one byte (or two if it's a 16 bit chip).
	 */
	if (this->options & NAND_BUSWIDTH_16) {
		if (readw(this->IO_ADDR_R) != 0xffff)
			return 1;
	} else {
		if (readb(this->IO_ADDR_R) != 0xff)
			return 1;
	}

	return 0;
}

#if defined(CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST)
static int nand_read_page(struct mtd_info *mtd, int block, int page, uchar *dst)
{
	struct nand_chip *this = mtd->priv;
	u_char ecc_calc[ECCTOTAL];
	u_char ecc_code[ECCTOTAL];
	u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
	int i;
	int eccsize = CONFIG_SYS_NAND_ECCSIZE;
	int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
	int eccsteps = ECCSTEPS;
	uint8_t *p = dst;

	nand_command(mtd, block, page, 0, NAND_CMD_READOOB);
	this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
	nand_command(mtd, block, page, 0, NAND_CMD_READ0);

	/* Pick the ECC bytes out of the oob data */
	for (i = 0; i < ECCTOTAL; i++)
		ecc_code[i] = oob_data[nand_ecc_pos[i]];


	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
		this->ecc.hwctl(mtd, NAND_ECC_READ);
		this->read_buf(mtd, p, eccsize);
		this->ecc.calculate(mtd, p, &ecc_calc[i]);
		this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
	}

	return 0;
}
#else
static int nand_read_page(struct mtd_info *mtd, int block, int page, uchar *dst)
{
	struct nand_chip *this = mtd->priv;
	u_char ecc_calc[ECCTOTAL];
	u_char ecc_code[ECCTOTAL];
	u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
	int i;
	int eccsize = CONFIG_SYS_NAND_ECCSIZE;
	int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
	int eccsteps = ECCSTEPS;
	uint8_t *p = dst;

	nand_command(mtd, block, page, 0, NAND_CMD_READ0);

	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
		this->ecc.hwctl(mtd, NAND_ECC_READ);
		this->read_buf(mtd, p, eccsize);
		this->ecc.calculate(mtd, p, &ecc_calc[i]);
	}
	this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);

	/* Pick the ECC bytes out of the oob data */
	for (i = 0; i < ECCTOTAL; i++)
		ecc_code[i] = oob_data[nand_ecc_pos[i]];

	eccsteps = ECCSTEPS;
	p = dst;

	for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
		/* No chance to do something with the possible error message
		 * from correct_data(). We just hope that all possible errors
		 * are corrected by this routine.
		 */
		this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
	}

	return 0;
}
#endif /* #if defined(CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST) */

static int nand_load(struct mtd_info *mtd, unsigned int offs,
		     unsigned int uboot_size, uchar *dst)
{
	unsigned int block, lastblock;
	unsigned int page;

	/*
	 * offs has to be aligned to a page address!
	 */
	block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
	lastblock = (offs + uboot_size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
	page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;

	while (block <= lastblock) {
		if (!nand_is_bad_block(mtd, block)) {
			/*
			 * Skip bad blocks
			 */
			while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
				nand_read_page(mtd, block, page, dst);
				dst += CONFIG_SYS_NAND_PAGE_SIZE;
				page++;
			}

			page = 0;
		} else {
			lastblock++;
		}

		block++;
	}

	return 0;
}

/*
 * The main entry for NAND booting. It's necessary that SDRAM is already
 * configured and available since this code loads the main U-Boot image
 * from NAND into SDRAM and starts it from there.
 */
void nand_boot(void)
{
	struct nand_chip nand_chip;
	nand_info_t nand_info;
	__attribute__((noreturn)) void (*uboot)(void);

	/*
	 * Init board specific nand support
	 */
	nand_chip.select_chip = NULL;
	nand_info.priv = &nand_chip;
	nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W = (void  __iomem *)CONFIG_SYS_NAND_BASE;
	nand_chip.dev_ready = NULL;	/* preset to NULL */
	nand_chip.options = 0;
	board_nand_init(&nand_chip);

	if (nand_chip.select_chip)
		nand_chip.select_chip(&nand_info, 0);

	/*
	 * Load U-Boot image from NAND into RAM
	 */
	nand_load(&nand_info, CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
		  (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);

#ifdef CONFIG_NAND_ENV_DST
	nand_load(&nand_info, CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
		  (uchar *)CONFIG_NAND_ENV_DST);

#ifdef CONFIG_ENV_OFFSET_REDUND
	nand_load(&nand_info, CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
		  (uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
#endif
#endif

	if (nand_chip.select_chip)
		nand_chip.select_chip(&nand_info, -1);

	/*
	 * Jump to U-Boot image
	 */
	uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
	(*uboot)();
}
Commit	Line	Data
887e2ec9	1	/*
46f37383	2	* (C) Copyright 2006-2008
887e2ec9 SR	3	* Stefan Roese, DENX Software Engineering, sr@denx.de.
887e2ec9 SR	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
887e2ec9 SR	6	*/
	7
	8	#include <common.h>
	9	#include <nand.h>
c568f77a	10	#include <asm/io.h>
887e2ec9	11
6d0f6bcf	12	static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
42be56f5	13
25efd99d SW	14	#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
	15	CONFIG_SYS_NAND_ECCSIZE)
	16	#define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
	17
	18
6d0f6bcf	19	#if (CONFIG_SYS_NAND_PAGE_SIZE <= 512)
46f37383 SR	20	/*
	21	* NAND command for small page NAND devices (512)
	22	*/
42be56f5	23	static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd)
887e2ec9	24	{
511d0c72	25	struct nand_chip *this = mtd->priv;
6d0f6bcf	26	int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
42be56f5	27
e29816f3 SR	28	while (!this->dev_ready(mtd))
e29816f3 SR	29	;
887e2ec9 SR	30
887e2ec9 SR	31	/* Begin command latch cycle */
4f32d776	32	this->cmd_ctrl(mtd, cmd, NAND_CTRL_CLE \| NAND_CTRL_CHANGE);
887e2ec9	33	/* Set ALE and clear CLE to start address cycle */
887e2ec9	34	/* Column address */
4f32d776	35	this->cmd_ctrl(mtd, offs, NAND_CTRL_ALE \| NAND_CTRL_CHANGE);
1dac3a51 SW	36	this->cmd_ctrl(mtd, page_addr & 0xff, NAND_CTRL_ALE); /* A[16:9] */
	37	this->cmd_ctrl(mtd, (page_addr >> 8) & 0xff,
	38	NAND_CTRL_ALE); /* A[24:17] */
6d0f6bcf	39	#ifdef CONFIG_SYS_NAND_4_ADDR_CYCLE
887e2ec9	40	/* One more address cycle for devices > 32MiB */
1dac3a51 SW	41	this->cmd_ctrl(mtd, (page_addr >> 16) & 0x0f,
1dac3a51 SW	42	NAND_CTRL_ALE); /* A[28:25] */
887e2ec9 SR	43	#endif
887e2ec9 SR	44	/* Latch in address */
c568f77a	45	this->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE \| NAND_CTRL_CHANGE);
887e2ec9 SR	46
	47	/*
	48	* Wait a while for the data to be ready
	49	*/
a9c847cb SR	50	while (!this->dev_ready(mtd))
a9c847cb SR	51	;
887e2ec9	52
42be56f5 SR	53	return 0;
42be56f5 SR	54	}
46f37383 SR	55	#else
	56	/*
	57	* NAND command for large page NAND devices (2k)
	58	*/
	59	static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd)
	60	{
	61	struct nand_chip *this = mtd->priv;
6d0f6bcf	62	int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
83709783 AW	63	void (hwctrl)(struct mtd_info mtd, int cmd,
83709783 AW	64	unsigned int ctrl) = this->cmd_ctrl;
46f37383	65
a9c847cb SR	66	while (!this->dev_ready(mtd))
a9c847cb SR	67	;
46f37383 SR	68
	69	/* Emulate NAND_CMD_READOOB */
	70	if (cmd == NAND_CMD_READOOB) {
6d0f6bcf	71	offs += CONFIG_SYS_NAND_PAGE_SIZE;
46f37383 SR	72	cmd = NAND_CMD_READ0;
	73	}
	74
65a9db7b AW	75	/* Shift the offset from byte addressing to word addressing. */
	76	if (this->options & NAND_BUSWIDTH_16)
	77	offs >>= 1;
	78
46f37383	79	/* Begin command latch cycle */
83709783	80	hwctrl(mtd, cmd, NAND_CTRL_CLE \| NAND_CTRL_CHANGE);
46f37383	81	/* Set ALE and clear CLE to start address cycle */
46f37383	82	/* Column address */
83709783	83	hwctrl(mtd, offs & 0xff,
4b070809	84	NAND_CTRL_ALE \| NAND_CTRL_CHANGE); /* A[7:0] */
83709783	85	hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
46f37383	86	/* Row address */
83709783 AW	87	hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
83709783 AW	88	hwctrl(mtd, ((page_addr >> 8) & 0xff),
1dac3a51	89	NAND_CTRL_ALE); /* A[27:20] */
6d0f6bcf	90	#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
46f37383	91	/* One more address cycle for devices > 128MiB */
83709783	92	hwctrl(mtd, (page_addr >> 16) & 0x0f,
1dac3a51	93	NAND_CTRL_ALE); /* A[31:28] */
46f37383 SR	94	#endif
46f37383 SR	95	/* Latch in address */
83709783	96	hwctrl(mtd, NAND_CMD_READSTART,
4b070809	97	NAND_CTRL_CLE \| NAND_CTRL_CHANGE);
83709783	98	hwctrl(mtd, NAND_CMD_NONE, NAND_NCE \| NAND_CTRL_CHANGE);
46f37383 SR	99
	100	/*
	101	* Wait a while for the data to be ready
	102	*/
a9c847cb SR	103	while (!this->dev_ready(mtd))
a9c847cb SR	104	;
46f37383 SR	105
	106	return 0;
	107	}
	108	#endif
42be56f5 SR	109
	110	static int nand_is_bad_block(struct mtd_info *mtd, int block)
	111	{
	112	struct nand_chip *this = mtd->priv;
	113
6d0f6bcf	114	nand_command(mtd, block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
42be56f5	115
887e2ec9	116	/*
eced4626	117	* Read one byte (or two if it's a 16 bit chip).
887e2ec9	118	*/
eced4626 AW	119	if (this->options & NAND_BUSWIDTH_16) {
	120	if (readw(this->IO_ADDR_R) != 0xffff)
	121	return 1;
	122	} else {
	123	if (readb(this->IO_ADDR_R) != 0xff)
	124	return 1;
	125	}
887e2ec9 SR	126
	127	return 0;
	128	}
	129
dc7cd8e5 HS	130	#if defined(CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST)
	131	static int nand_read_page(struct mtd_info mtd, int block, int page, uchar dst)
	132	{
	133	struct nand_chip *this = mtd->priv;
25efd99d SW	134	u_char ecc_calc[ECCTOTAL];
	135	u_char ecc_code[ECCTOTAL];
	136	u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
dc7cd8e5 HS	137	int i;
	138	int eccsize = CONFIG_SYS_NAND_ECCSIZE;
	139	int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
25efd99d	140	int eccsteps = ECCSTEPS;
dc7cd8e5	141	uint8_t *p = dst;
dc7cd8e5	142
dc7cd8e5 HS	143	nand_command(mtd, block, page, 0, NAND_CMD_READOOB);
	144	this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
	145	nand_command(mtd, block, page, 0, NAND_CMD_READ0);
	146
	147	/* Pick the ECC bytes out of the oob data */
25efd99d	148	for (i = 0; i < ECCTOTAL; i++)
dc7cd8e5 HS	149	ecc_code[i] = oob_data[nand_ecc_pos[i]];
	150
	151
	152	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
	153	this->ecc.hwctl(mtd, NAND_ECC_READ);
	154	this->read_buf(mtd, p, eccsize);
	155	this->ecc.calculate(mtd, p, &ecc_calc[i]);
40a0682d	156	this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
dc7cd8e5 HS	157	}
	158
	159	return 0;
	160	}
	161	#else
887e2ec9 SR	162	static int nand_read_page(struct mtd_info mtd, int block, int page, uchar dst)
887e2ec9 SR	163	{
511d0c72	164	struct nand_chip *this = mtd->priv;
25efd99d SW	165	u_char ecc_calc[ECCTOTAL];
	166	u_char ecc_code[ECCTOTAL];
	167	u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
887e2ec9	168	int i;
6d0f6bcf JCPV	169	int eccsize = CONFIG_SYS_NAND_ECCSIZE;
6d0f6bcf JCPV	170	int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
25efd99d	171	int eccsteps = ECCSTEPS;
42be56f5	172	uint8_t *p = dst;
887e2ec9	173
42be56f5	174	nand_command(mtd, block, page, 0, NAND_CMD_READ0);
887e2ec9	175
42be56f5	176	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
c568f77a	177	this->ecc.hwctl(mtd, NAND_ECC_READ);
42be56f5	178	this->read_buf(mtd, p, eccsize);
c568f77a	179	this->ecc.calculate(mtd, p, &ecc_calc[i]);
42be56f5	180	}
6d0f6bcf	181	this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
42be56f5 SR	182
42be56f5 SR	183	/* Pick the ECC bytes out of the oob data */
25efd99d	184	for (i = 0; i < ECCTOTAL; i++)
42be56f5 SR	185	ecc_code[i] = oob_data[nand_ecc_pos[i]];
42be56f5 SR	186
25efd99d	187	eccsteps = ECCSTEPS;
42be56f5 SR	188	p = dst;
	189
	190	for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
	191	/* No chance to do something with the possible error message
	192	* from correct_data(). We just hope that all possible errors
	193	* are corrected by this routine.
	194	*/
6d68621c	195	this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
42be56f5	196	}
887e2ec9 SR	197
	198	return 0;
	199	}
dc7cd8e5	200	#endif /* #if defined(CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST) */
887e2ec9	201
aa646643	202	static int nand_load(struct mtd_info *mtd, unsigned int offs,
4b070809	203	unsigned int uboot_size, uchar *dst)
887e2ec9	204	{
aa646643 GL	205	unsigned int block, lastblock;
aa646643 GL	206	unsigned int page;
887e2ec9 SR	207
887e2ec9 SR	208	/*
aa646643	209	* offs has to be aligned to a page address!
887e2ec9	210	*/
6d0f6bcf JCPV	211	block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
	212	lastblock = (offs + uboot_size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
	213	page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;
887e2ec9	214
aa646643	215	while (block <= lastblock) {
887e2ec9 SR	216	if (!nand_is_bad_block(mtd, block)) {
	217	/*
	218	* Skip bad blocks
	219	*/
6d0f6bcf	220	while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
887e2ec9	221	nand_read_page(mtd, block, page, dst);
6d0f6bcf	222	dst += CONFIG_SYS_NAND_PAGE_SIZE;
aa646643	223	page++;
887e2ec9 SR	224	}
887e2ec9 SR	225
aa646643 GL	226	page = 0;
	227	} else {
	228	lastblock++;
887e2ec9 SR	229	}
	230
	231	block++;
	232	}
	233
	234	return 0;
	235	}
	236
64852d09 SR	237	/*
	238	* The main entry for NAND booting. It's necessary that SDRAM is already
	239	* configured and available since this code loads the main U-Boot image
	240	* from NAND into SDRAM and starts it from there.
	241	*/
887e2ec9 SR	242	void nand_boot(void)
887e2ec9 SR	243	{
887e2ec9 SR	244	struct nand_chip nand_chip;
887e2ec9 SR	245	nand_info_t nand_info;
e4c09508	246	__attribute__((noreturn)) void (*uboot)(void);
887e2ec9	247
887e2ec9 SR	248	/*
	249	* Init board specific nand support
	250	*/
48571ff0	251	nand_chip.select_chip = NULL;
887e2ec9	252	nand_info.priv = &nand_chip;
6d0f6bcf	253	nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
887e2ec9	254	nand_chip.dev_ready = NULL; /* preset to NULL */
a89a9901	255	nand_chip.options = 0;
887e2ec9 SR	256	board_nand_init(&nand_chip);
887e2ec9 SR	257
aa646643 GL	258	if (nand_chip.select_chip)
	259	nand_chip.select_chip(&nand_info, 0);
	260
887e2ec9 SR	261	/*
	262	* Load U-Boot image from NAND into RAM
	263	*/
6d68621c SR	264	nand_load(&nand_info, CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
6d68621c SR	265	(uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
887e2ec9	266
b74ab737 GL	267	#ifdef CONFIG_NAND_ENV_DST
	268	nand_load(&nand_info, CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
	269	(uchar *)CONFIG_NAND_ENV_DST);
	270
	271	#ifdef CONFIG_ENV_OFFSET_REDUND
	272	nand_load(&nand_info, CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
	273	(uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
	274	#endif
	275	#endif
	276
aa646643 GL	277	if (nand_chip.select_chip)
	278	nand_chip.select_chip(&nand_info, -1);
	279
887e2ec9 SR	280	/*
	281	* Jump to U-Boot image
	282	*/
6d0f6bcf	283	uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
887e2ec9 SR	284	(*uboot)();
887e2ec9 SR	285	}