2 * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <mach/sc-regs.h>
10 #include <mach/sg-regs.h>
12 #undef DPLL_SSC_RATE_1PER
14 static void dpll_init(void)
20 * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
21 * to FOUT ( DPLLCTRL.bit[29:20] )
23 tmp
= readl(SC_DPLLCTRL
);
25 #if CONFIG_DDR_FREQ == 1600
27 #elif CONFIG_DDR_FREQ == 1333
30 # error "Unsupported frequency"
35 * Set 0x0(1%)/0x1(2%) to SSC_RATE(DPLLCTRL.bit[15])
37 #if defined(DPLL_SSC_RATE_1PER)
42 writel(tmp
, SC_DPLLCTRL
);
44 tmp
= readl(SC_DPLLCTRL2
);
45 tmp
|= SC_DPLLCTRL2_NRSTDS
;
46 writel(tmp
, SC_DPLLCTRL2
);
49 static void vpll_init(void)
51 u32 tmp
, clk_mode_axosel
;
53 /* Set VPLL27A & VPLL27B */
54 tmp
= readl(SG_PINMON0
);
55 clk_mode_axosel
= tmp
& SG_PINMON0_CLK_MODE_AXOSEL_MASK
;
57 /* 25MHz or 6.25MHz is default for Pro4R, no need to set VPLLA/B */
58 if (clk_mode_axosel
== SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ
||
59 clk_mode_axosel
== SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ
)
62 /* Disable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
63 tmp
= readl(SC_VPLL27ACTRL
);
65 writel(tmp
, SC_VPLL27ACTRL
);
66 tmp
= readl(SC_VPLL27BCTRL
);
68 writel(tmp
, SC_VPLL27BCTRL
);
70 /* Unset VPLA_K_LD and VPLB_K_LD bit */
71 tmp
= readl(SC_VPLL27ACTRL3
);
73 writel(tmp
, SC_VPLL27ACTRL3
);
74 tmp
= readl(SC_VPLL27BCTRL3
);
76 writel(tmp
, SC_VPLL27BCTRL3
);
78 /* Set VPLA_M and VPLB_M to 0x20 */
79 tmp
= readl(SC_VPLL27ACTRL2
);
82 writel(tmp
, SC_VPLL27ACTRL2
);
83 tmp
= readl(SC_VPLL27BCTRL2
);
86 writel(tmp
, SC_VPLL27BCTRL2
);
88 if (clk_mode_axosel
== SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ
||
89 clk_mode_axosel
== SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ
) {
90 /* Set VPLA_K and VPLB_K for AXO: 25MHz */
91 tmp
= readl(SC_VPLL27ACTRL3
);
94 writel(tmp
, SC_VPLL27ACTRL3
);
95 tmp
= readl(SC_VPLL27BCTRL3
);
98 writel(tmp
, SC_VPLL27BCTRL3
);
100 /* Set VPLA_K and VPLB_K for AXO: 24.576 MHz */
101 tmp
= readl(SC_VPLL27ACTRL3
);
104 writel(tmp
, SC_VPLL27ACTRL3
);
105 tmp
= readl(SC_VPLL27BCTRL3
);
108 writel(tmp
, SC_VPLL27BCTRL3
);
114 /* Set VPLA_K_LD and VPLB_K_LD to load K parameters */
115 tmp
= readl(SC_VPLL27ACTRL3
);
117 writel(tmp
, SC_VPLL27ACTRL3
);
118 tmp
= readl(SC_VPLL27BCTRL3
);
120 writel(tmp
, SC_VPLL27BCTRL3
);
122 /* Unset VPLA_SNRST and VPLB_SNRST bit */
123 tmp
= readl(SC_VPLL27ACTRL2
);
125 writel(tmp
, SC_VPLL27ACTRL2
);
126 tmp
= readl(SC_VPLL27BCTRL2
);
128 writel(tmp
, SC_VPLL27BCTRL2
);
130 /* Enable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
131 tmp
= readl(SC_VPLL27ACTRL
);
133 writel(tmp
, SC_VPLL27ACTRL
);
134 tmp
= readl(SC_VPLL27BCTRL
);
136 writel(tmp
, SC_VPLL27BCTRL
);
145 * Wait 500 usec until dpll get stable
146 * We wait 1 usec in vpll_init() so 1 usec can be saved here.