]>
git.ipfire.org Git - people/ms/u-boot.git/blob - arch/arm/mach-uniphier/umc/umc-ph1-sld8.c
2 * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <linux/sizes.h>
11 #include <mach/init.h>
12 #include <mach/umc-regs.h>
13 #include <mach/ddrphy-regs.h>
15 static void umc_start_ssif(void __iomem
*ssif_base
)
17 writel(0x00000000, ssif_base
+ 0x0000b004);
18 writel(0xffffffff, ssif_base
+ 0x0000c004);
19 writel(0x000fffcf, ssif_base
+ 0x0000c008);
20 writel(0x00000001, ssif_base
+ 0x0000b000);
21 writel(0x00000001, ssif_base
+ 0x0000c000);
22 writel(0x03010101, ssif_base
+ UMC_MDMCHSEL
);
23 writel(0x03010100, ssif_base
+ UMC_DMDCHSEL
);
25 writel(0x00000000, ssif_base
+ UMC_CLKEN_SSIF_FETCH
);
26 writel(0x00000000, ssif_base
+ UMC_CLKEN_SSIF_COMQUE0
);
27 writel(0x00000000, ssif_base
+ UMC_CLKEN_SSIF_COMWC0
);
28 writel(0x00000000, ssif_base
+ UMC_CLKEN_SSIF_COMRC0
);
29 writel(0x00000000, ssif_base
+ UMC_CLKEN_SSIF_COMQUE1
);
30 writel(0x00000000, ssif_base
+ UMC_CLKEN_SSIF_COMWC1
);
31 writel(0x00000000, ssif_base
+ UMC_CLKEN_SSIF_COMRC1
);
32 writel(0x00000000, ssif_base
+ UMC_CLKEN_SSIF_WC
);
33 writel(0x00000000, ssif_base
+ UMC_CLKEN_SSIF_RC
);
34 writel(0x00000000, ssif_base
+ UMC_CLKEN_SSIF_DST
);
36 writel(0x00000001, ssif_base
+ UMC_CPURST
);
37 writel(0x00000001, ssif_base
+ UMC_IDSRST
);
38 writel(0x00000001, ssif_base
+ UMC_IXMRST
);
39 writel(0x00000001, ssif_base
+ UMC_MDMRST
);
40 writel(0x00000001, ssif_base
+ UMC_MDDRST
);
41 writel(0x00000001, ssif_base
+ UMC_SIORST
);
42 writel(0x00000001, ssif_base
+ UMC_VIORST
);
43 writel(0x00000001, ssif_base
+ UMC_FRCRST
);
44 writel(0x00000001, ssif_base
+ UMC_RGLRST
);
45 writel(0x00000001, ssif_base
+ UMC_AIORST
);
46 writel(0x00000001, ssif_base
+ UMC_DMDRST
);
49 static void umc_dramcont_init(void __iomem
*dramcont
, void __iomem
*ca_base
,
52 #ifdef CONFIG_DDR_STANDARD
53 writel(0x55990b11, dramcont
+ UMC_CMDCTLA
);
54 writel(0x16958944, dramcont
+ UMC_CMDCTLB
);
56 writel(0x45990b11, dramcont
+ UMC_CMDCTLA
);
57 writel(0x16958924, dramcont
+ UMC_CMDCTLB
);
60 writel(0x5101046A, dramcont
+ UMC_INITCTLA
);
63 writel(0x27028B0A, dramcont
+ UMC_INITCTLB
);
65 writel(0x38028B0A, dramcont
+ UMC_INITCTLB
);
67 writel(0x00FF00FF, dramcont
+ UMC_INITCTLC
);
68 writel(0x00000b51, dramcont
+ UMC_DRMMR0
);
69 writel(0x00000006, dramcont
+ UMC_DRMMR1
);
70 writel(0x00000290, dramcont
+ UMC_DRMMR2
);
72 #ifdef CONFIG_DDR_STANDARD
73 writel(0x00000000, dramcont
+ UMC_DRMMR3
);
75 writel(0x00000800, dramcont
+ UMC_DRMMR3
);
79 writel(0x00240512, dramcont
+ UMC_SPCCTLA
);
81 writel(0x00350512, dramcont
+ UMC_SPCCTLA
);
83 writel(0x00ff0006, dramcont
+ UMC_SPCCTLB
);
84 writel(0x000a00ac, dramcont
+ UMC_RDATACTL_D0
);
85 writel(0x04060806, dramcont
+ UMC_WDATACTL_D0
);
86 writel(0x04a02000, dramcont
+ UMC_DATASET
);
87 writel(0x00000000, ca_base
+ 0x2300);
88 writel(0x00400020, dramcont
+ UMC_DCCGCTL
);
89 writel(0x00000003, dramcont
+ 0x7000);
90 writel(0x0000004f, dramcont
+ 0x8000);
91 writel(0x000000c3, dramcont
+ 0x8004);
92 writel(0x00000077, dramcont
+ 0x8008);
93 writel(0x0000003b, dramcont
+ UMC_DICGCTLA
);
94 writel(0x020a0808, dramcont
+ UMC_DICGCTLB
);
95 writel(0x00000004, dramcont
+ UMC_FLOWCTLG
);
96 writel(0x80000201, ca_base
+ 0xc20);
97 writel(0x0801e01e, dramcont
+ UMC_FLOWCTLA
);
98 writel(0x00200000, dramcont
+ UMC_FLOWCTLB
);
99 writel(0x00004444, dramcont
+ UMC_FLOWCTLC
);
100 writel(0x200a0a00, dramcont
+ UMC_SPCSETB
);
101 writel(0x00000000, dramcont
+ UMC_SPCSETD
);
102 writel(0x00000520, dramcont
+ UMC_DFICUPDCTLA
);
105 static int umc_init_sub(int freq
, int size_ch0
, int size_ch1
)
107 void __iomem
*ssif_base
= (void __iomem
*)UMC_SSIF_BASE
;
108 void __iomem
*ca_base0
= (void __iomem
*)UMC_CA_BASE(0);
109 void __iomem
*ca_base1
= (void __iomem
*)UMC_CA_BASE(1);
110 void __iomem
*dramcont0
= (void __iomem
*)UMC_DRAMCONT_BASE(0);
111 void __iomem
*dramcont1
= (void __iomem
*)UMC_DRAMCONT_BASE(1);
112 void __iomem
*phy0_0
= (void __iomem
*)DDRPHY_BASE(0, 0);
113 void __iomem
*phy1_0
= (void __iomem
*)DDRPHY_BASE(1, 0);
115 umc_dram_init_start(dramcont0
);
116 umc_dram_init_start(dramcont1
);
117 umc_dram_init_poll(dramcont0
);
118 umc_dram_init_poll(dramcont1
);
120 writel(0x00000101, dramcont0
+ UMC_DIOCTLA
);
122 ph1_sld8_ddrphy_init(phy0_0
, freq
, size_ch0
);
124 ddrphy_prepare_training(phy0_0
, 0);
125 ddrphy_training(phy0_0
);
127 writel(0x00000101, dramcont1
+ UMC_DIOCTLA
);
129 ph1_sld8_ddrphy_init(phy1_0
, freq
, size_ch1
);
131 ddrphy_prepare_training(phy1_0
, 1);
132 ddrphy_training(phy1_0
);
134 umc_dramcont_init(dramcont0
, ca_base0
, size_ch0
, freq
);
135 umc_dramcont_init(dramcont1
, ca_base1
, size_ch1
, freq
);
137 umc_start_ssif(ssif_base
);
142 int ph1_sld8_umc_init(const struct uniphier_board_data
*bd
)
144 if ((bd
->dram_ch0_size
== SZ_128M
|| bd
->dram_ch0_size
== SZ_256M
) &&
145 (bd
->dram_ch1_size
== SZ_128M
|| bd
->dram_ch1_size
== SZ_256M
) &&
146 bd
->dram_freq
== 1333 &&
147 bd
->dram_ch0_width
== 16 && bd
->dram_ch1_width
== 16) {
148 return umc_init_sub(bd
->dram_freq
,
149 bd
->dram_ch0_size
/ SZ_128M
,
150 bd
->dram_ch1_size
/ SZ_128M
);
152 pr_err("Unsupported DDR configuration\n");