arch/powerpc/include/asm/fsl_secure_boot.h

   1 /*
   2  * Copyright 2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __FSL_SECURE_BOOT_H
   8 #define __FSL_SECURE_BOOT_H
   9 #include <asm/config_mpc85xx.h>
  10
  11 #ifdef CONFIG_SECURE_BOOT
  12
  13 #ifndef CONFIG_FIT_SIGNATURE
  14 #define CONFIG_CHAIN_OF_TRUST
  15 #endif
  16
  17 #if defined(CONFIG_FSL_CORENET)
  18 #define CONFIG_SYS_PBI_FLASH_BASE               0xc0000000
  19 #elif defined(CONFIG_BSC9132QDS)
  20 #define CONFIG_SYS_PBI_FLASH_BASE               0xc8000000
  21 #elif defined(CONFIG_C29XPCIE)
  22 #define CONFIG_SYS_PBI_FLASH_BASE               0xcc000000
  23 #else
  24 #define CONFIG_SYS_PBI_FLASH_BASE               0xce000000
  25 #endif
  26 #define CONFIG_SYS_PBI_FLASH_WINDOW             0xcff80000
  27
  28 #if defined(CONFIG_B4860QDS) || \
  29         defined(CONFIG_T4240QDS) || \
  30         defined(CONFIG_T2080QDS) || \
  31         defined(CONFIG_T2080RDB) || \
  32         defined(CONFIG_T1040QDS) || \
  33         defined(CONFIG_T104xD4QDS) || \
  34         defined(CONFIG_T104xRDB) || \
  35         defined(CONFIG_T104xD4RDB) || \
  36         defined(CONFIG_PPC_T1023) || \
  37         defined(CONFIG_PPC_T1024)
  38 #ifndef CONFIG_SYS_RAMBOOT
  39 #define CONFIG_SYS_CPC_REINIT_F
  40 #endif
  41 #define CONFIG_KEY_REVOCATION
  42 #undef CONFIG_SYS_INIT_L3_ADDR
  43 #define CONFIG_SYS_INIT_L3_ADDR                 0xbff00000
  44 #endif
  45
  46 #if defined(CONFIG_RAMBOOT_PBL)
  47 #undef CONFIG_SYS_INIT_L3_ADDR
  48 #ifdef CONFIG_SYS_INIT_L3_VADDR
  49 #define CONFIG_SYS_INIT_L3_ADDR \
  50                         (CONFIG_SYS_INIT_L3_VADDR & ~0xFFF00000) | \
  51                                         0xbff00000
  52 #else
  53 #define CONFIG_SYS_INIT_L3_ADDR         0xbff00000
  54 #endif
  55 #endif
  56
  57 #if defined(CONFIG_C29XPCIE)
  58 #define CONFIG_KEY_REVOCATION
  59 #endif
  60
  61 #if defined(CONFIG_PPC_P3041)   ||      \
  62         defined(CONFIG_PPC_P4080) ||    \
  63         defined(CONFIG_PPC_P5020) ||    \
  64         defined(CONFIG_PPC_P5040) ||    \
  65         defined(CONFIG_PPC_P2041)
  66         #define CONFIG_FSL_TRUST_ARCH_v1
  67 #endif
  68
  69 #if defined(CONFIG_FSL_CORENET) && !defined(CONFIG_SYS_RAMBOOT)
  70 /* The key used for verification of next level images
  71  * is picked up from an Extension Table which has
  72  * been verified by the ISBC (Internal Secure boot Code)
  73  * in boot ROM of the SoC.
  74  * The feature is only applicable in case of NOR boot and is
  75  * not applicable in case of RAMBOOT (NAND, SD, SPI).
  76  */
  77 #define CONFIG_FSL_ISBC_KEY_EXT
  78 #endif
  79 #endif /* #ifdef CONFIG_SECURE_BOOT */
  80
  81 #ifdef CONFIG_CHAIN_OF_TRUST
  82
  83 #ifdef CONFIG_SPL_BUILD
  84 #define CONFIG_SPL_DM                   1
  85 #define CONFIG_SPL_CRYPTO_SUPPORT
  86 #define CONFIG_SPL_HASH_SUPPORT
  87 #define CONFIG_SPL_RSA
  88 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
  89 /*
  90  * PPAACT and SPAACT table for PAMU must be placed on DDR after DDR init
  91  * due to space crunch on CPC and thus malloc will not work.
  92  */
  93 #define CONFIG_SPL_PPAACT_ADDR          0x2e000000
  94 #define CONFIG_SPL_SPAACT_ADDR          0x2f000000
  95 #define CONFIG_SPL_JR0_LIODN_S          454
  96 #define CONFIG_SPL_JR0_LIODN_NS         458
  97 /*
  98  * Define the key hash for U-Boot here if public/private key pair used to
  99  * sign U-boot are different from the SRK hash put in the fuse
 100  * Example of defining KEY_HASH is
 101  * #define CONFIG_SPL_UBOOT_KEY_HASH \
 102  *      "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b"
 103  * else leave it defined as NULL
 104  */
 105
 106 #define CONFIG_SPL_UBOOT_KEY_HASH       NULL
 107 #endif /* ifdef CONFIG_SPL_BUILD */
 108
 109 #define CONFIG_CMD_ESBC_VALIDATE
 110 #define CONFIG_CMD_BLOB
 111 #define CONFIG_FSL_SEC_MON
 112 #define CONFIG_SHA_PROG_HW_ACCEL
 113 #define CONFIG_RSA_FREESCALE_EXP
 114
 115 #ifndef CONFIG_FSL_CAAM
 116 #define CONFIG_FSL_CAAM
 117 #endif
 118
 119 #ifndef CONFIG_SPL_BUILD
 120 /*
 121  * fsl_setenv_chain_of_trust() must be called from
 122  * board_late_init()
 123  */
 124 #ifndef CONFIG_BOARD_LATE_INIT
 125 #define CONFIG_BOARD_LATE_INIT
 126 #endif
 127
 128 /* If Boot Script is not on NOR and is required to be copied on RAM */
 129 #ifdef CONFIG_BOOTSCRIPT_COPY_RAM
 130 #define CONFIG_BS_HDR_ADDR_RAM          0x00010000
 131 #define CONFIG_BS_HDR_ADDR_DEVICE       0x00800000
 132 #define CONFIG_BS_HDR_SIZE              0x00002000
 133 #define CONFIG_BS_ADDR_RAM              0x00012000
 134 #define CONFIG_BS_ADDR_DEVICE           0x00802000
 135 #define CONFIG_BS_SIZE                  0x00001000
 136
 137 #define CONFIG_BOOTSCRIPT_HDR_ADDR      CONFIG_BS_HDR_ADDR_RAM
 138 #else
 139
 140 /* The bootscript header address is different for B4860 because the NOR
 141  * mapping is different on B4 due to reduced NOR size.
 142  */
 143 #if defined(CONFIG_B4860QDS)
 144 #define CONFIG_BOOTSCRIPT_HDR_ADDR      0xecc00000
 145 #elif defined(CONFIG_FSL_CORENET)
 146 #define CONFIG_BOOTSCRIPT_HDR_ADDR      0xe8e00000
 147 #elif defined(CONFIG_BSC9132QDS)
 148 #define CONFIG_BOOTSCRIPT_HDR_ADDR      0x88020000
 149 #elif defined(CONFIG_C29XPCIE)
 150 #define CONFIG_BOOTSCRIPT_HDR_ADDR      0xec020000
 151 #else
 152 #define CONFIG_BOOTSCRIPT_HDR_ADDR      0xee020000
 153 #endif
 154
 155 #endif /* #ifdef CONFIG_BOOTSCRIPT_COPY_RAM */
 156
 157 #include <config_fsl_chain_trust.h>
 158 #endif /* #ifndef CONFIG_SPL_BUILD */
 159 #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */
 160 #endif