arch/powerpc/include/asm/fsl_secure_boot.h

   1 /*
   2  * Copyright 2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __FSL_SECURE_BOOT_H
   8 #define __FSL_SECURE_BOOT_H
   9 #include <asm/config_mpc85xx.h>
  10
  11 #ifdef CONFIG_SECURE_BOOT
  12
  13 #ifndef CONFIG_FIT_SIGNATURE
  14 #define CONFIG_CHAIN_OF_TRUST
  15 #endif
  16
  17 #if defined(CONFIG_FSL_CORENET)
  18 #define CONFIG_SYS_PBI_FLASH_BASE               0xc0000000
  19 #elif defined(CONFIG_TARGET_BSC9132QDS)
  20 #define CONFIG_SYS_PBI_FLASH_BASE               0xc8000000
  21 #elif defined(CONFIG_TARGET_C29XPCIE)
  22 #define CONFIG_SYS_PBI_FLASH_BASE               0xcc000000
  23 #else
  24 #define CONFIG_SYS_PBI_FLASH_BASE               0xce000000
  25 #endif
  26 #define CONFIG_SYS_PBI_FLASH_WINDOW             0xcff80000
  27
  28 #if defined(CONFIG_TARGET_B4860QDS) || \
  29         defined(CONFIG_TARGET_B4420QDS) || \
  30         defined(CONFIG_T4240QDS) || \
  31         defined(CONFIG_T2080QDS) || \
  32         defined(CONFIG_T2080RDB) || \
  33         defined(CONFIG_T1040QDS) || \
  34         defined(CONFIG_T104xD4QDS) || \
  35         defined(CONFIG_T104xRDB) || \
  36         defined(CONFIG_T104xD4RDB) || \
  37         defined(CONFIG_PPC_T1023) || \
  38         defined(CONFIG_PPC_T1024)
  39 #ifndef CONFIG_SYS_RAMBOOT
  40 #define CONFIG_SYS_CPC_REINIT_F
  41 #endif
  42 #define CONFIG_KEY_REVOCATION
  43 #undef CONFIG_SYS_INIT_L3_ADDR
  44 #define CONFIG_SYS_INIT_L3_ADDR                 0xbff00000
  45 #endif
  46
  47 #if defined(CONFIG_RAMBOOT_PBL)
  48 #undef CONFIG_SYS_INIT_L3_ADDR
  49 #ifdef CONFIG_SYS_INIT_L3_VADDR
  50 #define CONFIG_SYS_INIT_L3_ADDR \
  51                         (CONFIG_SYS_INIT_L3_VADDR & ~0xFFF00000) | \
  52                                         0xbff00000
  53 #else
  54 #define CONFIG_SYS_INIT_L3_ADDR         0xbff00000
  55 #endif
  56 #endif
  57
  58 #if defined(CONFIG_TARGET_C29XPCIE)
  59 #define CONFIG_KEY_REVOCATION
  60 #endif
  61
  62 #if defined(CONFIG_ARCH_P3041)  ||      \
  63         defined(CONFIG_ARCH_P4080) ||   \
  64         defined(CONFIG_ARCH_P5020) ||   \
  65         defined(CONFIG_ARCH_P5040) ||   \
  66         defined(CONFIG_ARCH_P2041)
  67         #define CONFIG_FSL_TRUST_ARCH_v1
  68 #endif
  69
  70 #if defined(CONFIG_FSL_CORENET) && !defined(CONFIG_SYS_RAMBOOT)
  71 /* The key used for verification of next level images
  72  * is picked up from an Extension Table which has
  73  * been verified by the ISBC (Internal Secure boot Code)
  74  * in boot ROM of the SoC.
  75  * The feature is only applicable in case of NOR boot and is
  76  * not applicable in case of RAMBOOT (NAND, SD, SPI).
  77  */
  78 #define CONFIG_FSL_ISBC_KEY_EXT
  79 #endif
  80 #endif /* #ifdef CONFIG_SECURE_BOOT */
  81
  82 #ifdef CONFIG_CHAIN_OF_TRUST
  83 #ifdef CONFIG_SPL_BUILD
  84 /*
  85  * PPAACT and SPAACT table for PAMU must be placed on DDR after DDR init
  86  * due to space crunch on CPC and thus malloc will not work.
  87  */
  88 #define CONFIG_SPL_PPAACT_ADDR          0x2e000000
  89 #define CONFIG_SPL_SPAACT_ADDR          0x2f000000
  90 #define CONFIG_SPL_JR0_LIODN_S          454
  91 #define CONFIG_SPL_JR0_LIODN_NS         458
  92 /*
  93  * Define the key hash for U-Boot here if public/private key pair used to
  94  * sign U-boot are different from the SRK hash put in the fuse
  95  * Example of defining KEY_HASH is
  96  * #define CONFIG_SPL_UBOOT_KEY_HASH \
  97  *      "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b"
  98  * else leave it defined as NULL
  99  */
 100
 101 #define CONFIG_SPL_UBOOT_KEY_HASH       NULL
 102 #endif /* ifdef CONFIG_SPL_BUILD */
 103
 104 #define CONFIG_CMD_ESBC_VALIDATE
 105 #define CONFIG_CMD_BLOB
 106 #define CONFIG_FSL_SEC_MON
 107 #define CONFIG_SHA_PROG_HW_ACCEL
 108 #define CONFIG_RSA_FREESCALE_EXP
 109
 110 #ifndef CONFIG_FSL_CAAM
 111 #define CONFIG_FSL_CAAM
 112 #endif
 113
 114 #ifndef CONFIG_SPL_BUILD
 115 /*
 116  * fsl_setenv_chain_of_trust() must be called from
 117  * board_late_init()
 118  */
 119 #ifndef CONFIG_BOARD_LATE_INIT
 120 #define CONFIG_BOARD_LATE_INIT
 121 #endif
 122
 123 /* If Boot Script is not on NOR and is required to be copied on RAM */
 124 #ifdef CONFIG_BOOTSCRIPT_COPY_RAM
 125 #define CONFIG_BS_HDR_ADDR_RAM          0x00010000
 126 #define CONFIG_BS_HDR_ADDR_DEVICE       0x00800000
 127 #define CONFIG_BS_HDR_SIZE              0x00002000
 128 #define CONFIG_BS_ADDR_RAM              0x00012000
 129 #define CONFIG_BS_ADDR_DEVICE           0x00802000
 130 #define CONFIG_BS_SIZE                  0x00001000
 131
 132 #define CONFIG_BOOTSCRIPT_HDR_ADDR      CONFIG_BS_HDR_ADDR_RAM
 133 #else
 134
 135 /* The bootscript header address is different for B4860 because the NOR
 136  * mapping is different on B4 due to reduced NOR size.
 137  */
 138 #if defined(CONFIG_TARGET_B4860QDS) || defined(CONFIG_TARGET_B4420QDS)
 139 #define CONFIG_BOOTSCRIPT_HDR_ADDR      0xecc00000
 140 #elif defined(CONFIG_FSL_CORENET)
 141 #define CONFIG_BOOTSCRIPT_HDR_ADDR      0xe8e00000
 142 #elif defined(CONFIG_TARGET_BSC9132QDS)
 143 #define CONFIG_BOOTSCRIPT_HDR_ADDR      0x88020000
 144 #elif defined(CONFIG_TARGET_C29XPCIE)
 145 #define CONFIG_BOOTSCRIPT_HDR_ADDR      0xec020000
 146 #else
 147 #define CONFIG_BOOTSCRIPT_HDR_ADDR      0xee020000
 148 #endif
 149
 150 #endif /* #ifdef CONFIG_BOOTSCRIPT_COPY_RAM */
 151
 152 #include <config_fsl_chain_trust.h>
 153 #endif /* #ifndef CONFIG_SPL_BUILD */
 154 #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */
 155 #endif