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Driver/DDR: Moving Freescale DDR driver to a common driver
[people/ms/u-boot.git] / arch / powerpc / include / asm / immap_85xx.h
1 /*
2 * MPC85xx Internal Memory Map
3 *
4 * Copyright 2007-2012 Freescale Semiconductor, Inc.
5 *
6 * Copyright(c) 2002,2003 Motorola Inc.
7 * Xianghua Xiao (x.xiao@motorola.com)
8 *
9 * SPDX-License-Identifier: GPL-2.0+
10 */
11
12 #ifndef __IMMAP_85xx__
13 #define __IMMAP_85xx__
14
15 #include <asm/types.h>
16 #include <asm/fsl_dma.h>
17 #include <asm/fsl_i2c.h>
18 #include <asm/fsl_ifc.h>
19 #include <asm/fsl_lbc.h>
20 #include <asm/fsl_fman.h>
21
22 typedef struct ccsr_local {
23 u32 ccsrbarh; /* CCSR Base Addr High */
24 u32 ccsrbarl; /* CCSR Base Addr Low */
25 u32 ccsrar; /* CCSR Attr */
26 #define CCSRAR_C 0x80000000 /* Commit */
27 u8 res1[4];
28 u32 altcbarh; /* Alternate Configuration Base Addr High */
29 u32 altcbarl; /* Alternate Configuration Base Addr Low */
30 u32 altcar; /* Alternate Configuration Attr */
31 u8 res2[4];
32 u32 bstrh; /* Boot space translation high */
33 u32 bstrl; /* Boot space translation Low */
34 u32 bstrar; /* Boot space translation attributes */
35 u8 res3[0xbd4];
36 struct {
37 u32 lawbarh; /* LAWn base addr high */
38 u32 lawbarl; /* LAWn base addr low */
39 u32 lawar; /* LAWn attributes */
40 u8 res4[4];
41 } law[32];
42 u8 res35[0x204];
43 } ccsr_local_t;
44
45 /* Local-Access Registers & ECM Registers */
46 typedef struct ccsr_local_ecm {
47 u32 ccsrbar; /* CCSR Base Addr */
48 u8 res1[4];
49 u32 altcbar; /* Alternate Configuration Base Addr */
50 u8 res2[4];
51 u32 altcar; /* Alternate Configuration Attr */
52 u8 res3[12];
53 u32 bptr; /* Boot Page Translation */
54 u8 res4[3044];
55 u32 lawbar0; /* Local Access Window 0 Base Addr */
56 u8 res5[4];
57 u32 lawar0; /* Local Access Window 0 Attrs */
58 u8 res6[20];
59 u32 lawbar1; /* Local Access Window 1 Base Addr */
60 u8 res7[4];
61 u32 lawar1; /* Local Access Window 1 Attrs */
62 u8 res8[20];
63 u32 lawbar2; /* Local Access Window 2 Base Addr */
64 u8 res9[4];
65 u32 lawar2; /* Local Access Window 2 Attrs */
66 u8 res10[20];
67 u32 lawbar3; /* Local Access Window 3 Base Addr */
68 u8 res11[4];
69 u32 lawar3; /* Local Access Window 3 Attrs */
70 u8 res12[20];
71 u32 lawbar4; /* Local Access Window 4 Base Addr */
72 u8 res13[4];
73 u32 lawar4; /* Local Access Window 4 Attrs */
74 u8 res14[20];
75 u32 lawbar5; /* Local Access Window 5 Base Addr */
76 u8 res15[4];
77 u32 lawar5; /* Local Access Window 5 Attrs */
78 u8 res16[20];
79 u32 lawbar6; /* Local Access Window 6 Base Addr */
80 u8 res17[4];
81 u32 lawar6; /* Local Access Window 6 Attrs */
82 u8 res18[20];
83 u32 lawbar7; /* Local Access Window 7 Base Addr */
84 u8 res19[4];
85 u32 lawar7; /* Local Access Window 7 Attrs */
86 u8 res19_8a[20];
87 u32 lawbar8; /* Local Access Window 8 Base Addr */
88 u8 res19_8b[4];
89 u32 lawar8; /* Local Access Window 8 Attrs */
90 u8 res19_9a[20];
91 u32 lawbar9; /* Local Access Window 9 Base Addr */
92 u8 res19_9b[4];
93 u32 lawar9; /* Local Access Window 9 Attrs */
94 u8 res19_10a[20];
95 u32 lawbar10; /* Local Access Window 10 Base Addr */
96 u8 res19_10b[4];
97 u32 lawar10; /* Local Access Window 10 Attrs */
98 u8 res19_11a[20];
99 u32 lawbar11; /* Local Access Window 11 Base Addr */
100 u8 res19_11b[4];
101 u32 lawar11; /* Local Access Window 11 Attrs */
102 u8 res20[652];
103 u32 eebacr; /* ECM CCB Addr Configuration */
104 u8 res21[12];
105 u32 eebpcr; /* ECM CCB Port Configuration */
106 u8 res22[3564];
107 u32 eedr; /* ECM Error Detect */
108 u8 res23[4];
109 u32 eeer; /* ECM Error Enable */
110 u32 eeatr; /* ECM Error Attrs Capture */
111 u32 eeadr; /* ECM Error Addr Capture */
112 u8 res24[492];
113 } ccsr_local_ecm_t;
114
115 /* DDR memory controller registers */
116 typedef struct ccsr_ddr {
117 u32 cs0_bnds; /* Chip Select 0 Memory Bounds */
118 u8 res1[4];
119 u32 cs1_bnds; /* Chip Select 1 Memory Bounds */
120 u8 res2[4];
121 u32 cs2_bnds; /* Chip Select 2 Memory Bounds */
122 u8 res3[4];
123 u32 cs3_bnds; /* Chip Select 3 Memory Bounds */
124 u8 res4[100];
125 u32 cs0_config; /* Chip Select Configuration */
126 u32 cs1_config; /* Chip Select Configuration */
127 u32 cs2_config; /* Chip Select Configuration */
128 u32 cs3_config; /* Chip Select Configuration */
129 u8 res4a[48];
130 u32 cs0_config_2; /* Chip Select Configuration 2 */
131 u32 cs1_config_2; /* Chip Select Configuration 2 */
132 u32 cs2_config_2; /* Chip Select Configuration 2 */
133 u32 cs3_config_2; /* Chip Select Configuration 2 */
134 u8 res5[48];
135 u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */
136 u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */
137 u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */
138 u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */
139 u32 sdram_cfg; /* SDRAM Control Configuration */
140 u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */
141 u32 sdram_mode; /* SDRAM Mode Configuration */
142 u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */
143 u32 sdram_md_cntl; /* SDRAM Mode Control */
144 u32 sdram_interval; /* SDRAM Interval Configuration */
145 u32 sdram_data_init; /* SDRAM Data initialization */
146 u8 res6[4];
147 u32 sdram_clk_cntl; /* SDRAM Clock Control */
148 u8 res7[20];
149 u32 init_addr; /* training init addr */
150 u32 init_ext_addr; /* training init extended addr */
151 u8 res8_1[16];
152 u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */
153 u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */
154 u8 reg8_1a[8];
155 u32 ddr_zq_cntl; /* ZQ calibration control*/
156 u32 ddr_wrlvl_cntl; /* write leveling control*/
157 u8 reg8_1aa[4];
158 u32 ddr_sr_cntr; /* self refresh counter */
159 u32 ddr_sdram_rcw_1; /* Control Words 1 */
160 u32 ddr_sdram_rcw_2; /* Control Words 2 */
161 u8 reg_1ab[8];
162 u32 ddr_wrlvl_cntl_2; /* write leveling control 2 */
163 u32 ddr_wrlvl_cntl_3; /* write leveling control 3 */
164 u8 res8_1b[104];
165 u32 sdram_mode_3; /* SDRAM Mode Configuration 3 */
166 u32 sdram_mode_4; /* SDRAM Mode Configuration 4 */
167 u32 sdram_mode_5; /* SDRAM Mode Configuration 5 */
168 u32 sdram_mode_6; /* SDRAM Mode Configuration 6 */
169 u32 sdram_mode_7; /* SDRAM Mode Configuration 7 */
170 u32 sdram_mode_8; /* SDRAM Mode Configuration 8 */
171 u8 res8_1ba[0x908];
172 u32 ddr_dsr1; /* Debug Status 1 */
173 u32 ddr_dsr2; /* Debug Status 2 */
174 u32 ddr_cdr1; /* Control Driver 1 */
175 u32 ddr_cdr2; /* Control Driver 2 */
176 u8 res8_1c[200];
177 u32 ip_rev1; /* IP Block Revision 1 */
178 u32 ip_rev2; /* IP Block Revision 2 */
179 u32 eor; /* Enhanced Optimization Register */
180 u8 res8_2[252];
181 u32 mtcr; /* Memory Test Control Register */
182 u8 res8_3[28];
183 u32 mtp1; /* Memory Test Pattern 1 */
184 u32 mtp2; /* Memory Test Pattern 2 */
185 u32 mtp3; /* Memory Test Pattern 3 */
186 u32 mtp4; /* Memory Test Pattern 4 */
187 u32 mtp5; /* Memory Test Pattern 5 */
188 u32 mtp6; /* Memory Test Pattern 6 */
189 u32 mtp7; /* Memory Test Pattern 7 */
190 u32 mtp8; /* Memory Test Pattern 8 */
191 u32 mtp9; /* Memory Test Pattern 9 */
192 u32 mtp10; /* Memory Test Pattern 10 */
193 u8 res8_4[184];
194 u32 data_err_inject_hi; /* Data Path Err Injection Mask High */
195 u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */
196 u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */
197 u8 res9[20];
198 u32 capture_data_hi; /* Data Path Read Capture High */
199 u32 capture_data_lo; /* Data Path Read Capture Low */
200 u32 capture_ecc; /* Data Path Read Capture ECC */
201 u8 res10[20];
202 u32 err_detect; /* Error Detect */
203 u32 err_disable; /* Error Disable */
204 u32 err_int_en;
205 u32 capture_attributes; /* Error Attrs Capture */
206 u32 capture_address; /* Error Addr Capture */
207 u32 capture_ext_address; /* Error Extended Addr Capture */
208 u32 err_sbe; /* Single-Bit ECC Error Management */
209 u8 res11[164];
210 u32 debug[32]; /* debug_1 to debug_32 */
211 u8 res12[128];
212 } ccsr_ddr_t;
213
214 #define DDR_EOR_RD_BDW_OPT_DIS 0x80000000 /* Read BDW Opt. disable */
215 #define DDR_EOR_ADDR_HASH_EN 0x40000000 /* Address hash enabled */
216
217 /* I2C Registers */
218 typedef struct ccsr_i2c {
219 struct fsl_i2c i2c[1];
220 u8 res[4096 - 1 * sizeof(struct fsl_i2c)];
221 } ccsr_i2c_t;
222
223 #if defined(CONFIG_MPC8540) \
224 || defined(CONFIG_MPC8541) \
225 || defined(CONFIG_MPC8548) \
226 || defined(CONFIG_MPC8555)
227 /* DUART Registers */
228 typedef struct ccsr_duart {
229 u8 res1[1280];
230 /* URBR1, UTHR1, UDLB1 with the same addr */
231 u8 urbr1_uthr1_udlb1;
232 /* UIER1, UDMB1 with the same addr01 */
233 u8 uier1_udmb1;
234 /* UIIR1, UFCR1, UAFR1 with the same addr */
235 u8 uiir1_ufcr1_uafr1;
236 u8 ulcr1; /* UART1 Line Control */
237 u8 umcr1; /* UART1 Modem Control */
238 u8 ulsr1; /* UART1 Line Status */
239 u8 umsr1; /* UART1 Modem Status */
240 u8 uscr1; /* UART1 Scratch */
241 u8 res2[8];
242 u8 udsr1; /* UART1 DMA Status */
243 u8 res3[239];
244 /* URBR2, UTHR2, UDLB2 with the same addr */
245 u8 urbr2_uthr2_udlb2;
246 /* UIER2, UDMB2 with the same addr */
247 u8 uier2_udmb2;
248 /* UIIR2, UFCR2, UAFR2 with the same addr */
249 u8 uiir2_ufcr2_uafr2;
250 u8 ulcr2; /* UART2 Line Control */
251 u8 umcr2; /* UART2 Modem Control */
252 u8 ulsr2; /* UART2 Line Status */
253 u8 umsr2; /* UART2 Modem Status */
254 u8 uscr2; /* UART2 Scratch */
255 u8 res4[8];
256 u8 udsr2; /* UART2 DMA Status */
257 u8 res5[2543];
258 } ccsr_duart_t;
259 #else /* MPC8560 uses UART on its CPM */
260 typedef struct ccsr_duart {
261 u8 res[4096];
262 } ccsr_duart_t;
263 #endif
264
265 /* eSPI Registers */
266 typedef struct ccsr_espi {
267 u32 mode; /* eSPI mode */
268 u32 event; /* eSPI event */
269 u32 mask; /* eSPI mask */
270 u32 com; /* eSPI command */
271 u32 tx; /* eSPI transmit FIFO access */
272 u32 rx; /* eSPI receive FIFO access */
273 u8 res1[8]; /* reserved */
274 u32 csmode[4]; /* 0x2c: sSPI CS0/1/2/3 mode */
275 u8 res2[4048]; /* fill up to 0x1000 */
276 } ccsr_espi_t;
277
278 /* PCI Registers */
279 typedef struct ccsr_pcix {
280 u32 cfg_addr; /* PCIX Configuration Addr */
281 u32 cfg_data; /* PCIX Configuration Data */
282 u32 int_ack; /* PCIX IRQ Acknowledge */
283 u8 res000c[52];
284 u32 liodn_base; /* PCIX LIODN base register */
285 u8 res0044[2996];
286 u32 ipver1; /* PCIX IP block revision register 1 */
287 u32 ipver2; /* PCIX IP block revision register 2 */
288 u32 potar0; /* PCIX Outbound Transaction Addr 0 */
289 u32 potear0; /* PCIX Outbound Translation Extended Addr 0 */
290 u32 powbar0; /* PCIX Outbound Window Base Addr 0 */
291 u32 powbear0; /* PCIX Outbound Window Base Extended Addr 0 */
292 u32 powar0; /* PCIX Outbound Window Attrs 0 */
293 u8 res2[12];
294 u32 potar1; /* PCIX Outbound Transaction Addr 1 */
295 u32 potear1; /* PCIX Outbound Translation Extended Addr 1 */
296 u32 powbar1; /* PCIX Outbound Window Base Addr 1 */
297 u32 powbear1; /* PCIX Outbound Window Base Extended Addr 1 */
298 u32 powar1; /* PCIX Outbound Window Attrs 1 */
299 u8 res3[12];
300 u32 potar2; /* PCIX Outbound Transaction Addr 2 */
301 u32 potear2; /* PCIX Outbound Translation Extended Addr 2 */
302 u32 powbar2; /* PCIX Outbound Window Base Addr 2 */
303 u32 powbear2; /* PCIX Outbound Window Base Extended Addr 2 */
304 u32 powar2; /* PCIX Outbound Window Attrs 2 */
305 u8 res4[12];
306 u32 potar3; /* PCIX Outbound Transaction Addr 3 */
307 u32 potear3; /* PCIX Outbound Translation Extended Addr 3 */
308 u32 powbar3; /* PCIX Outbound Window Base Addr 3 */
309 u32 powbear3; /* PCIX Outbound Window Base Extended Addr 3 */
310 u32 powar3; /* PCIX Outbound Window Attrs 3 */
311 u8 res5[12];
312 u32 potar4; /* PCIX Outbound Transaction Addr 4 */
313 u32 potear4; /* PCIX Outbound Translation Extended Addr 4 */
314 u32 powbar4; /* PCIX Outbound Window Base Addr 4 */
315 u32 powbear4; /* PCIX Outbound Window Base Extended Addr 4 */
316 u32 powar4; /* PCIX Outbound Window Attrs 4 */
317 u8 res6[268];
318 u32 pitar3; /* PCIX Inbound Translation Addr 3 */
319 u32 pitear3; /* PCIX Inbound Translation Extended Addr 3 */
320 u32 piwbar3; /* PCIX Inbound Window Base Addr 3 */
321 u32 piwbear3; /* PCIX Inbound Window Base Extended Addr 3 */
322 u32 piwar3; /* PCIX Inbound Window Attrs 3 */
323 u8 res7[12];
324 u32 pitar2; /* PCIX Inbound Translation Addr 2 */
325 u32 pitear2; /* PCIX Inbound Translation Extended Addr 2 */
326 u32 piwbar2; /* PCIX Inbound Window Base Addr 2 */
327 u32 piwbear2; /* PCIX Inbound Window Base Extended Addr 2 */
328 u32 piwar2; /* PCIX Inbound Window Attrs 2 */
329 u8 res8[12];
330 u32 pitar1; /* PCIX Inbound Translation Addr 1 */
331 u32 pitear1; /* PCIX Inbound Translation Extended Addr 1 */
332 u32 piwbar1; /* PCIX Inbound Window Base Addr 1 */
333 u8 res9[4];
334 u32 piwar1; /* PCIX Inbound Window Attrs 1 */
335 u8 res10[12];
336 u32 pedr; /* PCIX Error Detect */
337 u32 pecdr; /* PCIX Error Capture Disable */
338 u32 peer; /* PCIX Error Enable */
339 u32 peattrcr; /* PCIX Error Attrs Capture */
340 u32 peaddrcr; /* PCIX Error Addr Capture */
341 u32 peextaddrcr; /* PCIX Error Extended Addr Capture */
342 u32 pedlcr; /* PCIX Error Data Low Capture */
343 u32 pedhcr; /* PCIX Error Error Data High Capture */
344 u32 gas_timr; /* PCIX Gasket Timer */
345 u8 res11[476];
346 } ccsr_pcix_t;
347
348 #define PCIX_COMMAND 0x62
349 #define POWAR_EN 0x80000000
350 #define POWAR_IO_READ 0x00080000
351 #define POWAR_MEM_READ 0x00040000
352 #define POWAR_IO_WRITE 0x00008000
353 #define POWAR_MEM_WRITE 0x00004000
354 #define POWAR_MEM_512M 0x0000001c
355 #define POWAR_IO_1M 0x00000013
356
357 #define PIWAR_EN 0x80000000
358 #define PIWAR_PF 0x20000000
359 #define PIWAR_LOCAL 0x00f00000
360 #define PIWAR_READ_SNOOP 0x00050000
361 #define PIWAR_WRITE_SNOOP 0x00005000
362 #define PIWAR_MEM_2G 0x0000001e
363
364 typedef struct ccsr_gpio {
365 u32 gpdir;
366 u32 gpodr;
367 u32 gpdat;
368 u32 gpier;
369 u32 gpimr;
370 u32 gpicr;
371 } ccsr_gpio_t;
372
373 /* L2 Cache Registers */
374 typedef struct ccsr_l2cache {
375 u32 l2ctl; /* L2 configuration 0 */
376 u8 res1[12];
377 u32 l2cewar0; /* L2 cache external write addr 0 */
378 u8 res2[4];
379 u32 l2cewcr0; /* L2 cache external write control 0 */
380 u8 res3[4];
381 u32 l2cewar1; /* L2 cache external write addr 1 */
382 u8 res4[4];
383 u32 l2cewcr1; /* L2 cache external write control 1 */
384 u8 res5[4];
385 u32 l2cewar2; /* L2 cache external write addr 2 */
386 u8 res6[4];
387 u32 l2cewcr2; /* L2 cache external write control 2 */
388 u8 res7[4];
389 u32 l2cewar3; /* L2 cache external write addr 3 */
390 u8 res8[4];
391 u32 l2cewcr3; /* L2 cache external write control 3 */
392 u8 res9[180];
393 u32 l2srbar0; /* L2 memory-mapped SRAM base addr 0 */
394 u8 res10[4];
395 u32 l2srbar1; /* L2 memory-mapped SRAM base addr 1 */
396 u8 res11[3316];
397 u32 l2errinjhi; /* L2 error injection mask high */
398 u32 l2errinjlo; /* L2 error injection mask low */
399 u32 l2errinjctl; /* L2 error injection tag/ECC control */
400 u8 res12[20];
401 u32 l2captdatahi; /* L2 error data high capture */
402 u32 l2captdatalo; /* L2 error data low capture */
403 u32 l2captecc; /* L2 error ECC capture */
404 u8 res13[20];
405 u32 l2errdet; /* L2 error detect */
406 u32 l2errdis; /* L2 error disable */
407 u32 l2errinten; /* L2 error interrupt enable */
408 u32 l2errattr; /* L2 error attributes capture */
409 u32 l2erraddr; /* L2 error addr capture */
410 u8 res14[4];
411 u32 l2errctl; /* L2 error control */
412 u8 res15[420];
413 } ccsr_l2cache_t;
414
415 #define MPC85xx_L2CTL_L2E 0x80000000
416 #define MPC85xx_L2CTL_L2SRAM_ENTIRE 0x00010000
417 #define MPC85xx_L2ERRDIS_MBECC 0x00000008
418 #define MPC85xx_L2ERRDIS_SBECC 0x00000004
419
420 /* DMA Registers */
421 typedef struct ccsr_dma {
422 u8 res1[256];
423 struct fsl_dma dma[4];
424 u32 dgsr; /* DMA General Status */
425 u8 res2[11516];
426 } ccsr_dma_t;
427
428 /* tsec */
429 typedef struct ccsr_tsec {
430 u8 res1[16];
431 u32 ievent; /* IRQ Event */
432 u32 imask; /* IRQ Mask */
433 u32 edis; /* Error Disabled */
434 u8 res2[4];
435 u32 ecntrl; /* Ethernet Control */
436 u32 minflr; /* Minimum Frame Len */
437 u32 ptv; /* Pause Time Value */
438 u32 dmactrl; /* DMA Control */
439 u32 tbipa; /* TBI PHY Addr */
440 u8 res3[88];
441 u32 fifo_tx_thr; /* FIFO transmit threshold */
442 u8 res4[8];
443 u32 fifo_tx_starve; /* FIFO transmit starve */
444 u32 fifo_tx_starve_shutoff; /* FIFO transmit starve shutoff */
445 u8 res5[96];
446 u32 tctrl; /* TX Control */
447 u32 tstat; /* TX Status */
448 u8 res6[4];
449 u32 tbdlen; /* TX Buffer Desc Data Len */
450 u8 res7[16];
451 u32 ctbptrh; /* Current TX Buffer Desc Ptr High */
452 u32 ctbptr; /* Current TX Buffer Desc Ptr */
453 u8 res8[88];
454 u32 tbptrh; /* TX Buffer Desc Ptr High */
455 u32 tbptr; /* TX Buffer Desc Ptr Low */
456 u8 res9[120];
457 u32 tbaseh; /* TX Desc Base Addr High */
458 u32 tbase; /* TX Desc Base Addr */
459 u8 res10[168];
460 u32 ostbd; /* Out-of-Sequence(OOS) TX Buffer Desc */
461 u32 ostbdp; /* OOS TX Data Buffer Ptr */
462 u32 os32tbdp; /* OOS 32 Bytes TX Data Buffer Ptr Low */
463 u32 os32iptrh; /* OOS 32 Bytes TX Insert Ptr High */
464 u32 os32iptrl; /* OOS 32 Bytes TX Insert Ptr Low */
465 u32 os32tbdr; /* OOS 32 Bytes TX Reserved */
466 u32 os32iil; /* OOS 32 Bytes TX Insert Idx/Len */
467 u8 res11[52];
468 u32 rctrl; /* RX Control */
469 u32 rstat; /* RX Status */
470 u8 res12[4];
471 u32 rbdlen; /* RxBD Data Len */
472 u8 res13[16];
473 u32 crbptrh; /* Current RX Buffer Desc Ptr High */
474 u32 crbptr; /* Current RX Buffer Desc Ptr */
475 u8 res14[24];
476 u32 mrblr; /* Maximum RX Buffer Len */
477 u32 mrblr2r3; /* Maximum RX Buffer Len R2R3 */
478 u8 res15[56];
479 u32 rbptrh; /* RX Buffer Desc Ptr High 0 */
480 u32 rbptr; /* RX Buffer Desc Ptr */
481 u32 rbptrh1; /* RX Buffer Desc Ptr High 1 */
482 u32 rbptrl1; /* RX Buffer Desc Ptr Low 1 */
483 u32 rbptrh2; /* RX Buffer Desc Ptr High 2 */
484 u32 rbptrl2; /* RX Buffer Desc Ptr Low 2 */
485 u32 rbptrh3; /* RX Buffer Desc Ptr High 3 */
486 u32 rbptrl3; /* RX Buffer Desc Ptr Low 3 */
487 u8 res16[96];
488 u32 rbaseh; /* RX Desc Base Addr High 0 */
489 u32 rbase; /* RX Desc Base Addr */
490 u32 rbaseh1; /* RX Desc Base Addr High 1 */
491 u32 rbasel1; /* RX Desc Base Addr Low 1 */
492 u32 rbaseh2; /* RX Desc Base Addr High 2 */
493 u32 rbasel2; /* RX Desc Base Addr Low 2 */
494 u32 rbaseh3; /* RX Desc Base Addr High 3 */
495 u32 rbasel3; /* RX Desc Base Addr Low 3 */
496 u8 res17[224];
497 u32 maccfg1; /* MAC Configuration 1 */
498 u32 maccfg2; /* MAC Configuration 2 */
499 u32 ipgifg; /* Inter Packet Gap/Inter Frame Gap */
500 u32 hafdup; /* Half Duplex */
501 u32 maxfrm; /* Maximum Frame Len */
502 u8 res18[12];
503 u32 miimcfg; /* MII Management Configuration */
504 u32 miimcom; /* MII Management Cmd */
505 u32 miimadd; /* MII Management Addr */
506 u32 miimcon; /* MII Management Control */
507 u32 miimstat; /* MII Management Status */
508 u32 miimind; /* MII Management Indicator */
509 u8 res19[4];
510 u32 ifstat; /* Interface Status */
511 u32 macstnaddr1; /* Station Addr Part 1 */
512 u32 macstnaddr2; /* Station Addr Part 2 */
513 u8 res20[312];
514 u32 tr64; /* TX & RX 64-byte Frame Counter */
515 u32 tr127; /* TX & RX 65-127 byte Frame Counter */
516 u32 tr255; /* TX & RX 128-255 byte Frame Counter */
517 u32 tr511; /* TX & RX 256-511 byte Frame Counter */
518 u32 tr1k; /* TX & RX 512-1023 byte Frame Counter */
519 u32 trmax; /* TX & RX 1024-1518 byte Frame Counter */
520 u32 trmgv; /* TX & RX 1519-1522 byte Good VLAN Frame */
521 u32 rbyt; /* RX Byte Counter */
522 u32 rpkt; /* RX Packet Counter */
523 u32 rfcs; /* RX FCS Error Counter */
524 u32 rmca; /* RX Multicast Packet Counter */
525 u32 rbca; /* RX Broadcast Packet Counter */
526 u32 rxcf; /* RX Control Frame Packet Counter */
527 u32 rxpf; /* RX Pause Frame Packet Counter */
528 u32 rxuo; /* RX Unknown OP Code Counter */
529 u32 raln; /* RX Alignment Error Counter */
530 u32 rflr; /* RX Frame Len Error Counter */
531 u32 rcde; /* RX Code Error Counter */
532 u32 rcse; /* RX Carrier Sense Error Counter */
533 u32 rund; /* RX Undersize Packet Counter */
534 u32 rovr; /* RX Oversize Packet Counter */
535 u32 rfrg; /* RX Fragments Counter */
536 u32 rjbr; /* RX Jabber Counter */
537 u32 rdrp; /* RX Drop Counter */
538 u32 tbyt; /* TX Byte Counter Counter */
539 u32 tpkt; /* TX Packet Counter */
540 u32 tmca; /* TX Multicast Packet Counter */
541 u32 tbca; /* TX Broadcast Packet Counter */
542 u32 txpf; /* TX Pause Control Frame Counter */
543 u32 tdfr; /* TX Deferral Packet Counter */
544 u32 tedf; /* TX Excessive Deferral Packet Counter */
545 u32 tscl; /* TX Single Collision Packet Counter */
546 u32 tmcl; /* TX Multiple Collision Packet Counter */
547 u32 tlcl; /* TX Late Collision Packet Counter */
548 u32 txcl; /* TX Excessive Collision Packet Counter */
549 u32 tncl; /* TX Total Collision Counter */
550 u8 res21[4];
551 u32 tdrp; /* TX Drop Frame Counter */
552 u32 tjbr; /* TX Jabber Frame Counter */
553 u32 tfcs; /* TX FCS Error Counter */
554 u32 txcf; /* TX Control Frame Counter */
555 u32 tovr; /* TX Oversize Frame Counter */
556 u32 tund; /* TX Undersize Frame Counter */
557 u32 tfrg; /* TX Fragments Frame Counter */
558 u32 car1; /* Carry One */
559 u32 car2; /* Carry Two */
560 u32 cam1; /* Carry Mask One */
561 u32 cam2; /* Carry Mask Two */
562 u8 res22[192];
563 u32 iaddr0; /* Indivdual addr 0 */
564 u32 iaddr1; /* Indivdual addr 1 */
565 u32 iaddr2; /* Indivdual addr 2 */
566 u32 iaddr3; /* Indivdual addr 3 */
567 u32 iaddr4; /* Indivdual addr 4 */
568 u32 iaddr5; /* Indivdual addr 5 */
569 u32 iaddr6; /* Indivdual addr 6 */
570 u32 iaddr7; /* Indivdual addr 7 */
571 u8 res23[96];
572 u32 gaddr0; /* Global addr 0 */
573 u32 gaddr1; /* Global addr 1 */
574 u32 gaddr2; /* Global addr 2 */
575 u32 gaddr3; /* Global addr 3 */
576 u32 gaddr4; /* Global addr 4 */
577 u32 gaddr5; /* Global addr 5 */
578 u32 gaddr6; /* Global addr 6 */
579 u32 gaddr7; /* Global addr 7 */
580 u8 res24[96];
581 u32 pmd0; /* Pattern Match Data */
582 u8 res25[4];
583 u32 pmask0; /* Pattern Mask */
584 u8 res26[4];
585 u32 pcntrl0; /* Pattern Match Control */
586 u8 res27[4];
587 u32 pattrb0; /* Pattern Match Attrs */
588 u32 pattrbeli0; /* Pattern Match Attrs Extract Len & Idx */
589 u32 pmd1; /* Pattern Match Data */
590 u8 res28[4];
591 u32 pmask1; /* Pattern Mask */
592 u8 res29[4];
593 u32 pcntrl1; /* Pattern Match Control */
594 u8 res30[4];
595 u32 pattrb1; /* Pattern Match Attrs */
596 u32 pattrbeli1; /* Pattern Match Attrs Extract Len & Idx */
597 u32 pmd2; /* Pattern Match Data */
598 u8 res31[4];
599 u32 pmask2; /* Pattern Mask */
600 u8 res32[4];
601 u32 pcntrl2; /* Pattern Match Control */
602 u8 res33[4];
603 u32 pattrb2; /* Pattern Match Attrs */
604 u32 pattrbeli2; /* Pattern Match Attrs Extract Len & Idx */
605 u32 pmd3; /* Pattern Match Data */
606 u8 res34[4];
607 u32 pmask3; /* Pattern Mask */
608 u8 res35[4];
609 u32 pcntrl3; /* Pattern Match Control */
610 u8 res36[4];
611 u32 pattrb3; /* Pattern Match Attrs */
612 u32 pattrbeli3; /* Pattern Match Attrs Extract Len & Idx */
613 u32 pmd4; /* Pattern Match Data */
614 u8 res37[4];
615 u32 pmask4; /* Pattern Mask */
616 u8 res38[4];
617 u32 pcntrl4; /* Pattern Match Control */
618 u8 res39[4];
619 u32 pattrb4; /* Pattern Match Attrs */
620 u32 pattrbeli4; /* Pattern Match Attrs Extract Len & Idx */
621 u32 pmd5; /* Pattern Match Data */
622 u8 res40[4];
623 u32 pmask5; /* Pattern Mask */
624 u8 res41[4];
625 u32 pcntrl5; /* Pattern Match Control */
626 u8 res42[4];
627 u32 pattrb5; /* Pattern Match Attrs */
628 u32 pattrbeli5; /* Pattern Match Attrs Extract Len & Idx */
629 u32 pmd6; /* Pattern Match Data */
630 u8 res43[4];
631 u32 pmask6; /* Pattern Mask */
632 u8 res44[4];
633 u32 pcntrl6; /* Pattern Match Control */
634 u8 res45[4];
635 u32 pattrb6; /* Pattern Match Attrs */
636 u32 pattrbeli6; /* Pattern Match Attrs Extract Len & Idx */
637 u32 pmd7; /* Pattern Match Data */
638 u8 res46[4];
639 u32 pmask7; /* Pattern Mask */
640 u8 res47[4];
641 u32 pcntrl7; /* Pattern Match Control */
642 u8 res48[4];
643 u32 pattrb7; /* Pattern Match Attrs */
644 u32 pattrbeli7; /* Pattern Match Attrs Extract Len & Idx */
645 u32 pmd8; /* Pattern Match Data */
646 u8 res49[4];
647 u32 pmask8; /* Pattern Mask */
648 u8 res50[4];
649 u32 pcntrl8; /* Pattern Match Control */
650 u8 res51[4];
651 u32 pattrb8; /* Pattern Match Attrs */
652 u32 pattrbeli8; /* Pattern Match Attrs Extract Len & Idx */
653 u32 pmd9; /* Pattern Match Data */
654 u8 res52[4];
655 u32 pmask9; /* Pattern Mask */
656 u8 res53[4];
657 u32 pcntrl9; /* Pattern Match Control */
658 u8 res54[4];
659 u32 pattrb9; /* Pattern Match Attrs */
660 u32 pattrbeli9; /* Pattern Match Attrs Extract Len & Idx */
661 u32 pmd10; /* Pattern Match Data */
662 u8 res55[4];
663 u32 pmask10; /* Pattern Mask */
664 u8 res56[4];
665 u32 pcntrl10; /* Pattern Match Control */
666 u8 res57[4];
667 u32 pattrb10; /* Pattern Match Attrs */
668 u32 pattrbeli10; /* Pattern Match Attrs Extract Len & Idx */
669 u32 pmd11; /* Pattern Match Data */
670 u8 res58[4];
671 u32 pmask11; /* Pattern Mask */
672 u8 res59[4];
673 u32 pcntrl11; /* Pattern Match Control */
674 u8 res60[4];
675 u32 pattrb11; /* Pattern Match Attrs */
676 u32 pattrbeli11; /* Pattern Match Attrs Extract Len & Idx */
677 u32 pmd12; /* Pattern Match Data */
678 u8 res61[4];
679 u32 pmask12; /* Pattern Mask */
680 u8 res62[4];
681 u32 pcntrl12; /* Pattern Match Control */
682 u8 res63[4];
683 u32 pattrb12; /* Pattern Match Attrs */
684 u32 pattrbeli12; /* Pattern Match Attrs Extract Len & Idx */
685 u32 pmd13; /* Pattern Match Data */
686 u8 res64[4];
687 u32 pmask13; /* Pattern Mask */
688 u8 res65[4];
689 u32 pcntrl13; /* Pattern Match Control */
690 u8 res66[4];
691 u32 pattrb13; /* Pattern Match Attrs */
692 u32 pattrbeli13; /* Pattern Match Attrs Extract Len & Idx */
693 u32 pmd14; /* Pattern Match Data */
694 u8 res67[4];
695 u32 pmask14; /* Pattern Mask */
696 u8 res68[4];
697 u32 pcntrl14; /* Pattern Match Control */
698 u8 res69[4];
699 u32 pattrb14; /* Pattern Match Attrs */
700 u32 pattrbeli14; /* Pattern Match Attrs Extract Len & Idx */
701 u32 pmd15; /* Pattern Match Data */
702 u8 res70[4];
703 u32 pmask15; /* Pattern Mask */
704 u8 res71[4];
705 u32 pcntrl15; /* Pattern Match Control */
706 u8 res72[4];
707 u32 pattrb15; /* Pattern Match Attrs */
708 u32 pattrbeli15; /* Pattern Match Attrs Extract Len & Idx */
709 u8 res73[248];
710 u32 attr; /* Attrs */
711 u32 attreli; /* Attrs Extract Len & Idx */
712 u8 res74[1024];
713 } ccsr_tsec_t;
714
715 /* PIC Registers */
716 typedef struct ccsr_pic {
717 u8 res1[64];
718 u32 ipidr0; /* Interprocessor IRQ Dispatch 0 */
719 u8 res2[12];
720 u32 ipidr1; /* Interprocessor IRQ Dispatch 1 */
721 u8 res3[12];
722 u32 ipidr2; /* Interprocessor IRQ Dispatch 2 */
723 u8 res4[12];
724 u32 ipidr3; /* Interprocessor IRQ Dispatch 3 */
725 u8 res5[12];
726 u32 ctpr; /* Current Task Priority */
727 u8 res6[12];
728 u32 whoami; /* Who Am I */
729 u8 res7[12];
730 u32 iack; /* IRQ Acknowledge */
731 u8 res8[12];
732 u32 eoi; /* End Of IRQ */
733 u8 res9[3916];
734 u32 frr; /* Feature Reporting */
735 u8 res10[28];
736 u32 gcr; /* Global Configuration */
737 #define MPC85xx_PICGCR_RST 0x80000000
738 #define MPC85xx_PICGCR_M 0x20000000
739 u8 res11[92];
740 u32 vir; /* Vendor Identification */
741 u8 res12[12];
742 u32 pir; /* Processor Initialization */
743 u8 res13[12];
744 u32 ipivpr0; /* IPI Vector/Priority 0 */
745 u8 res14[12];
746 u32 ipivpr1; /* IPI Vector/Priority 1 */
747 u8 res15[12];
748 u32 ipivpr2; /* IPI Vector/Priority 2 */
749 u8 res16[12];
750 u32 ipivpr3; /* IPI Vector/Priority 3 */
751 u8 res17[12];
752 u32 svr; /* Spurious Vector */
753 u8 res18[12];
754 u32 tfrr; /* Timer Frequency Reporting */
755 u8 res19[12];
756 u32 gtccr0; /* Global Timer Current Count 0 */
757 u8 res20[12];
758 u32 gtbcr0; /* Global Timer Base Count 0 */
759 u8 res21[12];
760 u32 gtvpr0; /* Global Timer Vector/Priority 0 */
761 u8 res22[12];
762 u32 gtdr0; /* Global Timer Destination 0 */
763 u8 res23[12];
764 u32 gtccr1; /* Global Timer Current Count 1 */
765 u8 res24[12];
766 u32 gtbcr1; /* Global Timer Base Count 1 */
767 u8 res25[12];
768 u32 gtvpr1; /* Global Timer Vector/Priority 1 */
769 u8 res26[12];
770 u32 gtdr1; /* Global Timer Destination 1 */
771 u8 res27[12];
772 u32 gtccr2; /* Global Timer Current Count 2 */
773 u8 res28[12];
774 u32 gtbcr2; /* Global Timer Base Count 2 */
775 u8 res29[12];
776 u32 gtvpr2; /* Global Timer Vector/Priority 2 */
777 u8 res30[12];
778 u32 gtdr2; /* Global Timer Destination 2 */
779 u8 res31[12];
780 u32 gtccr3; /* Global Timer Current Count 3 */
781 u8 res32[12];
782 u32 gtbcr3; /* Global Timer Base Count 3 */
783 u8 res33[12];
784 u32 gtvpr3; /* Global Timer Vector/Priority 3 */
785 u8 res34[12];
786 u32 gtdr3; /* Global Timer Destination 3 */
787 u8 res35[268];
788 u32 tcr; /* Timer Control */
789 u8 res36[12];
790 u32 irqsr0; /* IRQ_OUT Summary 0 */
791 u8 res37[12];
792 u32 irqsr1; /* IRQ_OUT Summary 1 */
793 u8 res38[12];
794 u32 cisr0; /* Critical IRQ Summary 0 */
795 u8 res39[12];
796 u32 cisr1; /* Critical IRQ Summary 1 */
797 u8 res40[188];
798 u32 msgr0; /* Message 0 */
799 u8 res41[12];
800 u32 msgr1; /* Message 1 */
801 u8 res42[12];
802 u32 msgr2; /* Message 2 */
803 u8 res43[12];
804 u32 msgr3; /* Message 3 */
805 u8 res44[204];
806 u32 mer; /* Message Enable */
807 u8 res45[12];
808 u32 msr; /* Message Status */
809 u8 res46[60140];
810 u32 eivpr0; /* External IRQ Vector/Priority 0 */
811 u8 res47[12];
812 u32 eidr0; /* External IRQ Destination 0 */
813 u8 res48[12];
814 u32 eivpr1; /* External IRQ Vector/Priority 1 */
815 u8 res49[12];
816 u32 eidr1; /* External IRQ Destination 1 */
817 u8 res50[12];
818 u32 eivpr2; /* External IRQ Vector/Priority 2 */
819 u8 res51[12];
820 u32 eidr2; /* External IRQ Destination 2 */
821 u8 res52[12];
822 u32 eivpr3; /* External IRQ Vector/Priority 3 */
823 u8 res53[12];
824 u32 eidr3; /* External IRQ Destination 3 */
825 u8 res54[12];
826 u32 eivpr4; /* External IRQ Vector/Priority 4 */
827 u8 res55[12];
828 u32 eidr4; /* External IRQ Destination 4 */
829 u8 res56[12];
830 u32 eivpr5; /* External IRQ Vector/Priority 5 */
831 u8 res57[12];
832 u32 eidr5; /* External IRQ Destination 5 */
833 u8 res58[12];
834 u32 eivpr6; /* External IRQ Vector/Priority 6 */
835 u8 res59[12];
836 u32 eidr6; /* External IRQ Destination 6 */
837 u8 res60[12];
838 u32 eivpr7; /* External IRQ Vector/Priority 7 */
839 u8 res61[12];
840 u32 eidr7; /* External IRQ Destination 7 */
841 u8 res62[12];
842 u32 eivpr8; /* External IRQ Vector/Priority 8 */
843 u8 res63[12];
844 u32 eidr8; /* External IRQ Destination 8 */
845 u8 res64[12];
846 u32 eivpr9; /* External IRQ Vector/Priority 9 */
847 u8 res65[12];
848 u32 eidr9; /* External IRQ Destination 9 */
849 u8 res66[12];
850 u32 eivpr10; /* External IRQ Vector/Priority 10 */
851 u8 res67[12];
852 u32 eidr10; /* External IRQ Destination 10 */
853 u8 res68[12];
854 u32 eivpr11; /* External IRQ Vector/Priority 11 */
855 u8 res69[12];
856 u32 eidr11; /* External IRQ Destination 11 */
857 u8 res70[140];
858 u32 iivpr0; /* Internal IRQ Vector/Priority 0 */
859 u8 res71[12];
860 u32 iidr0; /* Internal IRQ Destination 0 */
861 u8 res72[12];
862 u32 iivpr1; /* Internal IRQ Vector/Priority 1 */
863 u8 res73[12];
864 u32 iidr1; /* Internal IRQ Destination 1 */
865 u8 res74[12];
866 u32 iivpr2; /* Internal IRQ Vector/Priority 2 */
867 u8 res75[12];
868 u32 iidr2; /* Internal IRQ Destination 2 */
869 u8 res76[12];
870 u32 iivpr3; /* Internal IRQ Vector/Priority 3 */
871 u8 res77[12];
872 u32 iidr3; /* Internal IRQ Destination 3 */
873 u8 res78[12];
874 u32 iivpr4; /* Internal IRQ Vector/Priority 4 */
875 u8 res79[12];
876 u32 iidr4; /* Internal IRQ Destination 4 */
877 u8 res80[12];
878 u32 iivpr5; /* Internal IRQ Vector/Priority 5 */
879 u8 res81[12];
880 u32 iidr5; /* Internal IRQ Destination 5 */
881 u8 res82[12];
882 u32 iivpr6; /* Internal IRQ Vector/Priority 6 */
883 u8 res83[12];
884 u32 iidr6; /* Internal IRQ Destination 6 */
885 u8 res84[12];
886 u32 iivpr7; /* Internal IRQ Vector/Priority 7 */
887 u8 res85[12];
888 u32 iidr7; /* Internal IRQ Destination 7 */
889 u8 res86[12];
890 u32 iivpr8; /* Internal IRQ Vector/Priority 8 */
891 u8 res87[12];
892 u32 iidr8; /* Internal IRQ Destination 8 */
893 u8 res88[12];
894 u32 iivpr9; /* Internal IRQ Vector/Priority 9 */
895 u8 res89[12];
896 u32 iidr9; /* Internal IRQ Destination 9 */
897 u8 res90[12];
898 u32 iivpr10; /* Internal IRQ Vector/Priority 10 */
899 u8 res91[12];
900 u32 iidr10; /* Internal IRQ Destination 10 */
901 u8 res92[12];
902 u32 iivpr11; /* Internal IRQ Vector/Priority 11 */
903 u8 res93[12];
904 u32 iidr11; /* Internal IRQ Destination 11 */
905 u8 res94[12];
906 u32 iivpr12; /* Internal IRQ Vector/Priority 12 */
907 u8 res95[12];
908 u32 iidr12; /* Internal IRQ Destination 12 */
909 u8 res96[12];
910 u32 iivpr13; /* Internal IRQ Vector/Priority 13 */
911 u8 res97[12];
912 u32 iidr13; /* Internal IRQ Destination 13 */
913 u8 res98[12];
914 u32 iivpr14; /* Internal IRQ Vector/Priority 14 */
915 u8 res99[12];
916 u32 iidr14; /* Internal IRQ Destination 14 */
917 u8 res100[12];
918 u32 iivpr15; /* Internal IRQ Vector/Priority 15 */
919 u8 res101[12];
920 u32 iidr15; /* Internal IRQ Destination 15 */
921 u8 res102[12];
922 u32 iivpr16; /* Internal IRQ Vector/Priority 16 */
923 u8 res103[12];
924 u32 iidr16; /* Internal IRQ Destination 16 */
925 u8 res104[12];
926 u32 iivpr17; /* Internal IRQ Vector/Priority 17 */
927 u8 res105[12];
928 u32 iidr17; /* Internal IRQ Destination 17 */
929 u8 res106[12];
930 u32 iivpr18; /* Internal IRQ Vector/Priority 18 */
931 u8 res107[12];
932 u32 iidr18; /* Internal IRQ Destination 18 */
933 u8 res108[12];
934 u32 iivpr19; /* Internal IRQ Vector/Priority 19 */
935 u8 res109[12];
936 u32 iidr19; /* Internal IRQ Destination 19 */
937 u8 res110[12];
938 u32 iivpr20; /* Internal IRQ Vector/Priority 20 */
939 u8 res111[12];
940 u32 iidr20; /* Internal IRQ Destination 20 */
941 u8 res112[12];
942 u32 iivpr21; /* Internal IRQ Vector/Priority 21 */
943 u8 res113[12];
944 u32 iidr21; /* Internal IRQ Destination 21 */
945 u8 res114[12];
946 u32 iivpr22; /* Internal IRQ Vector/Priority 22 */
947 u8 res115[12];
948 u32 iidr22; /* Internal IRQ Destination 22 */
949 u8 res116[12];
950 u32 iivpr23; /* Internal IRQ Vector/Priority 23 */
951 u8 res117[12];
952 u32 iidr23; /* Internal IRQ Destination 23 */
953 u8 res118[12];
954 u32 iivpr24; /* Internal IRQ Vector/Priority 24 */
955 u8 res119[12];
956 u32 iidr24; /* Internal IRQ Destination 24 */
957 u8 res120[12];
958 u32 iivpr25; /* Internal IRQ Vector/Priority 25 */
959 u8 res121[12];
960 u32 iidr25; /* Internal IRQ Destination 25 */
961 u8 res122[12];
962 u32 iivpr26; /* Internal IRQ Vector/Priority 26 */
963 u8 res123[12];
964 u32 iidr26; /* Internal IRQ Destination 26 */
965 u8 res124[12];
966 u32 iivpr27; /* Internal IRQ Vector/Priority 27 */
967 u8 res125[12];
968 u32 iidr27; /* Internal IRQ Destination 27 */
969 u8 res126[12];
970 u32 iivpr28; /* Internal IRQ Vector/Priority 28 */
971 u8 res127[12];
972 u32 iidr28; /* Internal IRQ Destination 28 */
973 u8 res128[12];
974 u32 iivpr29; /* Internal IRQ Vector/Priority 29 */
975 u8 res129[12];
976 u32 iidr29; /* Internal IRQ Destination 29 */
977 u8 res130[12];
978 u32 iivpr30; /* Internal IRQ Vector/Priority 30 */
979 u8 res131[12];
980 u32 iidr30; /* Internal IRQ Destination 30 */
981 u8 res132[12];
982 u32 iivpr31; /* Internal IRQ Vector/Priority 31 */
983 u8 res133[12];
984 u32 iidr31; /* Internal IRQ Destination 31 */
985 u8 res134[4108];
986 u32 mivpr0; /* Messaging IRQ Vector/Priority 0 */
987 u8 res135[12];
988 u32 midr0; /* Messaging IRQ Destination 0 */
989 u8 res136[12];
990 u32 mivpr1; /* Messaging IRQ Vector/Priority 1 */
991 u8 res137[12];
992 u32 midr1; /* Messaging IRQ Destination 1 */
993 u8 res138[12];
994 u32 mivpr2; /* Messaging IRQ Vector/Priority 2 */
995 u8 res139[12];
996 u32 midr2; /* Messaging IRQ Destination 2 */
997 u8 res140[12];
998 u32 mivpr3; /* Messaging IRQ Vector/Priority 3 */
999 u8 res141[12];
1000 u32 midr3; /* Messaging IRQ Destination 3 */
1001 u8 res142[59852];
1002 u32 ipi0dr0; /* Processor 0 Interprocessor IRQ Dispatch 0 */
1003 u8 res143[12];
1004 u32 ipi0dr1; /* Processor 0 Interprocessor IRQ Dispatch 1 */
1005 u8 res144[12];
1006 u32 ipi0dr2; /* Processor 0 Interprocessor IRQ Dispatch 2 */
1007 u8 res145[12];
1008 u32 ipi0dr3; /* Processor 0 Interprocessor IRQ Dispatch 3 */
1009 u8 res146[12];
1010 u32 ctpr0; /* Current Task Priority for Processor 0 */
1011 u8 res147[12];
1012 u32 whoami0; /* Who Am I for Processor 0 */
1013 u8 res148[12];
1014 u32 iack0; /* IRQ Acknowledge for Processor 0 */
1015 u8 res149[12];
1016 u32 eoi0; /* End Of IRQ for Processor 0 */
1017 u8 res150[130892];
1018 } ccsr_pic_t;
1019
1020 /* CPM Block */
1021 #ifndef CONFIG_CPM2
1022 typedef struct ccsr_cpm {
1023 u8 res[262144];
1024 } ccsr_cpm_t;
1025 #else
1026 /*
1027 * DPARM
1028 * General SIU
1029 */
1030 typedef struct ccsr_cpm_siu {
1031 u8 res1[80];
1032 u32 smaer;
1033 u32 smser;
1034 u32 smevr;
1035 u8 res2[4];
1036 u32 lmaer;
1037 u32 lmser;
1038 u32 lmevr;
1039 u8 res3[2964];
1040 } ccsr_cpm_siu_t;
1041
1042 /* IRQ Controller */
1043 typedef struct ccsr_cpm_intctl {
1044 u16 sicr;
1045 u8 res1[2];
1046 u32 sivec;
1047 u32 sipnrh;
1048 u32 sipnrl;
1049 u32 siprr;
1050 u32 scprrh;
1051 u32 scprrl;
1052 u32 simrh;
1053 u32 simrl;
1054 u32 siexr;
1055 u8 res2[88];
1056 u32 sccr;
1057 u8 res3[124];
1058 } ccsr_cpm_intctl_t;
1059
1060 /* input/output port */
1061 typedef struct ccsr_cpm_iop {
1062 u32 pdira;
1063 u32 ppara;
1064 u32 psora;
1065 u32 podra;
1066 u32 pdata;
1067 u8 res1[12];
1068 u32 pdirb;
1069 u32 pparb;
1070 u32 psorb;
1071 u32 podrb;
1072 u32 pdatb;
1073 u8 res2[12];
1074 u32 pdirc;
1075 u32 pparc;
1076 u32 psorc;
1077 u32 podrc;
1078 u32 pdatc;
1079 u8 res3[12];
1080 u32 pdird;
1081 u32 ppard;
1082 u32 psord;
1083 u32 podrd;
1084 u32 pdatd;
1085 u8 res4[12];
1086 } ccsr_cpm_iop_t;
1087
1088 /* CPM timers */
1089 typedef struct ccsr_cpm_timer {
1090 u8 tgcr1;
1091 u8 res1[3];
1092 u8 tgcr2;
1093 u8 res2[11];
1094 u16 tmr1;
1095 u16 tmr2;
1096 u16 trr1;
1097 u16 trr2;
1098 u16 tcr1;
1099 u16 tcr2;
1100 u16 tcn1;
1101 u16 tcn2;
1102 u16 tmr3;
1103 u16 tmr4;
1104 u16 trr3;
1105 u16 trr4;
1106 u16 tcr3;
1107 u16 tcr4;
1108 u16 tcn3;
1109 u16 tcn4;
1110 u16 ter1;
1111 u16 ter2;
1112 u16 ter3;
1113 u16 ter4;
1114 u8 res3[608];
1115 } ccsr_cpm_timer_t;
1116
1117 /* SDMA */
1118 typedef struct ccsr_cpm_sdma {
1119 u8 sdsr;
1120 u8 res1[3];
1121 u8 sdmr;
1122 u8 res2[739];
1123 } ccsr_cpm_sdma_t;
1124
1125 /* FCC1 */
1126 typedef struct ccsr_cpm_fcc1 {
1127 u32 gfmr;
1128 u32 fpsmr;
1129 u16 ftodr;
1130 u8 res1[2];
1131 u16 fdsr;
1132 u8 res2[2];
1133 u16 fcce;
1134 u8 res3[2];
1135 u16 fccm;
1136 u8 res4[2];
1137 u8 fccs;
1138 u8 res5[3];
1139 u8 ftirr_phy[4];
1140 } ccsr_cpm_fcc1_t;
1141
1142 /* FCC2 */
1143 typedef struct ccsr_cpm_fcc2 {
1144 u32 gfmr;
1145 u32 fpsmr;
1146 u16 ftodr;
1147 u8 res1[2];
1148 u16 fdsr;
1149 u8 res2[2];
1150 u16 fcce;
1151 u8 res3[2];
1152 u16 fccm;
1153 u8 res4[2];
1154 u8 fccs;
1155 u8 res5[3];
1156 u8 ftirr_phy[4];
1157 } ccsr_cpm_fcc2_t;
1158
1159 /* FCC3 */
1160 typedef struct ccsr_cpm_fcc3 {
1161 u32 gfmr;
1162 u32 fpsmr;
1163 u16 ftodr;
1164 u8 res1[2];
1165 u16 fdsr;
1166 u8 res2[2];
1167 u16 fcce;
1168 u8 res3[2];
1169 u16 fccm;
1170 u8 res4[2];
1171 u8 fccs;
1172 u8 res5[3];
1173 u8 res[36];
1174 } ccsr_cpm_fcc3_t;
1175
1176 /* FCC1 extended */
1177 typedef struct ccsr_cpm_fcc1_ext {
1178 u32 firper;
1179 u32 firer;
1180 u32 firsr_h;
1181 u32 firsr_l;
1182 u8 gfemr;
1183 u8 res[15];
1184
1185 } ccsr_cpm_fcc1_ext_t;
1186
1187 /* FCC2 extended */
1188 typedef struct ccsr_cpm_fcc2_ext {
1189 u32 firper;
1190 u32 firer;
1191 u32 firsr_h;
1192 u32 firsr_l;
1193 u8 gfemr;
1194 u8 res[31];
1195 } ccsr_cpm_fcc2_ext_t;
1196
1197 /* FCC3 extended */
1198 typedef struct ccsr_cpm_fcc3_ext {
1199 u8 gfemr;
1200 u8 res[47];
1201 } ccsr_cpm_fcc3_ext_t;
1202
1203 /* TC layers */
1204 typedef struct ccsr_cpm_tmp1 {
1205 u8 res[496];
1206 } ccsr_cpm_tmp1_t;
1207
1208 /* BRGs:5,6,7,8 */
1209 typedef struct ccsr_cpm_brg2 {
1210 u32 brgc5;
1211 u32 brgc6;
1212 u32 brgc7;
1213 u32 brgc8;
1214 u8 res[608];
1215 } ccsr_cpm_brg2_t;
1216
1217 /* I2C */
1218 typedef struct ccsr_cpm_i2c {
1219 u8 i2mod;
1220 u8 res1[3];
1221 u8 i2add;
1222 u8 res2[3];
1223 u8 i2brg;
1224 u8 res3[3];
1225 u8 i2com;
1226 u8 res4[3];
1227 u8 i2cer;
1228 u8 res5[3];
1229 u8 i2cmr;
1230 u8 res6[331];
1231 } ccsr_cpm_i2c_t;
1232
1233 /* CPM core */
1234 typedef struct ccsr_cpm_cp {
1235 u32 cpcr;
1236 u32 rccr;
1237 u8 res1[14];
1238 u16 rter;
1239 u8 res2[2];
1240 u16 rtmr;
1241 u16 rtscr;
1242 u8 res3[2];
1243 u32 rtsr;
1244 u8 res4[12];
1245 } ccsr_cpm_cp_t;
1246
1247 /* BRGs:1,2,3,4 */
1248 typedef struct ccsr_cpm_brg1 {
1249 u32 brgc1;
1250 u32 brgc2;
1251 u32 brgc3;
1252 u32 brgc4;
1253 } ccsr_cpm_brg1_t;
1254
1255 /* SCC1-SCC4 */
1256 typedef struct ccsr_cpm_scc {
1257 u32 gsmrl;
1258 u32 gsmrh;
1259 u16 psmr;
1260 u8 res1[2];
1261 u16 todr;
1262 u16 dsr;
1263 u16 scce;
1264 u8 res2[2];
1265 u16 sccm;
1266 u8 res3;
1267 u8 sccs;
1268 u8 res4[8];
1269 } ccsr_cpm_scc_t;
1270
1271 typedef struct ccsr_cpm_tmp2 {
1272 u8 res[32];
1273 } ccsr_cpm_tmp2_t;
1274
1275 /* SPI */
1276 typedef struct ccsr_cpm_spi {
1277 u16 spmode;
1278 u8 res1[4];
1279 u8 spie;
1280 u8 res2[3];
1281 u8 spim;
1282 u8 res3[2];
1283 u8 spcom;
1284 u8 res4[82];
1285 } ccsr_cpm_spi_t;
1286
1287 /* CPM MUX */
1288 typedef struct ccsr_cpm_mux {
1289 u8 cmxsi1cr;
1290 u8 res1;
1291 u8 cmxsi2cr;
1292 u8 res2;
1293 u32 cmxfcr;
1294 u32 cmxscr;
1295 u8 res3[2];
1296 u16 cmxuar;
1297 u8 res4[16];
1298 } ccsr_cpm_mux_t;
1299
1300 /* SI,MCC,etc */
1301 typedef struct ccsr_cpm_tmp3 {
1302 u8 res[58592];
1303 } ccsr_cpm_tmp3_t;
1304
1305 typedef struct ccsr_cpm_iram {
1306 u32 iram[8192];
1307 u8 res[98304];
1308 } ccsr_cpm_iram_t;
1309
1310 typedef struct ccsr_cpm {
1311 /* Some references are into the unique & known dpram spaces,
1312 * others are from the generic base.
1313 */
1314 #define im_dprambase im_dpram1
1315 u8 im_dpram1[16*1024];
1316 u8 res1[16*1024];
1317 u8 im_dpram2[16*1024];
1318 u8 res2[16*1024];
1319 ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */
1320 ccsr_cpm_intctl_t im_cpm_intctl; /* IRQ Controller */
1321 ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */
1322 ccsr_cpm_timer_t im_cpm_timer; /* CPM timers */
1323 ccsr_cpm_sdma_t im_cpm_sdma; /* SDMA control/status */
1324 ccsr_cpm_fcc1_t im_cpm_fcc1;
1325 ccsr_cpm_fcc2_t im_cpm_fcc2;
1326 ccsr_cpm_fcc3_t im_cpm_fcc3;
1327 ccsr_cpm_fcc1_ext_t im_cpm_fcc1_ext;
1328 ccsr_cpm_fcc2_ext_t im_cpm_fcc2_ext;
1329 ccsr_cpm_fcc3_ext_t im_cpm_fcc3_ext;
1330 ccsr_cpm_tmp1_t im_cpm_tmp1;
1331 ccsr_cpm_brg2_t im_cpm_brg2;
1332 ccsr_cpm_i2c_t im_cpm_i2c;
1333 ccsr_cpm_cp_t im_cpm_cp;
1334 ccsr_cpm_brg1_t im_cpm_brg1;
1335 ccsr_cpm_scc_t im_cpm_scc[4];
1336 ccsr_cpm_tmp2_t im_cpm_tmp2;
1337 ccsr_cpm_spi_t im_cpm_spi;
1338 ccsr_cpm_mux_t im_cpm_mux;
1339 ccsr_cpm_tmp3_t im_cpm_tmp3;
1340 ccsr_cpm_iram_t im_cpm_iram;
1341 } ccsr_cpm_t;
1342 #endif
1343
1344 #ifdef CONFIG_SYS_SRIO
1345 /* Architectural regsiters */
1346 struct rio_arch {
1347 u32 didcar; /* Device Identity CAR */
1348 u32 dicar; /* Device Information CAR */
1349 u32 aidcar; /* Assembly Identity CAR */
1350 u32 aicar; /* Assembly Information CAR */
1351 u32 pefcar; /* Processing Element Features CAR */
1352 u8 res0[4];
1353 u32 socar; /* Source Operations CAR */
1354 u32 docar; /* Destination Operations CAR */
1355 u8 res1[32];
1356 u32 mcsr; /* Mailbox CSR */
1357 u32 pwdcsr; /* Port-Write and Doorbell CSR */
1358 u8 res2[4];
1359 u32 pellccsr; /* Processing Element Logic Layer CCSR */
1360 u8 res3[12];
1361 u32 lcsbacsr; /* Local Configuration Space BACSR */
1362 u32 bdidcsr; /* Base Device ID CSR */
1363 u8 res4[4];
1364 u32 hbdidlcsr; /* Host Base Device ID Lock CSR */
1365 u32 ctcsr; /* Component Tag CSR */
1366 };
1367
1368 /* Extended Features Space: 1x/4x LP-Serial Port registers */
1369 struct rio_lp_serial_port {
1370 u32 plmreqcsr; /* Port Link Maintenance Request CSR */
1371 u32 plmrespcsr; /* Port Link Maintenance Response CS */
1372 u32 plascsr; /* Port Local Ackid Status CSR */
1373 u8 res0[12];
1374 u32 pescsr; /* Port Error and Status CSR */
1375 u32 pccsr; /* Port Control CSR */
1376 };
1377
1378 /* Extended Features Space: 1x/4x LP-Serial registers */
1379 struct rio_lp_serial {
1380 u32 pmbh0csr; /* Port Maintenance Block Header 0 CSR */
1381 u8 res0[28];
1382 u32 pltoccsr; /* Port Link Time-out CCSR */
1383 u32 prtoccsr; /* Port Response Time-out CCSR */
1384 u8 res1[20];
1385 u32 pgccsr; /* Port General CSR */
1386 struct rio_lp_serial_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
1387 };
1388
1389 /* Logical error reporting registers */
1390 struct rio_logical_err {
1391 u32 erbh; /* Error Reporting Block Header Register */
1392 u8 res0[4];
1393 u32 ltledcsr; /* Logical/Transport layer error DCSR */
1394 u32 ltleecsr; /* Logical/Transport layer error ECSR */
1395 u8 res1[4];
1396 u32 ltlaccsr; /* Logical/Transport layer ACCSR */
1397 u32 ltldidccsr; /* Logical/Transport layer DID CCSR */
1398 u32 ltlcccsr; /* Logical/Transport layer control CCSR */
1399 };
1400
1401 /* Physical error reporting port registers */
1402 struct rio_phys_err_port {
1403 u32 edcsr; /* Port error detect CSR */
1404 u32 erecsr; /* Port error rate enable CSR */
1405 u32 ecacsr; /* Port error capture attributes CSR */
1406 u32 pcseccsr0; /* Port packet/control symbol ECCSR 0 */
1407 u32 peccsr[3]; /* Port error capture CSR */
1408 u8 res0[12];
1409 u32 ercsr; /* Port error rate CSR */
1410 u32 ertcsr; /* Port error rate threshold CSR */
1411 u8 res1[16];
1412 };
1413
1414 /* Physical error reporting registers */
1415 struct rio_phys_err {
1416 struct rio_phys_err_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
1417 };
1418
1419 /* Implementation Space: General Port-Common */
1420 struct rio_impl_common {
1421 u8 res0[4];
1422 u32 llcr; /* Logical Layer Configuration Register */
1423 u8 res1[8];
1424 u32 epwisr; /* Error / Port-Write Interrupt SR */
1425 u8 res2[12];
1426 u32 lretcr; /* Logical Retry Error Threshold CR */
1427 u8 res3[92];
1428 u32 pretcr; /* Physical Retry Erorr Threshold CR */
1429 u8 res4[124];
1430 };
1431
1432 /* Implementation Space: Port Specific */
1433 struct rio_impl_port_spec {
1434 u32 adidcsr; /* Port Alt. Device ID CSR */
1435 u8 res0[28];
1436 u32 ptaacr; /* Port Pass-Through/Accept-All CR */
1437 u32 lopttlcr;
1438 u8 res1[8];
1439 u32 iecsr; /* Port Implementation Error CSR */
1440 u8 res2[12];
1441 u32 pcr; /* Port Phsyical Configuration Register */
1442 u8 res3[20];
1443 u32 slcsr; /* Port Serial Link CSR */
1444 u8 res4[4];
1445 u32 sleicr; /* Port Serial Link Error Injection */
1446 u32 a0txcr; /* Port Arbitration 0 Tx CR */
1447 u32 a1txcr; /* Port Arbitration 1 Tx CR */
1448 u32 a2txcr; /* Port Arbitration 2 Tx CR */
1449 u32 mreqtxbacr[3]; /* Port Request Tx Buffer ACR */
1450 u32 mrspfctxbacr; /* Port Response/Flow Control Tx Buffer ACR */
1451 };
1452
1453 /* Implementation Space: register */
1454 struct rio_implement {
1455 struct rio_impl_common com;
1456 struct rio_impl_port_spec port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
1457 };
1458
1459 /* Revision Control Register */
1460 struct rio_rev_ctrl {
1461 u32 ipbrr[2]; /* IP Block Revision Register */
1462 };
1463
1464 struct rio_atmu_row {
1465 u32 rowtar; /* RapidIO Outbound Window TAR */
1466 u32 rowtear; /* RapidIO Outbound Window TEAR */
1467 u32 rowbar;
1468 u8 res0[4];
1469 u32 rowar; /* RapidIO Outbound Attributes Register */
1470 u32 rowsr[3]; /* Port RapidIO outbound window segment register */
1471 };
1472
1473 struct rio_atmu_riw {
1474 u32 riwtar; /* RapidIO Inbound Window Translation AR */
1475 u8 res0[4];
1476 u32 riwbar; /* RapidIO Inbound Window Base AR */
1477 u8 res1[4];
1478 u32 riwar; /* RapidIO Inbound Attributes Register */
1479 u8 res2[12];
1480 };
1481
1482 /* ATMU window registers */
1483 struct rio_atmu_win {
1484 struct rio_atmu_row outbw[CONFIG_SYS_FSL_SRIO_OB_WIN_NUM];
1485 u8 res0[64];
1486 struct rio_atmu_riw inbw[CONFIG_SYS_FSL_SRIO_IB_WIN_NUM];
1487 };
1488
1489 struct rio_atmu {
1490 struct rio_atmu_win port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
1491 };
1492
1493 #ifdef CONFIG_SYS_FSL_RMU
1494 struct rio_msg {
1495 u32 omr; /* Outbound Mode Register */
1496 u32 osr; /* Outbound Status Register */
1497 u32 eodqdpar; /* Extended Outbound DQ DPAR */
1498 u32 odqdpar; /* Outbound Descriptor Queue DPAR */
1499 u32 eosar; /* Extended Outbound Unit Source AR */
1500 u32 osar; /* Outbound Unit Source AR */
1501 u32 odpr; /* Outbound Destination Port Register */
1502 u32 odatr; /* Outbound Destination Attributes Register */
1503 u32 odcr; /* Outbound Doubleword Count Register */
1504 u32 eodqepar; /* Extended Outbound DQ EPAR */
1505 u32 odqepar; /* Outbound Descriptor Queue EPAR */
1506 u32 oretr; /* Outbound Retry Error Threshold Register */
1507 u32 omgr; /* Outbound Multicast Group Register */
1508 u32 omlr; /* Outbound Multicast List Register */
1509 u8 res0[40];
1510 u32 imr; /* Outbound Mode Register */
1511 u32 isr; /* Inbound Status Register */
1512 u32 eidqdpar; /* Extended Inbound Descriptor Queue DPAR */
1513 u32 idqdpar; /* Inbound Descriptor Queue DPAR */
1514 u32 eifqepar; /* Extended Inbound Frame Queue EPAR */
1515 u32 ifqepar; /* Inbound Frame Queue EPAR */
1516 u32 imirir; /* Inbound Maximum Interrutp RIR */
1517 u8 res1[4];
1518 u32 eihqepar; /* Extended inbound message header queue EPAR */
1519 u32 ihqepar; /* Inbound message header queue EPAR */
1520 u8 res2[120];
1521 };
1522
1523 struct rio_dbell {
1524 u32 odmr; /* Outbound Doorbell Mode Register */
1525 u32 odsr; /* Outbound Doorbell Status Register */
1526 u8 res0[16];
1527 u32 oddpr; /* Outbound Doorbell Destination Port */
1528 u32 oddatr; /* Outbound Doorbell Destination AR */
1529 u8 res1[12];
1530 u32 oddretr; /* Outbound Doorbell Retry Threshold CR */
1531 u8 res2[48];
1532 u32 idmr; /* Inbound Doorbell Mode Register */
1533 u32 idsr; /* Inbound Doorbell Status Register */
1534 u32 iedqdpar; /* Extended Inbound Doorbell Queue DPAR */
1535 u32 iqdpar; /* Inbound Doorbell Queue DPAR */
1536 u32 iedqepar; /* Extended Inbound Doorbell Queue EPAR */
1537 u32 idqepar; /* Inbound Doorbell Queue EPAR */
1538 u32 idmirir; /* Inbound Doorbell Max Interrupt RIR */
1539 };
1540
1541 struct rio_pw {
1542 u32 pwmr; /* Port-Write Mode Register */
1543 u32 pwsr; /* Port-Write Status Register */
1544 u32 epwqbar; /* Extended Port-Write Queue BAR */
1545 u32 pwqbar; /* Port-Write Queue Base Address Register */
1546 };
1547 #endif
1548
1549 #ifdef CONFIG_SYS_FSL_SRIO_LIODN
1550 struct rio_liodn {
1551 u32 plbr;
1552 u8 res0[28];
1553 u32 plaor;
1554 u8 res1[12];
1555 u32 pludr;
1556 u32 plldr;
1557 u8 res2[456];
1558 };
1559 #endif
1560
1561 /* RapidIO Registers */
1562 struct ccsr_rio {
1563 struct rio_arch arch;
1564 u8 res0[144];
1565 struct rio_lp_serial lp_serial;
1566 u8 res1[1152];
1567 struct rio_logical_err logical_err;
1568 u8 res2[32];
1569 struct rio_phys_err phys_err;
1570 u8 res3[63808];
1571 struct rio_implement impl;
1572 u8 res4[2552];
1573 struct rio_rev_ctrl rev;
1574 struct rio_atmu atmu;
1575 #ifdef CONFIG_SYS_FSL_RMU
1576 u8 res5[8192];
1577 struct rio_msg msg[CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM];
1578 u8 res6[512];
1579 struct rio_dbell dbell;
1580 u8 res7[100];
1581 struct rio_pw pw;
1582 #endif
1583 #ifdef CONFIG_SYS_FSL_SRIO_LIODN
1584 u8 res5[8192];
1585 struct rio_liodn liodn[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
1586 #endif
1587 };
1588 #endif
1589
1590 /* Quick Engine Block Pin Muxing Registers */
1591 typedef struct par_io {
1592 u32 cpodr;
1593 u32 cpdat;
1594 u32 cpdir1;
1595 u32 cpdir2;
1596 u32 cppar1;
1597 u32 cppar2;
1598 u8 res[8];
1599 } par_io_t;
1600
1601 #ifdef CONFIG_SYS_FSL_CPC
1602 /*
1603 * Define a single offset that is the start of all the CPC register
1604 * blocks - if there is more than one CPC, we expect these to be
1605 * contiguous 4k regions
1606 */
1607
1608 typedef struct cpc_corenet {
1609 u32 cpccsr0; /* Config/status reg */
1610 u32 res1;
1611 u32 cpccfg0; /* Configuration register */
1612 u32 res2;
1613 u32 cpcewcr0; /* External Write reg 0 */
1614 u32 cpcewabr0; /* External write base reg 0 */
1615 u32 res3[2];
1616 u32 cpcewcr1; /* External Write reg 1 */
1617 u32 cpcewabr1; /* External write base reg 1 */
1618 u32 res4[54];
1619 u32 cpcsrcr1; /* SRAM control reg 1 */
1620 u32 cpcsrcr0; /* SRAM control reg 0 */
1621 u32 res5[62];
1622 struct {
1623 u32 id; /* partition ID */
1624 u32 res;
1625 u32 alloc; /* partition allocation */
1626 u32 way; /* partition way */
1627 } partition_regs[16];
1628 u32 res6[704];
1629 u32 cpcerrinjhi; /* Error injection high */
1630 u32 cpcerrinjlo; /* Error injection lo */
1631 u32 cpcerrinjctl; /* Error injection control */
1632 u32 res7[5];
1633 u32 cpccaptdatahi; /* capture data high */
1634 u32 cpccaptdatalo; /* capture data low */
1635 u32 cpcaptecc; /* capture ECC */
1636 u32 res8[5];
1637 u32 cpcerrdet; /* error detect */
1638 u32 cpcerrdis; /* error disable */
1639 u32 cpcerrinten; /* errir interrupt enable */
1640 u32 cpcerrattr; /* error attribute */
1641 u32 cpcerreaddr; /* error extended address */
1642 u32 cpcerraddr; /* error address */
1643 u32 cpcerrctl; /* error control */
1644 u32 res9[41]; /* pad out to 4k */
1645 u32 cpchdbcr0; /* hardware debug control register 0 */
1646 u32 res10[63]; /* pad out to 4k */
1647 } cpc_corenet_t;
1648
1649 #define CPC_CSR0_CE 0x80000000 /* Cache Enable */
1650 #define CPC_CSR0_PE 0x40000000 /* Enable ECC */
1651 #define CPC_CSR0_FI 0x00200000 /* Cache Flash Invalidate */
1652 #define CPC_CSR0_WT 0x00080000 /* Write-through mode */
1653 #define CPC_CSR0_FL 0x00000800 /* Hardware cache flush */
1654 #define CPC_CSR0_LFC 0x00000400 /* Cache Lock Flash Clear */
1655 #define CPC_CFG0_SZ_MASK 0x00003fff
1656 #define CPC_CFG0_SZ_K(x) ((x & CPC_CFG0_SZ_MASK) << 6)
1657 #define CPC_CFG0_NUM_WAYS(x) (((x >> 14) & 0x1f) + 1)
1658 #define CPC_CFG0_LINE_SZ(x) ((((x >> 23) & 0x3) + 1) * 32)
1659 #define CPC_SRCR1_SRBARU_MASK 0x0000ffff
1660 #define CPC_SRCR1_SRBARU(x) (((unsigned long long)x >> 32) \
1661 & CPC_SRCR1_SRBARU_MASK)
1662 #define CPC_SRCR0_SRBARL_MASK 0xffff8000
1663 #define CPC_SRCR0_SRBARL(x) (x & CPC_SRCR0_SRBARL_MASK)
1664 #define CPC_SRCR0_INTLVEN 0x00000100
1665 #define CPC_SRCR0_SRAMSZ_1_WAY 0x00000000
1666 #define CPC_SRCR0_SRAMSZ_2_WAY 0x00000002
1667 #define CPC_SRCR0_SRAMSZ_4_WAY 0x00000004
1668 #define CPC_SRCR0_SRAMSZ_8_WAY 0x00000006
1669 #define CPC_SRCR0_SRAMSZ_16_WAY 0x00000008
1670 #define CPC_SRCR0_SRAMSZ_32_WAY 0x0000000a
1671 #define CPC_SRCR0_SRAMEN 0x00000001
1672 #define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */
1673 #define CPC_HDBCR0_CDQ_SPEC_DIS 0x08000000
1674 #define CPC_HDBCR0_TAG_ECC_SCRUB_DIS 0x01000000
1675 #define CPC_HDBCR0_DATA_ECC_SCRUB_DIS 0x00400000
1676 #define CPC_HDBCR0_SPLRU_LEVEL_EN 0x003c0000
1677 #endif /* CONFIG_SYS_FSL_CPC */
1678
1679 /* Global Utilities Block */
1680 #ifdef CONFIG_FSL_CORENET
1681 typedef struct ccsr_gur {
1682 u32 porsr1; /* POR status 1 */
1683 u32 porsr2; /* POR status 2 */
1684 u8 res_008[0x20-0x8];
1685 u32 gpporcr1; /* General-purpose POR configuration */
1686 u32 gpporcr2; /* General-purpose POR configuration 2 */
1687 u32 dcfg_fusesr; /* Fuse status register */
1688 #define FSL_CORENET_DCFG_FUSESR_VID_SHIFT 25
1689 #define FSL_CORENET_DCFG_FUSESR_VID_MASK 0x1F
1690 #define FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT 20
1691 #define FSL_CORENET_DCFG_FUSESR_ALTVID_MASK 0x1F
1692 u8 res_02c[0x70-0x2c];
1693 u32 devdisr; /* Device disable control */
1694 u32 devdisr2; /* Device disable control 2 */
1695 u32 devdisr3; /* Device disable control 3 */
1696 u32 devdisr4; /* Device disable control 4 */
1697 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
1698 u32 devdisr5; /* Device disable control 5 */
1699 #define FSL_CORENET_DEVDISR_PBL 0x80000000
1700 #define FSL_CORENET_DEVDISR_PMAN 0x40000000
1701 #define FSL_CORENET_DEVDISR_ESDHC 0x20000000
1702 #define FSL_CORENET_DEVDISR_DMA1 0x00800000
1703 #define FSL_CORENET_DEVDISR_DMA2 0x00400000
1704 #define FSL_CORENET_DEVDISR_USB1 0x00080000
1705 #define FSL_CORENET_DEVDISR_USB2 0x00040000
1706 #define FSL_CORENET_DEVDISR_SATA1 0x00008000
1707 #define FSL_CORENET_DEVDISR_SATA2 0x00004000
1708 #define FSL_CORENET_DEVDISR_PME 0x00000800
1709 #define FSL_CORENET_DEVDISR_SEC 0x00000200
1710 #define FSL_CORENET_DEVDISR_RMU 0x00000080
1711 #define FSL_CORENET_DEVDISR_DCE 0x00000040
1712 #define FSL_CORENET_DEVDISR2_DTSEC1_1 0x80000000
1713 #define FSL_CORENET_DEVDISR2_DTSEC1_2 0x40000000
1714 #define FSL_CORENET_DEVDISR2_DTSEC1_3 0x20000000
1715 #define FSL_CORENET_DEVDISR2_DTSEC1_4 0x10000000
1716 #define FSL_CORENET_DEVDISR2_DTSEC1_5 0x08000000
1717 #define FSL_CORENET_DEVDISR2_DTSEC1_6 0x04000000
1718 #define FSL_CORENET_DEVDISR2_DTSEC1_9 0x00800000
1719 #define FSL_CORENET_DEVDISR2_DTSEC1_10 0x00400000
1720 #define FSL_CORENET_DEVDISR2_10GEC1_1 0x00800000
1721 #define FSL_CORENET_DEVDISR2_10GEC1_2 0x00400000
1722 #define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00080000
1723 #define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00040000
1724 #define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00020000
1725 #define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00010000
1726 #define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00008000
1727 #define FSL_CORENET_DEVDISR2_DTSEC2_6 0x00004000
1728 #define FSL_CORENET_DEVDISR2_DTSEC2_9 0x00000800
1729 #define FSL_CORENET_DEVDISR2_DTSEC2_10 0x00000400
1730 #define FSL_CORENET_DEVDISR2_10GEC2_1 0x00000800
1731 #define FSL_CORENET_DEVDISR2_10GEC2_2 0x00000400
1732 #define FSL_CORENET_DEVDISR2_FM1 0x00000080
1733 #define FSL_CORENET_DEVDISR2_FM2 0x00000040
1734 #define FSL_CORENET_DEVDISR2_CPRI 0x00000008
1735 #define FSL_CORENET_DEVDISR3_PCIE1 0x80000000
1736 #define FSL_CORENET_DEVDISR3_PCIE2 0x40000000
1737 #define FSL_CORENET_DEVDISR3_PCIE3 0x20000000
1738 #define FSL_CORENET_DEVDISR3_PCIE4 0x10000000
1739 #define FSL_CORENET_DEVDISR3_SRIO1 0x08000000
1740 #define FSL_CORENET_DEVDISR3_SRIO2 0x04000000
1741 #define FSL_CORENET_DEVDISR3_QMAN 0x00080000
1742 #define FSL_CORENET_DEVDISR3_BMAN 0x00040000
1743 #define FSL_CORENET_DEVDISR3_LA1 0x00008000
1744 #define FSL_CORENET_DEVDISR3_MAPLE1 0x00000800
1745 #define FSL_CORENET_DEVDISR3_MAPLE2 0x00000400
1746 #define FSL_CORENET_DEVDISR3_MAPLE3 0x00000200
1747 #define FSL_CORENET_DEVDISR4_I2C1 0x80000000
1748 #define FSL_CORENET_DEVDISR4_I2C2 0x40000000
1749 #define FSL_CORENET_DEVDISR4_DUART1 0x20000000
1750 #define FSL_CORENET_DEVDISR4_DUART2 0x10000000
1751 #define FSL_CORENET_DEVDISR4_ESPI 0x08000000
1752 #define FSL_CORENET_DEVDISR5_DDR1 0x80000000
1753 #define FSL_CORENET_DEVDISR5_DDR2 0x40000000
1754 #define FSL_CORENET_DEVDISR5_DDR3 0x20000000
1755 #define FSL_CORENET_DEVDISR5_CPC1 0x08000000
1756 #define FSL_CORENET_DEVDISR5_CPC2 0x04000000
1757 #define FSL_CORENET_DEVDISR5_CPC3 0x02000000
1758 #define FSL_CORENET_DEVDISR5_IFC 0x00800000
1759 #define FSL_CORENET_DEVDISR5_GPIO 0x00400000
1760 #define FSL_CORENET_DEVDISR5_DBG 0x00200000
1761 #define FSL_CORENET_DEVDISR5_NAL 0x00100000
1762 #define FSL_CORENET_DEVDISR5_TIMERS 0x00020000
1763 #define FSL_CORENET_NUM_DEVDISR 5
1764 #else
1765 #define FSL_CORENET_DEVDISR_PCIE1 0x80000000
1766 #define FSL_CORENET_DEVDISR_PCIE2 0x40000000
1767 #define FSL_CORENET_DEVDISR_PCIE3 0x20000000
1768 #define FSL_CORENET_DEVDISR_PCIE4 0x10000000
1769 #define FSL_CORENET_DEVDISR_RMU 0x08000000
1770 #define FSL_CORENET_DEVDISR_SRIO1 0x04000000
1771 #define FSL_CORENET_DEVDISR_SRIO2 0x02000000
1772 #define FSL_CORENET_DEVDISR_DMA1 0x00400000
1773 #define FSL_CORENET_DEVDISR_DMA2 0x00200000
1774 #define FSL_CORENET_DEVDISR_DDR1 0x00100000
1775 #define FSL_CORENET_DEVDISR_DDR2 0x00080000
1776 #define FSL_CORENET_DEVDISR_DBG 0x00010000
1777 #define FSL_CORENET_DEVDISR_NAL 0x00008000
1778 #define FSL_CORENET_DEVDISR_SATA1 0x00004000
1779 #define FSL_CORENET_DEVDISR_SATA2 0x00002000
1780 #define FSL_CORENET_DEVDISR_ELBC 0x00001000
1781 #define FSL_CORENET_DEVDISR_USB1 0x00000800
1782 #define FSL_CORENET_DEVDISR_USB2 0x00000400
1783 #define FSL_CORENET_DEVDISR_ESDHC 0x00000100
1784 #define FSL_CORENET_DEVDISR_GPIO 0x00000080
1785 #define FSL_CORENET_DEVDISR_ESPI 0x00000040
1786 #define FSL_CORENET_DEVDISR_I2C1 0x00000020
1787 #define FSL_CORENET_DEVDISR_I2C2 0x00000010
1788 #define FSL_CORENET_DEVDISR_DUART1 0x00000002
1789 #define FSL_CORENET_DEVDISR_DUART2 0x00000001
1790 #define FSL_CORENET_DEVDISR2_PME 0x80000000
1791 #define FSL_CORENET_DEVDISR2_SEC 0x40000000
1792 #define FSL_CORENET_DEVDISR2_QMBM 0x08000000
1793 #define FSL_CORENET_DEVDISR2_FM1 0x02000000
1794 #define FSL_CORENET_DEVDISR2_10GEC1 0x01000000
1795 #define FSL_CORENET_DEVDISR2_DTSEC1_1 0x00800000
1796 #define FSL_CORENET_DEVDISR2_DTSEC1_2 0x00400000
1797 #define FSL_CORENET_DEVDISR2_DTSEC1_3 0x00200000
1798 #define FSL_CORENET_DEVDISR2_DTSEC1_4 0x00100000
1799 #define FSL_CORENET_DEVDISR2_DTSEC1_5 0x00080000
1800 #define FSL_CORENET_DEVDISR2_FM2 0x00020000
1801 #define FSL_CORENET_DEVDISR2_10GEC2 0x00010000
1802 #define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00008000
1803 #define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00004000
1804 #define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00002000
1805 #define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00001000
1806 #define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00000800
1807 #define FSL_CORENET_NUM_DEVDISR 2
1808 u32 powmgtcsr; /* Power management status & control */
1809 #endif
1810 u8 res8[12];
1811 u32 coredisru; /* uppper portion for support of 64 cores */
1812 u32 coredisrl; /* lower portion for support of 64 cores */
1813 u8 res9[8];
1814 u32 pvr; /* Processor version */
1815 u32 svr; /* System version */
1816 u8 res10[8];
1817 u32 rstcr; /* Reset control */
1818 u32 rstrqpblsr; /* Reset request preboot loader status */
1819 u8 res11[8];
1820 u32 rstrqmr1; /* Reset request mask */
1821 u8 res12[4];
1822 u32 rstrqsr1; /* Reset request status */
1823 u8 res13[4];
1824 u8 res14[4];
1825 u32 rstrqwdtmrl; /* Reset request WDT mask */
1826 u8 res15[4];
1827 u32 rstrqwdtsrl; /* Reset request WDT status */
1828 u8 res16[4];
1829 u32 brrl; /* Boot release */
1830 u8 res17[24];
1831 u32 rcwsr[16]; /* Reset control word status */
1832
1833 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
1834 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 16
1835 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f
1836 #if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
1837 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000
1838 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26
1839 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
1840 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17
1841 #define FSL_CORENET2_RCWSR4_SRDS3_PRTCL 0x0000f800
1842 #define FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT 11
1843 #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL 0x000000f8
1844 #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT 3
1845 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
1846 #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420)
1847 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfe000000
1848 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 25
1849 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000
1850 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16
1851 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
1852 #elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\
1853 defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
1854 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
1855 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
1856 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
1857 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17
1858 #endif
1859 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL1 0x00800000
1860 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL2 0x00400000
1861 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL1 0x00200000
1862 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL2 0x00100000
1863 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL1 0x00080000
1864 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL2 0x00040000
1865 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL1 0x00020000
1866 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL2 0x00010000
1867
1868 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
1869 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 17
1870 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x1f
1871 #define FSL_CORENET_RCWSR4_SRDS_PRTCL 0xfc000000
1872 #define FSL_CORENET_RCWSR5_DDR_SYNC 0x00000080
1873 #define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 7
1874 #define FSL_CORENET_RCWSR5_SRDS_EN 0x00002000
1875 #define FSL_CORENET_RCWSR5_SRDS2_EN 0x00001000
1876 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
1877 #define FSL_CORENET_RCWSRn_SRDS_LPD_B2 0x3c000000 /* bits 162..165 */
1878 #define FSL_CORENET_RCWSRn_SRDS_LPD_B3 0x003c0000 /* bits 170..173 */
1879 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
1880
1881 #define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000
1882 #define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000
1883 #define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000
1884 #define FSL_CORENET_RCWSR11_EC1 0x00c00000 /* bits 360..361 */
1885 #ifdef CONFIG_PPC_P4080
1886 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1 0x00000000
1887 #define FSL_CORENET_RCWSR11_EC1_FM1_USB1 0x00800000
1888 #define FSL_CORENET_RCWSR11_EC2 0x001c0000 /* bits 363..365 */
1889 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1 0x00000000
1890 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2 0x00080000
1891 #define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000
1892 #endif
1893 #if defined(CONFIG_PPC_P2041) \
1894 || defined(CONFIG_PPC_P3041) || defined(CONFIG_PPC_P5020)
1895 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII 0x00000000
1896 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII 0x00800000
1897 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_NONE 0x00c00000
1898 #define FSL_CORENET_RCWSR11_EC2 0x00180000 /* bits 363..364 */
1899 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_RGMII 0x00000000
1900 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII 0x00100000
1901 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_NONE 0x00180000
1902 #endif
1903 #if defined(CONFIG_PPC_P5040)
1904 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII 0x00000000
1905 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII 0x00800000
1906 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_NONE 0x00c00000
1907 #define FSL_CORENET_RCWSR11_EC2 0x00180000 /* bits 363..364 */
1908 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_RGMII 0x00000000
1909 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000
1910 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000
1911 #endif
1912 #if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
1913 #define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
1914 #define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000
1915 #define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000
1916 #define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */
1917 #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000
1918 #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII 0x08000000
1919 #define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000
1920 #endif
1921 u8 res18[192];
1922 u32 scratchrw[4]; /* Scratch Read/Write */
1923 u8 res19[240];
1924 u32 scratchw1r[4]; /* Scratch Read (Write once) */
1925 u8 res20[240];
1926 u32 scrtsr[8]; /* Core reset status */
1927 u8 res21[224];
1928 u32 pex1liodnr; /* PCI Express 1 LIODN */
1929 u32 pex2liodnr; /* PCI Express 2 LIODN */
1930 u32 pex3liodnr; /* PCI Express 3 LIODN */
1931 u32 pex4liodnr; /* PCI Express 4 LIODN */
1932 u32 rio1liodnr; /* RIO 1 LIODN */
1933 u32 rio2liodnr; /* RIO 2 LIODN */
1934 u32 rio3liodnr; /* RIO 3 LIODN */
1935 u32 rio4liodnr; /* RIO 4 LIODN */
1936 u32 usb1liodnr; /* USB 1 LIODN */
1937 u32 usb2liodnr; /* USB 2 LIODN */
1938 u32 usb3liodnr; /* USB 3 LIODN */
1939 u32 usb4liodnr; /* USB 4 LIODN */
1940 u32 sdmmc1liodnr; /* SD/MMC 1 LIODN */
1941 u32 sdmmc2liodnr; /* SD/MMC 2 LIODN */
1942 u32 sdmmc3liodnr; /* SD/MMC 3 LIODN */
1943 u32 sdmmc4liodnr; /* SD/MMC 4 LIODN */
1944 u32 rio1maintliodnr;/* RIO 1 Maintenance LIODN */
1945 u32 rio2maintliodnr;/* RIO 2 Maintenance LIODN */
1946 u32 rio3maintliodnr;/* RIO 3 Maintenance LIODN */
1947 u32 rio4maintliodnr;/* RIO 4 Maintenance LIODN */
1948 u32 sata1liodnr; /* SATA 1 LIODN */
1949 u32 sata2liodnr; /* SATA 2 LIODN */
1950 u32 sata3liodnr; /* SATA 3 LIODN */
1951 u32 sata4liodnr; /* SATA 4 LIODN */
1952 u8 res22[32];
1953 u32 dma1liodnr; /* DMA 1 LIODN */
1954 u32 dma2liodnr; /* DMA 2 LIODN */
1955 u32 dma3liodnr; /* DMA 3 LIODN */
1956 u32 dma4liodnr; /* DMA 4 LIODN */
1957 u8 res23[48];
1958 u8 res24[64];
1959 u32 pblsr; /* Preboot loader status */
1960 u32 pamubypenr; /* PAMU bypass enable */
1961 u32 dmacr1; /* DMA control */
1962 u8 res25[4];
1963 u32 gensr1; /* General status */
1964 u8 res26[12];
1965 u32 gencr1; /* General control */
1966 u8 res27[12];
1967 u8 res28[4];
1968 u32 cgensrl; /* Core general status */
1969 u8 res29[8];
1970 u8 res30[4];
1971 u32 cgencrl; /* Core general control */
1972 u8 res31[184];
1973 u32 sriopstecr; /* SRIO prescaler timer enable control */
1974 u32 dcsrcr; /* DCSR Control register */
1975 u8 res31a[56];
1976 u32 tp_ityp[64]; /* Topology Initiator Type Register */
1977 struct {
1978 u32 upper;
1979 u32 lower;
1980 } tp_cluster[16]; /* Core Cluster n Topology Register */
1981 u8 res32[1344];
1982 u32 pmuxcr; /* Pin multiplexing control */
1983 u8 res33[60];
1984 u32 iovselsr; /* I/O voltage selection status */
1985 u8 res34[28];
1986 u32 ddrclkdr; /* DDR clock disable */
1987 u8 res35;
1988 u32 elbcclkdr; /* eLBC clock disable */
1989 u8 res36[20];
1990 u32 sdhcpcr; /* eSDHC polarity configuration */
1991 u8 res37[380];
1992 } ccsr_gur_t;
1993
1994 #define TP_ITYP_AV 0x00000001 /* Initiator available */
1995 #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
1996 #define TP_ITYP_TYPE_OTHER 0x0
1997 #define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */
1998 #define TP_ITYP_TYPE_SC 0x2 /* StarCore DSP */
1999 #define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
2000 #define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
2001 #define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */
2002
2003 #define TP_CLUSTER_EOC 0x80000000 /* end of clusters */
2004 #define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
2005 #define TP_INIT_PER_CLUSTER 4
2006
2007 #define FSL_CORENET_DCSR_SZ_MASK 0x00000003
2008 #define FSL_CORENET_DCSR_SZ_4M 0x0
2009 #define FSL_CORENET_DCSR_SZ_1G 0x3
2010
2011 /*
2012 * On p4080 we have an LIODN for msg unit (rmu) but not maintenance
2013 * everything after has RMan thus msg unit LIODN is used for maintenance
2014 */
2015 #define rmuliodnr rio1maintliodnr
2016
2017 typedef struct ccsr_clk {
2018 struct {
2019 u32 clkcncsr; /* core cluster n clock control status */
2020 u8 res_004[0x0c];
2021 u32 clkcgnhwacsr;/* clock generator n hardware accelerator */
2022 u8 res_014[0x0c];
2023 } clkcsr[12];
2024 u8 res_100[0x680]; /* 0x100 */
2025 struct {
2026 u32 pllcngsr;
2027 u8 res10[0x1c];
2028 } pllcgsr[12];
2029 u8 res21[0x280];
2030 u32 pllpgsr; /* 0xc00 Platform PLL General Status */
2031 u8 res16[0x1c];
2032 u32 plldgsr; /* 0xc20 DDR PLL General Status */
2033 u8 res17[0x3dc];
2034 } ccsr_clk_t;
2035
2036 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
2037 typedef struct ccsr_rcpm {
2038 u8 res_00[12];
2039 u32 tph10sr0; /* Thread PH10 Status Register */
2040 u8 res_10[12];
2041 u32 tph10setr0; /* Thread PH10 Set Control Register */
2042 u8 res_20[12];
2043 u32 tph10clrr0; /* Thread PH10 Clear Control Register */
2044 u8 res_30[12];
2045 u32 tph10psr0; /* Thread PH10 Previous Status Register */
2046 u8 res_40[12];
2047 u32 twaitsr0; /* Thread Wait Status Register */
2048 u8 res_50[96];
2049 u32 pcph15sr; /* Physical Core PH15 Status Register */
2050 u32 pcph15setr; /* Physical Core PH15 Set Control Register */
2051 u32 pcph15clrr; /* Physical Core PH15 Clear Control Register */
2052 u32 pcph15psr; /* Physical Core PH15 Prev Status Register */
2053 u8 res_c0[16];
2054 u32 pcph20sr; /* Physical Core PH20 Status Register */
2055 u32 pcph20setr; /* Physical Core PH20 Set Control Register */
2056 u32 pcph20clrr; /* Physical Core PH20 Clear Control Register */
2057 u32 pcph20psr; /* Physical Core PH20 Prev Status Register */
2058 u32 pcpw20sr; /* Physical Core PW20 Status Register */
2059 u8 res_e0[12];
2060 u32 pcph30sr; /* Physical Core PH30 Status Register */
2061 u32 pcph30setr; /* Physical Core PH30 Set Control Register */
2062 u32 pcph30clrr; /* Physical Core PH30 Clear Control Register */
2063 u32 pcph30psr; /* Physical Core PH30 Prev Status Register */
2064 u8 res_100[32];
2065 u32 ippwrgatecr; /* IP Power Gating Control Register */
2066 u8 res_124[12];
2067 u32 powmgtcsr; /* Power Management Control & Status Reg */
2068 u8 res_134[12];
2069 u32 ippdexpcr[4]; /* IP Powerdown Exception Control Reg */
2070 u8 res_150[12];
2071 u32 tpmimr0; /* Thread PM Interrupt Mask Reg */
2072 u8 res_160[12];
2073 u32 tpmcimr0; /* Thread PM Crit Interrupt Mask Reg */
2074 u8 res_170[12];
2075 u32 tpmmcmr0; /* Thread PM Machine Check Interrupt Mask Reg */
2076 u8 res_180[12];
2077 u32 tpmnmimr0; /* Thread PM NMI Mask Reg */
2078 u8 res_190[12];
2079 u32 tmcpmaskcr0; /* Thread Machine Check Mask Control Reg */
2080 u32 pctbenr; /* Physical Core Time Base Enable Reg */
2081 u32 pctbclkselr; /* Physical Core Time Base Clock Select */
2082 u32 tbclkdivr; /* Time Base Clock Divider Register */
2083 u8 res_1ac[4];
2084 u32 ttbhltcr[4]; /* Thread Time Base Halt Control Register */
2085 u32 clpcl10sr; /* Cluster PCL10 Status Register */
2086 u32 clpcl10setr; /* Cluster PCL30 Set Control Register */
2087 u32 clpcl10clrr; /* Cluster PCL30 Clear Control Register */
2088 u32 clpcl10psr; /* Cluster PCL30 Prev Status Register */
2089 u32 cddslpsetr; /* Core Domain Deep Sleep Set Register */
2090 u32 cddslpclrr; /* Core Domain Deep Sleep Clear Register */
2091 u32 cdpwroksetr; /* Core Domain Power OK Set Register */
2092 u32 cdpwrokclrr; /* Core Domain Power OK Clear Register */
2093 u32 cdpwrensr; /* Core Domain Power Enable Status Register */
2094 u32 cddslsr; /* Core Domain Deep Sleep Status Register */
2095 u8 res_1e8[8];
2096 u32 dslpcntcr[8]; /* Deep Sleep Counter Cfg Register */
2097 u8 res_300[3568];
2098 } ccsr_rcpm_t;
2099
2100 #define ctbenrl pctbenr
2101
2102 #else
2103 typedef struct ccsr_rcpm {
2104 u8 res1[4];
2105 u32 cdozsrl; /* Core Doze Status */
2106 u8 res2[4];
2107 u32 cdozcrl; /* Core Doze Control */
2108 u8 res3[4];
2109 u32 cnapsrl; /* Core Nap Status */
2110 u8 res4[4];
2111 u32 cnapcrl; /* Core Nap Control */
2112 u8 res5[4];
2113 u32 cdozpsrl; /* Core Doze Previous Status */
2114 u8 res6[4];
2115 u32 cdozpcrl; /* Core Doze Previous Control */
2116 u8 res7[4];
2117 u32 cwaitsrl; /* Core Wait Status */
2118 u8 res8[8];
2119 u32 powmgtcsr; /* Power Mangement Control & Status */
2120 u8 res9[12];
2121 u32 ippdexpcr0; /* IP Powerdown Exception Control 0 */
2122 u8 res10[12];
2123 u8 res11[4];
2124 u32 cpmimrl; /* Core PM IRQ Masking */
2125 u8 res12[4];
2126 u32 cpmcimrl; /* Core PM Critical IRQ Masking */
2127 u8 res13[4];
2128 u32 cpmmcimrl; /* Core PM Machine Check IRQ Masking */
2129 u8 res14[4];
2130 u32 cpmnmimrl; /* Core PM NMI Masking */
2131 u8 res15[4];
2132 u32 ctbenrl; /* Core Time Base Enable */
2133 u8 res16[4];
2134 u32 ctbclkselrl; /* Core Time Base Clock Select */
2135 u8 res17[4];
2136 u32 ctbhltcrl; /* Core Time Base Halt Control */
2137 u8 res18[0xf68];
2138 } ccsr_rcpm_t;
2139 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
2140
2141 #else
2142 typedef struct ccsr_gur {
2143 u32 porpllsr; /* POR PLL ratio status */
2144 #ifdef CONFIG_MPC8536
2145 #define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000
2146 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25
2147 #elif defined(CONFIG_PPC_C29X)
2148 #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00
2149 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT (9 - ((gur->pordevsr2 \
2150 & MPC85xx_PORDEVSR2_DDR_SPD_0) \
2151 >> MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT))
2152 #else
2153 #if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132)
2154 #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00
2155 #else
2156 #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00
2157 #endif
2158 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9
2159 #endif
2160 #define MPC85xx_PORPLLSR_QE_RATIO 0x3e000000
2161 #define MPC85xx_PORPLLSR_QE_RATIO_SHIFT 25
2162 #define MPC85xx_PORPLLSR_PLAT_RATIO 0x0000003e
2163 #define MPC85xx_PORPLLSR_PLAT_RATIO_SHIFT 1
2164 u32 porbmsr; /* POR boot mode status */
2165 #define MPC85xx_PORBMSR_HA 0x00070000
2166 #define MPC85xx_PORBMSR_HA_SHIFT 16
2167 #define MPC85xx_PORBMSR_ROMLOC_SHIFT 24
2168 #define PORBMSR_ROMLOC_SPI 0x6
2169 #define PORBMSR_ROMLOC_SDHC 0x7
2170 #define PORBMSR_ROMLOC_NAND_2K 0x9
2171 #define PORBMSR_ROMLOC_NOR 0xf
2172 u32 porimpscr; /* POR I/O impedance status & control */
2173 u32 pordevsr; /* POR I/O device status regsiter */
2174 #if defined(CONFIG_P1017) || defined(CONFIG_P1023)
2175 #define MPC85xx_PORDEVSR_SGMII1_DIS 0x10000000
2176 #define MPC85xx_PORDEVSR_SGMII2_DIS 0x08000000
2177 #define MPC85xx_PORDEVSR_TSEC1_PRTC 0x02000000
2178 #else
2179 #define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000
2180 #define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000
2181 #endif
2182 #define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000
2183 #define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000
2184 #define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000
2185 #define MPC85xx_PORDEVSR_PCI1 0x00800000
2186 #if defined(CONFIG_P1013) || defined(CONFIG_P1022)
2187 #define MPC85xx_PORDEVSR_IO_SEL 0x007c0000
2188 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 18
2189 #elif defined(CONFIG_P1017) || defined(CONFIG_P1023)
2190 #define MPC85xx_PORDEVSR_IO_SEL 0x00600000
2191 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
2192 #else
2193 #if defined(CONFIG_P1010)
2194 #define MPC85xx_PORDEVSR_IO_SEL 0x00600000
2195 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
2196 #elif defined(CONFIG_BSC9132)
2197 #define MPC85xx_PORDEVSR_IO_SEL 0x00FE0000
2198 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 17
2199 #elif defined(CONFIG_PPC_C29X)
2200 #define MPC85xx_PORDEVSR_IO_SEL 0x00e00000
2201 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
2202 #else
2203 #define MPC85xx_PORDEVSR_IO_SEL 0x00780000
2204 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19
2205 #endif /* if defined(CONFIG_P1010) */
2206 #endif
2207 #define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000
2208 #define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000
2209 #define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000
2210 #define MPC85xx_PORDEVSR_PCI1_SPD 0x00008000
2211 #define MPC85xx_PORDEVSR_PCI2_SPD 0x00004000
2212 #define MPC85xx_PORDEVSR_DRAM_RTYPE 0x00000060
2213 #define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008
2214 #define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007
2215 u32 pordbgmsr; /* POR debug mode status */
2216 u32 pordevsr2; /* POR I/O device status 2 */
2217 #if defined(CONFIG_PPC_C29X)
2218 #define MPC85xx_PORDEVSR2_DDR_SPD_0 0x00000008
2219 #define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT 3
2220 #endif
2221 /* The 8544 RM says this is bit 26, but it's really bit 24 */
2222 #define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080
2223 u8 res1[8];
2224 u32 gpporcr; /* General-purpose POR configuration */
2225 u8 res2[12];
2226 #if defined(CONFIG_MPC8536)
2227 u32 gencfgr; /* General Configuration Register */
2228 #define MPC85xx_GENCFGR_SDHC_WP_INV 0x20000000
2229 #else
2230 u32 gpiocr; /* GPIO control */
2231 #endif
2232 u8 res3[12];
2233 #if defined(CONFIG_MPC8569)
2234 u32 plppar1; /* Platform port pin assignment 1 */
2235 u32 plppar2; /* Platform port pin assignment 2 */
2236 u32 plpdir1; /* Platform port pin direction 1 */
2237 u32 plpdir2; /* Platform port pin direction 2 */
2238 #else
2239 u32 gpoutdr; /* General-purpose output data */
2240 u8 res4[12];
2241 #endif
2242 u32 gpindr; /* General-purpose input data */
2243 u8 res5[12];
2244 u32 pmuxcr; /* Alt. function signal multiplex control */
2245 #if defined(CONFIG_P1010) || defined(CONFIG_P1014)
2246 #define MPC85xx_PMUXCR_TSEC1_0_1588 0x40000000
2247 #define MPC85xx_PMUXCR_TSEC1_0_RES 0xC0000000
2248 #define MPC85xx_PMUXCR_TSEC1_1_1588_TRIG 0x10000000
2249 #define MPC85xx_PMUXCR_TSEC1_1_GPIO_12 0x20000000
2250 #define MPC85xx_PMUXCR_TSEC1_1_RES 0x30000000
2251 #define MPC85xx_PMUXCR_TSEC1_2_DMA 0x04000000
2252 #define MPC85xx_PMUXCR_TSEC1_2_GPIO 0x08000000
2253 #define MPC85xx_PMUXCR_TSEC1_2_RES 0x0C000000
2254 #define MPC85xx_PMUXCR_TSEC1_3_RES 0x01000000
2255 #define MPC85xx_PMUXCR_TSEC1_3_GPIO_15 0x02000000
2256 #define MPC85xx_PMUXCR_IFC_ADDR16_SDHC 0x00400000
2257 #define MPC85xx_PMUXCR_IFC_ADDR16_USB 0x00800000
2258 #define MPC85xx_PMUXCR_IFC_ADDR16_IFC_CS2 0x00C00000
2259 #define MPC85xx_PMUXCR_IFC_ADDR17_18_SDHC 0x00100000
2260 #define MPC85xx_PMUXCR_IFC_ADDR17_18_USB 0x00200000
2261 #define MPC85xx_PMUXCR_IFC_ADDR17_18_DMA 0x00300000
2262 #define MPC85xx_PMUXCR_IFC_ADDR19_SDHC_DATA 0x00040000
2263 #define MPC85xx_PMUXCR_IFC_ADDR19_USB 0x00080000
2264 #define MPC85xx_PMUXCR_IFC_ADDR19_DMA 0x000C0000
2265 #define MPC85xx_PMUXCR_IFC_ADDR20_21_SDHC_DATA 0x00010000
2266 #define MPC85xx_PMUXCR_IFC_ADDR20_21_USB 0x00020000
2267 #define MPC85xx_PMUXCR_IFC_ADDR20_21_RES 0x00030000
2268 #define MPC85xx_PMUXCR_IFC_ADDR22_SDHC 0x00004000
2269 #define MPC85xx_PMUXCR_IFC_ADDR22_USB 0x00008000
2270 #define MPC85xx_PMUXCR_IFC_ADDR22_RES 0x0000C000
2271 #define MPC85xx_PMUXCR_IFC_ADDR23_SDHC 0x00001000
2272 #define MPC85xx_PMUXCR_IFC_ADDR23_USB 0x00002000
2273 #define MPC85xx_PMUXCR_IFC_ADDR23_RES 0x00003000
2274 #define MPC85xx_PMUXCR_IFC_ADDR24_SDHC 0x00000400
2275 #define MPC85xx_PMUXCR_IFC_ADDR24_USB 0x00000800
2276 #define MPC85xx_PMUXCR_IFC_ADDR24_RES 0x00000C00
2277 #define MPC85xx_PMUXCR_IFC_PAR_PERR_RES 0x00000300
2278 #define MPC85xx_PMUXCR_IFC_PAR_PERR_USB 0x00000200
2279 #define MPC85xx_PMUXCR_LCLK_RES 0x00000040
2280 #define MPC85xx_PMUXCR_LCLK_USB 0x00000080
2281 #define MPC85xx_PMUXCR_LCLK_IFC_CS3 0x000000C0
2282 #define MPC85xx_PMUXCR_SPI_RES 0x00000030
2283 #define MPC85xx_PMUXCR_SPI_GPIO 0x00000020
2284 #define MPC85xx_PMUXCR_CAN1_UART 0x00000004
2285 #define MPC85xx_PMUXCR_CAN1_TDM 0x00000008
2286 #define MPC85xx_PMUXCR_CAN1_RES 0x0000000C
2287 #define MPC85xx_PMUXCR_CAN2_UART 0x00000001
2288 #define MPC85xx_PMUXCR_CAN2_TDM 0x00000002
2289 #define MPC85xx_PMUXCR_CAN2_RES 0x00000003
2290 #endif
2291 #if defined(CONFIG_P1017) || defined(CONFIG_P1023)
2292 #define MPC85xx_PMUXCR_TSEC1_1 0x10000000
2293 #else
2294 #define MPC85xx_PMUXCR_SD_DATA 0x80000000
2295 #define MPC85xx_PMUXCR_SDHC_CD 0x40000000
2296 #define MPC85xx_PMUXCR_SDHC_WP 0x20000000
2297 #define MPC85xx_PMUXCR_ELBC_OFF_USB2_ON 0x01000000
2298 #define MPC85xx_PMUXCR_TDM_ENA 0x00800000
2299 #define MPC85xx_PMUXCR_QE0 0x00008000
2300 #define MPC85xx_PMUXCR_QE1 0x00004000
2301 #define MPC85xx_PMUXCR_QE2 0x00002000
2302 #define MPC85xx_PMUXCR_QE3 0x00001000
2303 #define MPC85xx_PMUXCR_QE4 0x00000800
2304 #define MPC85xx_PMUXCR_QE5 0x00000400
2305 #define MPC85xx_PMUXCR_QE6 0x00000200
2306 #define MPC85xx_PMUXCR_QE7 0x00000100
2307 #define MPC85xx_PMUXCR_QE8 0x00000080
2308 #define MPC85xx_PMUXCR_QE9 0x00000040
2309 #define MPC85xx_PMUXCR_QE10 0x00000020
2310 #define MPC85xx_PMUXCR_QE11 0x00000010
2311 #define MPC85xx_PMUXCR_QE12 0x00000008
2312 #endif
2313 #if defined(CONFIG_P1013) || defined(CONFIG_P1022)
2314 #define MPC85xx_PMUXCR_TDM_MASK 0x0001cc00
2315 #define MPC85xx_PMUXCR_TDM 0x00014800
2316 #define MPC85xx_PMUXCR_SPI_MASK 0x00600000
2317 #define MPC85xx_PMUXCR_SPI 0x00000000
2318 #endif
2319 #if defined(CONFIG_BSC9131)
2320 #define MPC85xx_PMUXCR_TSEC2_DMA_GPIO_IRQ 0x40000000
2321 #define MPC85xx_PMUXCR_TSEC2_USB 0xC0000000
2322 #define MPC85xx_PMUXCR_TSEC2_1588_PPS 0x10000000
2323 #define MPC85xx_PMUXCR_TSEC2_1588_RSVD 0x30000000
2324 #define MPC85xx_PMUXCR_IFC_AD_GPIO 0x04000000
2325 #define MPC85xx_PMUXCR_IFC_AD_GPIO_MASK 0x0C000000
2326 #define MPC85xx_PMUXCR_IFC_AD15_GPIO 0x01000000
2327 #define MPC85xx_PMUXCR_IFC_AD15_TIMER2 0x02000000
2328 #define MPC85xx_PMUXCR_IFC_AD16_GPO8 0x00400000
2329 #define MPC85xx_PMUXCR_IFC_AD16_MSRCID0 0x00800000
2330 #define MPC85xx_PMUXCR_IFC_AD17_GPO 0x00100000
2331 #define MPC85xx_PMUXCR_IFC_AD17_GPO_MASK 0x00300000
2332 #define MPC85xx_PMUXCR_IFC_AD17_MSRCID_DSP 0x00200000
2333 #define MPC85xx_PMUXCR_IFC_CS2_GPO65 0x00040000
2334 #define MPC85xx_PMUXCR_IFC_CS2_DSP_TDI 0x00080000
2335 #define MPC85xx_PMUXCR_SDHC_USIM 0x00010000
2336 #define MPC85xx_PMUXCR_SDHC_TDM_RFS_RCK 0x00020000
2337 #define MPC85xx_PMUXCR_SDHC_GPIO77 0x00030000
2338 #define MPC85xx_PMUXCR_SDHC_RESV 0x00004000
2339 #define MPC85xx_PMUXCR_SDHC_TDM_TXD_RXD 0x00008000
2340 #define MPC85xx_PMUXCR_SDHC_GPIO_TIMER4 0x0000C000
2341 #define MPC85xx_PMUXCR_USB_CLK_UART_SIN 0x00001000
2342 #define MPC85xx_PMUXCR_USB_CLK_GPIO69 0x00002000
2343 #define MPC85xx_PMUXCR_USB_CLK_TIMER3 0x00003000
2344 #define MPC85xx_PMUXCR_USB_UART_GPIO0 0x00000400
2345 #define MPC85xx_PMUXCR_USB_RSVD 0x00000C00
2346 #define MPC85xx_PMUXCR_USB_GPIO62_TRIG_IN 0x00000800
2347 #define MPC85xx_PMUXCR_USB_D1_2_IIC2_SDA_SCL 0x00000100
2348 #define MPC85xx_PMUXCR_USB_D1_2_GPIO71_72 0x00000200
2349 #define MPC85xx_PMUXCR_USB_D1_2_RSVD 0x00000300
2350 #define MPC85xx_PMUXCR_USB_DIR_GPIO2 0x00000040
2351 #define MPC85xx_PMUXCR_USB_DIR_TIMER1 0x00000080
2352 #define MPC85xx_PMUXCR_USB_DIR_MCP_B 0x000000C0
2353 #define MPC85xx_PMUXCR_SPI1_UART3 0x00000010
2354 #define MPC85xx_PMUXCR_SPI1_SIM 0x00000020
2355 #define MPC85xx_PMUXCR_SPI1_CKSTP_IN_GPO74 0x00000030
2356 #define MPC85xx_PMUXCR_SPI1_CS2_CKSTP_OUT_B 0x00000004
2357 #define MPC85xx_PMUXCR_SPI1_CS2_dbg_adi1_rxen 0x00000008
2358 #define MPC85xx_PMUXCR_SPI1_CS2_GPO75 0x0000000C
2359 #define MPC85xx_PMUXCR_SPI1_CS3_ANT_TCXO_PWM 0x00000001
2360 #define MPC85xx_PMUXCR_SPI1_CS3_dbg_adi2_rxen 0x00000002
2361 #define MPC85xx_PMUXCR_SPI1_CS3_GPO76 0x00000003
2362 #endif
2363 #ifdef CONFIG_BSC9132
2364 #define MPC85xx_PMUXCR0_SIM_SEL_MASK 0x0003b000
2365 #define MPC85xx_PMUXCR0_SIM_SEL 0x00014000
2366 #endif
2367 #if defined(CONFIG_PPC_C29X)
2368 #define MPC85xx_PMUXCR_SPI_MASK 0x00000300
2369 #define MPC85xx_PMUXCR_SPI 0x00000000
2370 #define MPC85xx_PMUXCR_SPI_GPIO 0x00000100
2371 #endif
2372 u32 pmuxcr2; /* Alt. function signal multiplex control 2 */
2373 #if defined(CONFIG_P1010) || defined(CONFIG_P1014)
2374 #define MPC85xx_PMUXCR2_UART_GPIO 0x40000000
2375 #define MPC85xx_PMUXCR2_UART_TDM 0x80000000
2376 #define MPC85xx_PMUXCR2_UART_RES 0xC0000000
2377 #define MPC85xx_PMUXCR2_IRQ2_TRIG_IN 0x10000000
2378 #define MPC85xx_PMUXCR2_IRQ2_RES 0x30000000
2379 #define MPC85xx_PMUXCR2_IRQ3_SRESET 0x04000000
2380 #define MPC85xx_PMUXCR2_IRQ3_RES 0x0C000000
2381 #define MPC85xx_PMUXCR2_GPIO01_DRVVBUS 0x01000000
2382 #define MPC85xx_PMUXCR2_GPIO01_RES 0x03000000
2383 #define MPC85xx_PMUXCR2_GPIO23_CKSTP 0x00400000
2384 #define MPC85xx_PMUXCR2_GPIO23_RES 0x00800000
2385 #define MPC85xx_PMUXCR2_GPIO23_USB 0x00C00000
2386 #define MPC85xx_PMUXCR2_GPIO4_MCP 0x00100000
2387 #define MPC85xx_PMUXCR2_GPIO4_RES 0x00200000
2388 #define MPC85xx_PMUXCR2_GPIO4_CLK_OUT 0x00300000
2389 #define MPC85xx_PMUXCR2_GPIO5_UDE 0x00040000
2390 #define MPC85xx_PMUXCR2_GPIO5_RES 0x00080000
2391 #define MPC85xx_PMUXCR2_READY_ASLEEP 0x00020000
2392 #define MPC85xx_PMUXCR2_DDR_ECC_MUX 0x00010000
2393 #define MPC85xx_PMUXCR2_DEBUG_PORT_EXPOSE 0x00008000
2394 #define MPC85xx_PMUXCR2_POST_EXPOSE 0x00004000
2395 #define MPC85xx_PMUXCR2_DEBUG_MUX_SEL_USBPHY 0x00002000
2396 #define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE 0x00001000
2397 #endif
2398 #if defined(CONFIG_P1013) || defined(CONFIG_P1022)
2399 #define MPC85xx_PMUXCR2_ETSECUSB_MASK 0x001f8000
2400 #define MPC85xx_PMUXCR2_USB 0x00150000
2401 #endif
2402 #if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132)
2403 #if defined(CONFIG_BSC9131)
2404 #define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD 0X40000000
2405 #define MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS 0X80000000
2406 #define MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42 0xC0000000
2407 #define MPC85xx_PMUXCR2_UART_RTS_B0_PWM2 0x10000000
2408 #define MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK 0x20000000
2409 #define MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43 0x30000000
2410 #define MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD 0x04000000
2411 #define MPC85xx_PMUXCR2_UART_CTS_B1_SRESET_B 0x08000000
2412 #define MPC85xx_PMUXCR2_UART_CTS_B1_GPIO44 0x0C000000
2413 #define MPC85xx_PMUXCR2_UART_RTS_B1_PPS_LED 0x01000000
2414 #define MPC85xx_PMUXCR2_UART_RTS_B1_RSVD 0x02000000
2415 #define MPC85xx_PMUXCR2_UART_RTS_B1_GPIO45 0x03000000
2416 #define MPC85xx_PMUXCR2_TRIG_OUT_ASLEEP 0x00400000
2417 #define MPC85xx_PMUXCR2_TRIG_OUT_DSP_TRST_B 0x00800000
2418 #define MPC85xx_PMUXCR2_ANT1_TIMER5 0x00100000
2419 #define MPC85xx_PMUXCR2_ANT1_TSEC_1588 0x00200000
2420 #define MPC85xx_PMUXCR2_ANT1_GPIO95_19 0x00300000
2421 #define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_MAX3_LOCK 0x00040000
2422 #define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_RSVD 0x00080000
2423 #define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_GPIO80_20 0x000C0000
2424 #define MPC85xx_PMUXCR2_ANT1_DIO0_3_SPI3_CS0 0x00010000
2425 #define MPC85xx_PMUXCR2_ANT1_DIO0_3_ANT2_DO_3 0x00020000
2426 #define MPC85xx_PMUXCR2_ANT1_DIO0_3_GPIO81_84 0x00030000
2427 #define MPC85xx_PMUXCR2_ANT1_DIO4_7_SPI4 0x00004000
2428 #define MPC85xx_PMUXCR2_ANT1_DIO4_7_ANT2_DO4_7 0x00008000
2429 #define MPC85xx_PMUXCR2_ANT1_DIO4_7_GPIO85_88 0x0000C000
2430 #define MPC85xx_PMUXCR2_ANT1_DIO8_9_MAX2_1_LOCK 0x00001000
2431 #define MPC85xx_PMUXCR2_ANT1_DIO8_9_ANT2_DO8_9 0x00002000
2432 #define MPC85xx_PMUXCR2_ANT1_DIO8_9_GPIO21_22 0x00003000
2433 #define MPC85xx_PMUXCR2_ANT1_DIO10_11_TIMER6_7 0x00000400
2434 #define MPC85xx_PMUXCR2_ANT1_DIO10_11_ANT2_DO10_11 0x00000800
2435 #define MPC85xx_PMUXCR2_ANT1_DIO10_11_GPIO23_24 0x00000C00
2436 #define MPC85xx_PMUXCR2_ANT2_RSVD 0x00000100
2437 #define MPC85xx_PMUXCR2_ANT2_GPO90_91_DMA 0x00000300
2438 #define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_USB 0x00000040
2439 #define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_GPIO 0x000000C0
2440 #define MPC85xx_PMUXCR2_ANT2_DIO11_RSVD 0x00000010
2441 #define MPC85xx_PMUXCR2_ANT2_DIO11_TIMER8 0x00000020
2442 #define MPC85xx_PMUXCR2_ANT2_DIO11_GPIO61 0x00000030
2443 #define MPC85xx_PMUXCR2_ANT3_AGC_GPO53 0x00000004
2444 #define MPC85xx_PMUXCR2_ANT3_DO_TDM 0x00000001
2445 #define MPC85xx_PMUXCR2_ANT3_DO_GPIO46_49 0x00000002
2446 #endif
2447 u32 pmuxcr3;
2448 #if defined(CONFIG_BSC9131)
2449 #define MPC85xx_PMUXCR3_ANT3_DO4_5_TDM 0x40000000
2450 #define MPC85xx_PMUXCR3_ANT3_DO4_5_GPIO_50_51 0x80000000
2451 #define MPC85xx_PMUXCR3_ANT3_DO6_7_TRIG_IN_SRESET_B 0x10000000
2452 #define MPC85xx_PMUXCR3_ANT3_DO6_7_GPIO_52_53 0x20000000
2453 #define MPC85xx_PMUXCR3_ANT3_DO8_MCP_B 0x04000000
2454 #define MPC85xx_PMUXCR3_ANT3_DO8_GPIO54 0x08000000
2455 #define MPC85xx_PMUXCR3_ANT3_DO9_10_CKSTP_IN_OUT 0x01000000
2456 #define MPC85xx_PMUXCR3_ANT3_DO9_10_GPIO55_56 0x02000000
2457 #define MPC85xx_PMUXCR3_ANT3_DO11_IRQ_OUT 0x00400000
2458 #define MPC85xx_PMUXCR3_ANT3_DO11_GPIO57 0x00800000
2459 #define MPC85xx_PMUXCR3_SPI2_CS2_GPO93 0x00100000
2460 #define MPC85xx_PMUXCR3_SPI2_CS3_GPO94 0x00040000
2461 #define MPC85xx_PMUXCR3_ANT2_AGC_RSVD 0x00010000
2462 #define MPC85xx_PMUXCR3_ANT2_GPO89 0x00030000
2463 #endif
2464 #ifdef CONFIG_BSC9132
2465 #define MPC85xx_PMUXCR3_USB_SEL_MASK 0x0000ff00
2466 #define MPC85xx_PMUXCR3_UART2_SEL 0x00005000
2467 #define MPC85xx_PMUXCR3_UART3_SEL_MASK 0xc0000000
2468 #define MPC85xx_PMUXCR3_UART3_SEL 0x40000000
2469 #endif
2470 u32 pmuxcr4;
2471 #else
2472 u8 res6[8];
2473 #endif
2474 u32 devdisr; /* Device disable control */
2475 #define MPC85xx_DEVDISR_PCI1 0x80000000
2476 #define MPC85xx_DEVDISR_PCI2 0x40000000
2477 #define MPC85xx_DEVDISR_PCIE 0x20000000
2478 #define MPC85xx_DEVDISR_LBC 0x08000000
2479 #define MPC85xx_DEVDISR_PCIE2 0x04000000
2480 #define MPC85xx_DEVDISR_PCIE3 0x02000000
2481 #define MPC85xx_DEVDISR_SEC 0x01000000
2482 #define MPC85xx_DEVDISR_SRIO 0x00080000
2483 #define MPC85xx_DEVDISR_RMSG 0x00040000
2484 #define MPC85xx_DEVDISR_DDR 0x00010000
2485 #define MPC85xx_DEVDISR_CPU 0x00008000
2486 #define MPC85xx_DEVDISR_CPU0 MPC85xx_DEVDISR_CPU
2487 #define MPC85xx_DEVDISR_TB 0x00004000
2488 #define MPC85xx_DEVDISR_TB0 MPC85xx_DEVDISR_TB
2489 #define MPC85xx_DEVDISR_CPU1 0x00002000
2490 #define MPC85xx_DEVDISR_TB1 0x00001000
2491 #define MPC85xx_DEVDISR_DMA 0x00000400
2492 #define MPC85xx_DEVDISR_TSEC1 0x00000080
2493 #define MPC85xx_DEVDISR_TSEC2 0x00000040
2494 #define MPC85xx_DEVDISR_TSEC3 0x00000020
2495 #define MPC85xx_DEVDISR_TSEC4 0x00000010
2496 #define MPC85xx_DEVDISR_I2C 0x00000004
2497 #define MPC85xx_DEVDISR_DUART 0x00000002
2498 u8 res7[12];
2499 u32 powmgtcsr; /* Power management status & control */
2500 u8 res8[12];
2501 u32 mcpsumr; /* Machine check summary */
2502 u8 res9[12];
2503 u32 pvr; /* Processor version */
2504 u32 svr; /* System version */
2505 u8 res10[8];
2506 u32 rstcr; /* Reset control */
2507 #if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569)
2508 u8 res11a[76];
2509 par_io_t qe_par_io[7];
2510 u8 res11b[1600];
2511 #elif defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
2512 u8 res11a[12];
2513 u32 iovselsr;
2514 u8 res11b[60];
2515 par_io_t qe_par_io[3];
2516 u8 res11c[1496];
2517 #else
2518 u8 res11a[1868];
2519 #endif
2520 u32 clkdvdr; /* Clock Divide register */
2521 u8 res12[1532];
2522 u32 clkocr; /* Clock out select */
2523 u8 res13[12];
2524 u32 ddrdllcr; /* DDR DLL control */
2525 u8 res14[12];
2526 u32 lbcdllcr; /* LBC DLL control */
2527 #if defined(CONFIG_BSC9131)
2528 u8 res15[12];
2529 u32 halt_req_mask;
2530 #define HALTED_TO_HALT_REQ_MASK_0 0x80000000
2531 u8 res18[232];
2532 #else
2533 u8 res15[248];
2534 #endif
2535 u32 lbiuiplldcr0; /* LBIU PLL Debug Reg 0 */
2536 u32 lbiuiplldcr1; /* LBIU PLL Debug Reg 1 */
2537 u32 ddrioovcr; /* DDR IO Override Control */
2538 u32 tsec12ioovcr; /* eTSEC 1/2 IO override control */
2539 u32 tsec34ioovcr; /* eTSEC 3/4 IO override control */
2540 u8 res16[52];
2541 u32 sdhcdcr; /* SDHC debug control register */
2542 u8 res17[61592];
2543 } ccsr_gur_t;
2544 #endif
2545
2546 #define SDHCDCR_CD_INV 0x80000000 /* invert SDHC card detect */
2547
2548 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
2549 #define MAX_SERDES 4
2550 #define SRDS_MAX_LANES 8
2551 #define SRDS_MAX_BANK 2
2552 typedef struct serdes_corenet {
2553 struct {
2554 u32 rstctl; /* Reset Control Register */
2555 #define SRDS_RSTCTL_RST 0x80000000
2556 #define SRDS_RSTCTL_RSTDONE 0x40000000
2557 #define SRDS_RSTCTL_RSTERR 0x20000000
2558 #define SRDS_RSTCTL_SWRST 0x10000000
2559 #define SRDS_RSTCTL_SDEN 0x00000020
2560 #define SRDS_RSTCTL_SDRST_B 0x00000040
2561 #define SRDS_RSTCTL_PLLRST_B 0x00000080
2562 u32 pllcr0; /* PLL Control Register 0 */
2563 #define SRDS_PLLCR0_POFF 0x80000000
2564 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
2565 #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
2566 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
2567 #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
2568 #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
2569 #define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
2570 #define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000
2571 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000
2572 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
2573 #define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000
2574 #define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000
2575 #define SRDS_PLLCR0_FRATE_SEL_4 0x00070000
2576 #define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000
2577 #define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000
2578 u32 pllcr1; /* PLL Control Register 1 */
2579 #define SRDS_PLLCR1_PLL_BWSEL 0x08000000
2580 u32 res_0c; /* 0x00c */
2581 u32 pllcr3;
2582 u32 pllcr4;
2583 u8 res_18[0x20-0x18];
2584 } bank[2];
2585 u8 res_40[0x90-0x40];
2586 u32 srdstcalcr; /* 0x90 TX Calibration Control */
2587 u8 res_94[0xa0-0x94];
2588 u32 srdsrcalcr; /* 0xa0 RX Calibration Control */
2589 u8 res_a4[0xb0-0xa4];
2590 u32 srdsgr0; /* 0xb0 General Register 0 */
2591 u8 res_b4[0xe0-0xb4];
2592 u32 srdspccr0; /* 0xe0 Protocol Converter Config 0 */
2593 u32 srdspccr1; /* 0xe4 Protocol Converter Config 1 */
2594 u32 srdspccr2; /* 0xe8 Protocol Converter Config 2 */
2595 u32 srdspccr3; /* 0xec Protocol Converter Config 3 */
2596 u32 srdspccr4; /* 0xf0 Protocol Converter Config 4 */
2597 u8 res_f4[0x100-0xf4];
2598 struct {
2599 u32 lnpssr; /* 0x100, 0x120, ..., 0x1e0 */
2600 u8 res_104[0x120-0x104];
2601 } srdslnpssr[8];
2602 u8 res_200[0x800-0x200];
2603 struct {
2604 u32 gcr0; /* 0x800 General Control Register 0 */
2605 u32 gcr1; /* 0x804 General Control Register 1 */
2606 u32 gcr2; /* 0x808 General Control Register 2 */
2607 u32 res_80c;
2608 u32 recr0; /* 0x810 Receive Equalization Control */
2609 u32 res_814;
2610 u32 tecr0; /* 0x818 Transmit Equalization Control */
2611 u32 res_81c;
2612 u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */
2613 u8 res_824[0x840-0x824];
2614 } lane[8]; /* Lane A, B, C, D, E, F, G, H */
2615 u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */
2616 } serdes_corenet_t;
2617
2618 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
2619
2620 #define SRDS_MAX_LANES 18
2621 #define SRDS_MAX_BANK 3
2622 typedef struct serdes_corenet {
2623 struct {
2624 u32 rstctl; /* Reset Control Register */
2625 #define SRDS_RSTCTL_RST 0x80000000
2626 #define SRDS_RSTCTL_RSTDONE 0x40000000
2627 #define SRDS_RSTCTL_RSTERR 0x20000000
2628 #define SRDS_RSTCTL_SDPD 0x00000020
2629 u32 pllcr0; /* PLL Control Register 0 */
2630 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
2631 #define SRDS_PLLCR0_PVCOCNT_EN 0x02000000
2632 #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
2633 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
2634 #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
2635 #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
2636 #define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
2637 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x00030000
2638 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
2639 #define SRDS_PLLCR0_FRATE_SEL_6_25 0x00010000
2640 u32 pllcr1; /* PLL Control Register 1 */
2641 #define SRDS_PLLCR1_PLL_BWSEL 0x08000000
2642 u32 res[5];
2643 } bank[3];
2644 u32 res1[12];
2645 u32 srdstcalcr; /* TX Calibration Control */
2646 u32 res2[3];
2647 u32 srdsrcalcr; /* RX Calibration Control */
2648 u32 res3[3];
2649 u32 srdsgr0; /* General Register 0 */
2650 u32 res4[11];
2651 u32 srdspccr0; /* Protocol Converter Config 0 */
2652 u32 srdspccr1; /* Protocol Converter Config 1 */
2653 u32 srdspccr2; /* Protocol Converter Config 2 */
2654 #define SRDS_PCCR2_RST_XGMII1 0x00800000
2655 #define SRDS_PCCR2_RST_XGMII2 0x00400000
2656 u32 res5[197];
2657 struct serdes_lane {
2658 u32 gcr0; /* General Control Register 0 */
2659 #define SRDS_GCR0_RRST 0x00400000
2660 #define SRDS_GCR0_1STLANE 0x00010000
2661 #define SRDS_GCR0_UOTHL 0x00100000
2662 u32 gcr1; /* General Control Register 1 */
2663 #define SRDS_GCR1_REIDL_CTL_MASK 0x001f0000
2664 #define SRDS_GCR1_REIDL_CTL_PCIE 0x00100000
2665 #define SRDS_GCR1_REIDL_CTL_SRIO 0x00000000
2666 #define SRDS_GCR1_REIDL_CTL_SGMII 0x00040000
2667 #define SRDS_GCR1_OPAD_CTL 0x04000000
2668 u32 res1[4];
2669 u32 tecr0; /* TX Equalization Control Reg 0 */
2670 #define SRDS_TECR0_TEQ_TYPE_MASK 0x30000000
2671 #define SRDS_TECR0_TEQ_TYPE_2LVL 0x10000000
2672 u32 res3;
2673 u32 ttlcr0; /* Transition Tracking Loop Ctrl 0 */
2674 #define SRDS_TTLCR0_FLT_SEL_MASK 0x3f000000
2675 #define SRDS_TTLCR0_FLT_SEL_KFR_26 0x10000000
2676 #define SRDS_TTLCR0_FLT_SEL_KPH_28 0x08000000
2677 #define SRDS_TTLCR0_FLT_SEL_750PPM 0x03000000
2678 #define SRDS_TTLCR0_PM_DIS 0x00004000
2679 #define SRDS_TTLCR0_FREQOVD_EN 0x00000001
2680 u32 res4[7];
2681 } lane[24];
2682 u32 res6[384];
2683 } serdes_corenet_t;
2684 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
2685
2686 enum {
2687 FSL_SRDS_B1_LANE_A = 0,
2688 FSL_SRDS_B1_LANE_B = 1,
2689 FSL_SRDS_B1_LANE_C = 2,
2690 FSL_SRDS_B1_LANE_D = 3,
2691 FSL_SRDS_B1_LANE_E = 4,
2692 FSL_SRDS_B1_LANE_F = 5,
2693 FSL_SRDS_B1_LANE_G = 6,
2694 FSL_SRDS_B1_LANE_H = 7,
2695 FSL_SRDS_B1_LANE_I = 8,
2696 FSL_SRDS_B1_LANE_J = 9,
2697 FSL_SRDS_B2_LANE_A = 16,
2698 FSL_SRDS_B2_LANE_B = 17,
2699 FSL_SRDS_B2_LANE_C = 18,
2700 FSL_SRDS_B2_LANE_D = 19,
2701 FSL_SRDS_B3_LANE_A = 20,
2702 FSL_SRDS_B3_LANE_B = 21,
2703 FSL_SRDS_B3_LANE_C = 22,
2704 FSL_SRDS_B3_LANE_D = 23,
2705 };
2706
2707 /* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
2708 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
2709 typedef struct ccsr_sec {
2710 u32 res0;
2711 u32 mcfgr; /* Master CFG Register */
2712 u8 res1[0x8];
2713 struct {
2714 u32 ms; /* Job Ring LIODN Register, MS */
2715 u32 ls; /* Job Ring LIODN Register, LS */
2716 } jrliodnr[4];
2717 u8 res2[0x30];
2718 struct {
2719 u32 ms; /* RTIC LIODN Register, MS */
2720 u32 ls; /* RTIC LIODN Register, LS */
2721 } rticliodnr[4];
2722 u8 res3[0x1c];
2723 u32 decorr; /* DECO Request Register */
2724 struct {
2725 u32 ms; /* DECO LIODN Register, MS */
2726 u32 ls; /* DECO LIODN Register, LS */
2727 } decoliodnr[8];
2728 u8 res4[0x40];
2729 u32 dar; /* DECO Avail Register */
2730 u32 drr; /* DECO Reset Register */
2731 u8 res5[0xe78];
2732 u32 crnr_ms; /* CHA Revision Number Register, MS */
2733 u32 crnr_ls; /* CHA Revision Number Register, LS */
2734 u32 ctpr_ms; /* Compile Time Parameters Register, MS */
2735 u32 ctpr_ls; /* Compile Time Parameters Register, LS */
2736 u8 res6[0x10];
2737 u32 far_ms; /* Fault Address Register, MS */
2738 u32 far_ls; /* Fault Address Register, LS */
2739 u32 falr; /* Fault Address LIODN Register */
2740 u32 fadr; /* Fault Address Detail Register */
2741 u8 res7[0x4];
2742 u32 csta; /* CAAM Status Register */
2743 u8 res8[0x8];
2744 u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/
2745 u32 ccbvid; /* CHA Cluster Block Version ID Register */
2746 u32 chavid_ms; /* CHA Version ID Register, MS */
2747 u32 chavid_ls; /* CHA Version ID Register, LS */
2748 u32 chanum_ms; /* CHA Number Register, MS */
2749 u32 chanum_ls; /* CHA Number Register, LS */
2750 u32 secvid_ms; /* SEC Version ID Register, MS */
2751 u32 secvid_ls; /* SEC Version ID Register, LS */
2752 u8 res9[0x6020];
2753 u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */
2754 u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */
2755 u8 res10[0x8fd8];
2756 } ccsr_sec_t;
2757
2758 #define SEC_CTPR_MS_AXI_LIODN 0x08000000
2759 #define SEC_CTPR_MS_QI 0x02000000
2760 #define SEC_RVID_MA 0x0f000000
2761 #define SEC_CHANUM_MS_JRNUM_MASK 0xf0000000
2762 #define SEC_CHANUM_MS_JRNUM_SHIFT 28
2763 #define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000
2764 #define SEC_CHANUM_MS_DECONUM_SHIFT 24
2765 #define SEC_SECVID_MS_IPID_MASK 0xffff0000
2766 #define SEC_SECVID_MS_IPID_SHIFT 16
2767 #define SEC_SECVID_MS_MAJ_REV_MASK 0x0000ff00
2768 #define SEC_SECVID_MS_MAJ_REV_SHIFT 8
2769 #define SEC_CCBVID_ERA_MASK 0xff000000
2770 #define SEC_CCBVID_ERA_SHIFT 24
2771 #endif
2772
2773 typedef struct ccsr_qman {
2774 #ifdef CONFIG_SYS_FSL_QMAN_V3
2775 u8 res0[0x200];
2776 #else
2777 struct {
2778 u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */
2779 u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */
2780 u32 res;
2781 u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg */
2782 } qcsp[32];
2783 #endif
2784 /* Not actually reserved, but irrelevant to u-boot */
2785 u8 res[0xbf8 - 0x200];
2786 u32 ip_rev_1;
2787 u32 ip_rev_2;
2788 u32 fqd_bare; /* FQD Extended Base Addr Register */
2789 u32 fqd_bar; /* FQD Base Addr Register */
2790 u8 res1[0x8];
2791 u32 fqd_ar; /* FQD Attributes Register */
2792 u8 res2[0xc];
2793 u32 pfdr_bare; /* PFDR Extended Base Addr Register */
2794 u32 pfdr_bar; /* PFDR Base Addr Register */
2795 u8 res3[0x8];
2796 u32 pfdr_ar; /* PFDR Attributes Register */
2797 u8 res4[0x4c];
2798 u32 qcsp_bare; /* QCSP Extended Base Addr Register */
2799 u32 qcsp_bar; /* QCSP Base Addr Register */
2800 u8 res5[0x78];
2801 u32 ci_sched_cfg; /* Initiator Scheduling Configuration */
2802 u32 srcidr; /* Source ID Register */
2803 u32 liodnr; /* LIODN Register */
2804 u8 res6[4];
2805 u32 ci_rlm_cfg; /* Initiator Read Latency Monitor Cfg */
2806 u32 ci_rlm_avg; /* Initiator Read Latency Monitor Avg */
2807 u8 res7[0x2e8];
2808 #ifdef CONFIG_SYS_FSL_QMAN_V3
2809 struct {
2810 u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */
2811 u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */
2812 u32 res;
2813 u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg*/
2814 } qcsp[50];
2815 #endif
2816 } ccsr_qman_t;
2817
2818 typedef struct ccsr_bman {
2819 /* Not actually reserved, but irrelevant to u-boot */
2820 u8 res[0xbf8];
2821 u32 ip_rev_1;
2822 u32 ip_rev_2;
2823 u32 fbpr_bare; /* FBPR Extended Base Addr Register */
2824 u32 fbpr_bar; /* FBPR Base Addr Register */
2825 u8 res1[0x8];
2826 u32 fbpr_ar; /* FBPR Attributes Register */
2827 u8 res2[0xf0];
2828 u32 srcidr; /* Source ID Register */
2829 u32 liodnr; /* LIODN Register */
2830 u8 res7[0x2f4];
2831 } ccsr_bman_t;
2832
2833 typedef struct ccsr_pme {
2834 u8 res0[0x804];
2835 u32 liodnbr; /* LIODN Base Register */
2836 u8 res1[0x1f8];
2837 u32 srcidr; /* Source ID Register */
2838 u8 res2[8];
2839 u32 liodnr; /* LIODN Register */
2840 u8 res3[0x1e8];
2841 u32 pm_ip_rev_1; /* PME IP Block Revision Reg 1*/
2842 u32 pm_ip_rev_2; /* PME IP Block Revision Reg 1*/
2843 u8 res4[0x400];
2844 } ccsr_pme_t;
2845
2846 #ifdef CONFIG_SYS_FSL_RAID_ENGINE
2847 struct ccsr_raide {
2848 u8 res0[0x543];
2849 u32 liodnbr; /* LIODN Base Register */
2850 u8 res1[0xab8];
2851 struct {
2852 struct {
2853 u32 cfg0; /* cfg register 0 */
2854 u32 cfg1; /* cfg register 1 */
2855 u8 res1[0x3f8];
2856 } ring[2];
2857 u8 res[0x800];
2858 } jq[2];
2859 };
2860 #endif
2861
2862 #ifdef CONFIG_SYS_DPAA_RMAN
2863 struct ccsr_rman {
2864 u8 res0[0xf64];
2865 u32 mmliodnbr; /* Message Manager LIODN Base Register */
2866 u32 mmitar; /* RMAN Inbound Translation Address Register */
2867 u32 mmitdr; /* RMAN Inbound Translation Data Register */
2868 u8 res4[0x1f090];
2869 };
2870 #endif
2871
2872 #ifdef CONFIG_SYS_PMAN
2873 struct ccsr_pman {
2874 u8 res_00[0x40];
2875 u32 poes1; /* PMAN Operation Error Status Register 1 */
2876 u32 poes2; /* PMAN Operation Error Status Register 2 */
2877 u32 poeah; /* PMAN Operation Error Address High */
2878 u32 poeal; /* PMAN Operation Error Address Low */
2879 u8 res_50[0x50];
2880 u32 pr1; /* PMAN Revision Register 1 */
2881 u32 pr2; /* PMAN Revision Register 2 */
2882 u8 res_a8[0x8];
2883 u32 pcap; /* PMAN Capabilities Register */
2884 u8 res_b4[0xc];
2885 u32 pc1; /* PMAN Control Register 1 */
2886 u32 pc2; /* PMAN Control Register 2 */
2887 u32 pc3; /* PMAN Control Register 3 */
2888 u32 pc4; /* PMAN Control Register 4 */
2889 u32 pc5; /* PMAN Control Register 5 */
2890 u32 pc6; /* PMAN Control Register 6 */
2891 u8 res_d8[0x8];
2892 u32 ppa1; /* PMAN Prefetch Attributes Register 1 */
2893 u32 ppa2; /* PMAN Prefetch Attributes Register 2 */
2894 u8 res_e8[0x8];
2895 u32 pics; /* PMAN Interrupt Control and Status */
2896 u8 res_f4[0xf0c];
2897 };
2898 #endif
2899
2900 #ifdef CONFIG_FSL_CORENET
2901 #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000
2902 #ifdef CONFIG_SYS_PMAN
2903 #define CONFIG_SYS_FSL_CORENET_PMAN1_OFFSET 0x4000
2904 #define CONFIG_SYS_FSL_CORENET_PMAN2_OFFSET 0x5000
2905 #define CONFIG_SYS_FSL_CORENET_PMAN3_OFFSET 0x6000
2906 #endif
2907 #define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x8000
2908 #define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x9000
2909 #define CONFIG_SYS_MPC8xxx_DDR3_OFFSET 0xA000
2910 #define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000
2911 #define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000
2912 #define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000
2913 #define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000
2914 #define CONFIG_SYS_FSL_CPC_OFFSET 0x10000
2915 #define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000
2916 #define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000
2917 #define CONFIG_SYS_MPC85xx_DMA_OFFSET CONFIG_SYS_MPC85xx_DMA1_OFFSET
2918 #define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000
2919 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000
2920 #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000
2921 #define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x124000
2922 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000
2923 #define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000
2924 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_PPC_B4860)\
2925 && !defined(CONFIG_PPC_B4420)
2926 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x240000
2927 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x250000
2928 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x260000
2929 #define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x270000
2930 #else
2931 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000
2932 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x201000
2933 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x202000
2934 #define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x203000
2935 #endif
2936 #define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x210000
2937 #define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x211000
2938 #define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000
2939 #define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100
2940 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x220000
2941 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x221000
2942 #define CONFIG_SYS_FSL_SEC_OFFSET 0x300000
2943 #define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000
2944 #define CONFIG_SYS_FSL_QMAN_OFFSET 0x318000
2945 #define CONFIG_SYS_FSL_BMAN_OFFSET 0x31a000
2946 #define CONFIG_SYS_FSL_RAID_ENGINE_OFFSET 0x320000
2947 #define CONFIG_SYS_FSL_FM1_OFFSET 0x400000
2948 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x488000
2949 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x489000
2950 #define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0x48a000
2951 #define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0x48b000
2952 #define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0x48c000
2953 #define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0x48d000
2954 #define CONFIG_SYS_FSL_FM1_RX0_10G_OFFSET 0x490000
2955 #define CONFIG_SYS_FSL_FM1_RX1_10G_OFFSET 0x491000
2956 #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x4e0000
2957 #define CONFIG_SYS_FSL_FM2_OFFSET 0x500000
2958 #define CONFIG_SYS_FSL_FM2_RX0_1G_OFFSET 0x588000
2959 #define CONFIG_SYS_FSL_FM2_RX1_1G_OFFSET 0x589000
2960 #define CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET 0x58a000
2961 #define CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET 0x58b000
2962 #define CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET 0x58c000
2963 #define CONFIG_SYS_FSL_FM2_RX5_1G_OFFSET 0x58d000
2964 #define CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET 0x590000
2965 #define CONFIG_SYS_FSL_FM2_RX1_10G_OFFSET 0x591000
2966 #define CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET 0xC20000
2967 #else
2968 #define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000
2969 #define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x2000
2970 #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x5000
2971 #define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x6000
2972 #define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x7000
2973 #define CONFIG_SYS_MPC85xx_PCI1_OFFSET 0x8000
2974 #define CONFIG_SYS_MPC85xx_PCIX_OFFSET 0x8000
2975 #define CONFIG_SYS_MPC85xx_PCI2_OFFSET 0x9000
2976 #define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000
2977 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0xa000
2978 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x9000
2979 #if defined(CONFIG_MPC8572) || defined(CONFIG_P2020)
2980 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x8000
2981 #else
2982 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0xb000
2983 #endif
2984 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0xF000
2985 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x18000
2986 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x19000
2987 #define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x1e000
2988 #define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000
2989 #define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000
2990 #define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x22000
2991 #define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x23000
2992 #ifdef CONFIG_TSECV2
2993 #define CONFIG_SYS_TSEC1_OFFSET 0xB0000
2994 #elif defined(CONFIG_TSECV2_1)
2995 #define CONFIG_SYS_TSEC1_OFFSET 0x10000
2996 #else
2997 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
2998 #endif
2999 #define CONFIG_SYS_MDIO1_OFFSET 0x24000
3000 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000
3001 #if defined(CONFIG_PPC_C29X)
3002 #define CONFIG_SYS_FSL_SEC_OFFSET 0x80000
3003 #else
3004 #define CONFIG_SYS_FSL_SEC_OFFSET 0x30000
3005 #endif
3006 #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100
3007 #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000
3008 #define CONFIG_SYS_SNVS_OFFSET 0xE6000
3009 #define CONFIG_SYS_SFP_OFFSET 0xE7000
3010 #define CONFIG_SYS_MPC85xx_CPM_OFFSET 0x80000
3011 #define CONFIG_SYS_FSL_QMAN_OFFSET 0x88000
3012 #define CONFIG_SYS_FSL_BMAN_OFFSET 0x8a000
3013 #define CONFIG_SYS_FSL_FM1_OFFSET 0x100000
3014 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x188000
3015 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x189000
3016 #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x1e0000
3017 #endif
3018
3019 #define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000
3020 #define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000
3021 #define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000
3022
3023 #if defined(CONFIG_BSC9132)
3024 #define CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET 0x10000
3025 #define CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR \
3026 (CONFIG_SYS_FSL_DSP_CCSRBAR + CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET)
3027 #endif
3028
3029 #define CONFIG_SYS_FSL_CPC_ADDR \
3030 (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET)
3031 #define CONFIG_SYS_FSL_QMAN_ADDR \
3032 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET)
3033 #define CONFIG_SYS_FSL_BMAN_ADDR \
3034 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_BMAN_OFFSET)
3035 #define CONFIG_SYS_FSL_CORENET_PME_ADDR \
3036 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET)
3037 #define CONFIG_SYS_FSL_RAID_ENGINE_ADDR \
3038 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_RAID_ENGINE_OFFSET)
3039 #define CONFIG_SYS_FSL_CORENET_RMAN_ADDR \
3040 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RMAN_OFFSET)
3041 #define CONFIG_SYS_MPC85xx_GUTS_ADDR \
3042 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET)
3043 #define CONFIG_SYS_FSL_CORENET_CCM_ADDR \
3044 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET)
3045 #define CONFIG_SYS_FSL_CORENET_CLK_ADDR \
3046 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET)
3047 #define CONFIG_SYS_FSL_CORENET_RCPM_ADDR \
3048 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET)
3049 #define CONFIG_SYS_MPC85xx_ECM_ADDR \
3050 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET)
3051 #define CONFIG_SYS_FSL_DDR_ADDR \
3052 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
3053 #define CONFIG_SYS_FSL_DDR2_ADDR \
3054 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
3055 #define CONFIG_SYS_FSL_DDR3_ADDR \
3056 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR3_OFFSET)
3057 #define CONFIG_SYS_LBC_ADDR \
3058 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
3059 #define CONFIG_SYS_IFC_ADDR \
3060 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_IFC_OFFSET)
3061 #define CONFIG_SYS_MPC85xx_ESPI_ADDR \
3062 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET)
3063 #define CONFIG_SYS_MPC85xx_PCIX_ADDR \
3064 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET)
3065 #define CONFIG_SYS_MPC85xx_PCIX2_ADDR \
3066 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET)
3067 #define CONFIG_SYS_MPC85xx_GPIO_ADDR \
3068 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET)
3069 #define CONFIG_SYS_MPC85xx_SATA1_ADDR \
3070 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET)
3071 #define CONFIG_SYS_MPC85xx_SATA2_ADDR \
3072 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET)
3073 #define CONFIG_SYS_MPC85xx_L2_ADDR \
3074 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET)
3075 #define CONFIG_SYS_MPC85xx_DMA_ADDR \
3076 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET)
3077 #define CONFIG_SYS_MPC85xx_ESDHC_ADDR \
3078 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
3079 #define CONFIG_SYS_MPC8xxx_PIC_ADDR \
3080 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET)
3081 #define CONFIG_SYS_MPC85xx_CPM_ADDR \
3082 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET)
3083 #define CONFIG_SYS_MPC85xx_SERDES1_ADDR \
3084 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET)
3085 #define CONFIG_SYS_MPC85xx_SERDES2_ADDR \
3086 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
3087 #define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \
3088 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
3089 #define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \
3090 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET)
3091 #define CONFIG_SYS_MPC85xx_USB1_ADDR \
3092 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_OFFSET)
3093 #define CONFIG_SYS_MPC85xx_USB2_ADDR \
3094 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_OFFSET)
3095 #define CONFIG_SYS_MPC85xx_USB1_PHY_ADDR \
3096 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET)
3097 #define CONFIG_SYS_MPC85xx_USB2_PHY_ADDR \
3098 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET)
3099 #define CONFIG_SYS_FSL_SEC_ADDR \
3100 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
3101 #define CONFIG_SYS_FSL_FM1_ADDR \
3102 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
3103 #define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \
3104 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
3105 #define CONFIG_SYS_FSL_FM2_ADDR \
3106 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET)
3107 #define CONFIG_SYS_FSL_SRIO_ADDR \
3108 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SRIO_OFFSET)
3109
3110 #define CONFIG_SYS_PCI1_ADDR \
3111 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET)
3112 #define CONFIG_SYS_PCI2_ADDR \
3113 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI2_OFFSET)
3114 #define CONFIG_SYS_PCIE1_ADDR \
3115 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE1_OFFSET)
3116 #define CONFIG_SYS_PCIE2_ADDR \
3117 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE2_OFFSET)
3118 #define CONFIG_SYS_PCIE3_ADDR \
3119 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE3_OFFSET)
3120 #define CONFIG_SYS_PCIE4_ADDR \
3121 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE4_OFFSET)
3122
3123 #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
3124 #define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
3125
3126 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
3127 struct ccsr_cluster_l2 {
3128 u32 l2csr0; /* 0x000 L2 cache control and status register 0 */
3129 u32 l2csr1; /* 0x004 L2 cache control and status register 1 */
3130 u32 l2cfg0; /* 0x008 L2 cache configuration register 0 */
3131 u8 res_0c[500];/* 0x00c - 0x1ff */
3132 u32 l2pir0; /* 0x200 L2 cache partitioning ID register 0 */
3133 u8 res_204[4];
3134 u32 l2par0; /* 0x208 L2 cache partitioning allocation register 0 */
3135 u32 l2pwr0; /* 0x20c L2 cache partitioning way register 0 */
3136 u32 l2pir1; /* 0x210 L2 cache partitioning ID register 1 */
3137 u8 res_214[4];
3138 u32 l2par1; /* 0x218 L2 cache partitioning allocation register 1 */
3139 u32 l2pwr1; /* 0x21c L2 cache partitioning way register 1 */
3140 u32 u2pir2; /* 0x220 L2 cache partitioning ID register 2 */
3141 u8 res_224[4];
3142 u32 l2par2; /* 0x228 L2 cache partitioning allocation register 2 */
3143 u32 l2pwr2; /* 0x22c L2 cache partitioning way register 2 */
3144 u32 l2pir3; /* 0x230 L2 cache partitioning ID register 3 */
3145 u8 res_234[4];
3146 u32 l2par3; /* 0x238 L2 cache partitining allocation register 3 */
3147 u32 l2pwr3; /* 0x23c L2 cache partitining way register 3 */
3148 u32 l2pir4; /* 0x240 L2 cache partitioning ID register 3 */
3149 u8 res244[4];
3150 u32 l2par4; /* 0x248 L2 cache partitioning allocation register 3 */
3151 u32 l2pwr4; /* 0x24c L2 cache partitioning way register 3 */
3152 u32 l2pir5; /* 0x250 L2 cache partitioning ID register 3 */
3153 u8 res_254[4];
3154 u32 l2par5; /* 0x258 L2 cache partitioning allocation register 3 */
3155 u32 l2pwr5; /* 0x25c L2 cache partitioning way register 3 */
3156 u32 l2pir6; /* 0x260 L2 cache partitioning ID register 3 */
3157 u8 res_264[4];
3158 u32 l2par6; /* 0x268 L2 cache partitioning allocation register 3 */
3159 u32 l2pwr6; /* 0x26c L2 cache partitioning way register 3 */
3160 u32 l2pir7; /* 0x270 L2 cache partitioning ID register 3 */
3161 u8 res274[4];
3162 u32 l2par7; /* 0x278 L2 cache partitioning allocation register 3 */
3163 u32 l2pwr7; /* 0x27c L2 cache partitioning way register 3 */
3164 u8 res_280[0xb80]; /* 0x280 - 0xdff */
3165 u32 l2errinjhi; /* 0xe00 L2 cache error injection mask high */
3166 u32 l2errinjlo; /* 0xe04 L2 cache error injection mask low */
3167 u32 l2errinjctl;/* 0xe08 L2 cache error injection control */
3168 u8 res_e0c[20]; /* 0xe0c - 0x01f */
3169 u32 l2captdatahi; /* 0xe20 L2 cache error capture data high */
3170 u32 l2captdatalo; /* 0xe24 L2 cache error capture data low */
3171 u32 l2captecc; /* 0xe28 L2 cache error capture ECC syndrome */
3172 u8 res_e2c[20]; /* 0xe2c - 0xe3f */
3173 u32 l2errdet; /* 0xe40 L2 cache error detect */
3174 u32 l2errdis; /* 0xe44 L2 cache error disable */
3175 u32 l2errinten; /* 0xe48 L2 cache error interrupt enable */
3176 u32 l2errattr; /* 0xe4c L2 cache error attribute */
3177 u32 l2erreaddr; /* 0xe50 L2 cache error extended address */
3178 u32 l2erraddr; /* 0xe54 L2 cache error address */
3179 u32 l2errctl; /* 0xe58 L2 cache error control */
3180 };
3181 #define CONFIG_SYS_FSL_CLUSTER_1_L2 \
3182 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET)
3183 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
3184
3185 #define CONFIG_SYS_DCSR_DCFG_OFFSET 0X20000
3186 struct dcsr_dcfg_regs {
3187 u8 res_0[0x520];
3188 u32 ecccr1;
3189 #define DCSR_DCFG_ECC_DISABLE_USB1 0x00008000
3190 #define DCSR_DCFG_ECC_DISABLE_USB2 0x00004000
3191 u8 res_524[0x1000 - 0x524]; /* 0x524 - 0x1000 */
3192 };
3193 #endif /*__IMMAP_85xx__*/
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