board/amcc/acadia/memory.c

   1 /*
   2  * (C) Copyright 2007
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /* define DEBUG for debugging output (obviously ;-)) */
   9 #if 0
  10 #define DEBUG
  11 #endif
  12
  13 #include <common.h>
  14 #include <asm/processor.h>
  15 #include <asm/io.h>
  16 #include <asm/ppc4xx-gpio.h>
  17
  18 extern void board_pll_init_f(void);
  19
  20 static void cram_bcr_write(u32 wr_val)
  21 {
  22         wr_val <<= 2;
  23
  24         /* set CRAM_CRE to 1 */
  25         gpio_write_bit(CONFIG_SYS_GPIO_CRAM_CRE, 1);
  26
  27         /* Write BCR to CRAM on CS1 */
  28         out32(wr_val + 0x00200000, 0);
  29         debug("CRAM VAL: %08x for CS1 ", wr_val + 0x00200000);
  30
  31         /* Write BCR to CRAM on CS2 */
  32         out32(wr_val + 0x02200000, 0);
  33         debug("CRAM VAL: %08x for CS2\n", wr_val + 0x02200000);
  34
  35         sync();
  36         eieio();
  37
  38         /* set CRAM_CRE back to 0 (normal operation) */
  39         gpio_write_bit(CONFIG_SYS_GPIO_CRAM_CRE, 0);
  40
  41         return;
  42 }
  43
  44 phys_size_t initdram(void)
  45 {
  46         int i;
  47         u32 val;
  48
  49         /* 1. EBC need to program READY, CLK, ADV for ASync mode */
  50         gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
  51         gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
  52         gpio_config(CONFIG_SYS_GPIO_CRAM_CRE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
  53         gpio_config(CONFIG_SYS_GPIO_CRAM_WAIT, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG);
  54
  55         /* 2. EBC in Async mode */
  56         mtebc(PB1AP, 0x078F1EC0);
  57         mtebc(PB2AP, 0x078F1EC0);
  58         mtebc(PB1CR, 0x000BC000);
  59         mtebc(PB2CR, 0x020BC000);
  60
  61         /* 3. Set CRAM in Sync mode */
  62         cram_bcr_write(0x7012);         /* CRAM burst setting */
  63
  64         /* 4. EBC in Sync mode */
  65         mtebc(PB1AP, 0x9C0201C0);
  66         mtebc(PB2AP, 0x9C0201C0);
  67
  68         /* Set GPIO pins back to alternate function */
  69         gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
  70         gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
  71
  72         /* Config EBC to use RDY */
  73         mfsdr(SDR0_ULTRA0, val);
  74         mtsdr(SDR0_ULTRA0, val | SDR_ULTRA0_EBCRDYEN);
  75
  76         /* Wait a short while, since for NAND booting this is too fast */
  77         for (i=0; i<200000; i++)
  78                 ;
  79
  80         return (CONFIG_SYS_MBYTES_RAM << 20);
  81 }