board/amcc/canyonlands/canyonlands.c

   1 /*
   2  * (C) Copyright 2008
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18  * MA 02111-1307 USA
  19  */
  20
  21 #include <common.h>
  22 #include <ppc440.h>
  23 #include <libfdt.h>
  24 #include <fdt_support.h>
  25 #include <i2c.h>
  26 #include <asm/processor.h>
  27 #include <asm/io.h>
  28 #include <asm/mmu.h>
  29 #include <asm/4xx_pcie.h>
  30 #include <asm/gpio.h>
  31
  32 extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
  33
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 #define CONFIG_SYS_BCSR3_PCIE           0x10
  37
  38 #define BOARD_CANYONLANDS_PCIE  1
  39 #define BOARD_CANYONLANDS_SATA  2
  40 #define BOARD_GLACIER           3
  41 #define BOARD_ARCHES            4
  42
  43 /*
  44  * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
  45  * board specific values.
  46  */
  47 #if defined(CONFIG_ARCHES)
  48 u32 ddr_wrdtr(u32 default_val) {
  49         return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_0_DEG | 0x823);
  50 }
  51 #else
  52 u32 ddr_wrdtr(u32 default_val) {
  53         return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);
  54 }
  55
  56 u32 ddr_clktr(u32 default_val) {
  57         return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
  58 }
  59 #endif
  60
  61 #if defined(CONFIG_ARCHES)
  62 /*
  63  * FPGA read/write helper macros
  64  */
  65 static inline int board_fpga_read(int offset)
  66 {
  67         int data;
  68
  69         data = in_8((void *)(CONFIG_SYS_FPGA_BASE + offset));
  70
  71         return data;
  72 }
  73
  74 static inline void board_fpga_write(int offset, int data)
  75 {
  76         out_8((void *)(CONFIG_SYS_FPGA_BASE + offset), data);
  77 }
  78
  79 /*
  80  * CPLD read/write helper macros
  81  */
  82 static inline int board_cpld_read(int offset)
  83 {
  84         int data;
  85
  86         out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
  87         data = in_8((void *)(CONFIG_SYS_CPLD_DATA));
  88
  89         return data;
  90 }
  91
  92 static inline void board_cpld_write(int offset, int data)
  93 {
  94         out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
  95         out_8((void *)(CONFIG_SYS_CPLD_DATA), data);
  96 }
  97 #endif  /* defined(CONFIG_ARCHES) */
  98
  99 int board_early_init_f(void)
 100 {
 101 #if !defined(CONFIG_ARCHES)
 102         u32 sdr0_cust0;
 103         u32 pvr = get_pvr();
 104 #endif
 105
 106         /*
 107          * Setup the interrupt controller polarities, triggers, etc.
 108          */
 109         mtdcr(uic0sr, 0xffffffff);      /* clear all */
 110         mtdcr(uic0er, 0x00000000);      /* disable all */
 111         mtdcr(uic0cr, 0x00000005);      /* ATI & UIC1 crit are critical */
 112         mtdcr(uic0pr, 0xffffffff);      /* per ref-board manual */
 113         mtdcr(uic0tr, 0x00000000);      /* per ref-board manual */
 114         mtdcr(uic0vr, 0x00000000);      /* int31 highest, base=0x000 */
 115         mtdcr(uic0sr, 0xffffffff);      /* clear all */
 116
 117         mtdcr(uic1sr, 0xffffffff);      /* clear all */
 118         mtdcr(uic1er, 0x00000000);      /* disable all */
 119         mtdcr(uic1cr, 0x00000000);      /* all non-critical */
 120         mtdcr(uic1pr, 0xffffffff);      /* per ref-board manual */
 121         mtdcr(uic1tr, 0x00000000);      /* per ref-board manual */
 122         mtdcr(uic1vr, 0x00000000);      /* int31 highest, base=0x000 */
 123         mtdcr(uic1sr, 0xffffffff);      /* clear all */
 124
 125         mtdcr(uic2sr, 0xffffffff);      /* clear all */
 126         mtdcr(uic2er, 0x00000000);      /* disable all */
 127         mtdcr(uic2cr, 0x00000000);      /* all non-critical */
 128         mtdcr(uic2pr, 0xffffffff);      /* per ref-board manual */
 129         mtdcr(uic2tr, 0x00000000);      /* per ref-board manual */
 130         mtdcr(uic2vr, 0x00000000);      /* int31 highest, base=0x000 */
 131         mtdcr(uic2sr, 0xffffffff);      /* clear all */
 132
 133         mtdcr(uic3sr, 0xffffffff);      /* clear all */
 134         mtdcr(uic3er, 0x00000000);      /* disable all */
 135         mtdcr(uic3cr, 0x00000000);      /* all non-critical */
 136         mtdcr(uic3pr, 0xffffffff);      /* per ref-board manual */
 137         mtdcr(uic3tr, 0x00000000);      /* per ref-board manual */
 138         mtdcr(uic3vr, 0x00000000);      /* int31 highest, base=0x000 */
 139         mtdcr(uic3sr, 0xffffffff);      /* clear all */
 140
 141 #if !defined(CONFIG_ARCHES)
 142         /* SDR Setting - enable NDFC */
 143         mfsdr(SDR0_CUST0, sdr0_cust0);
 144         sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL    |
 145                 SDR0_CUST0_NDFC_ENABLE          |
 146                 SDR0_CUST0_NDFC_BW_8_BIT        |
 147                 SDR0_CUST0_NDFC_ARE_MASK        |
 148                 SDR0_CUST0_NDFC_BAC_ENCODE(3)   |
 149                 (0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
 150         mtsdr(SDR0_CUST0, sdr0_cust0);
 151 #endif
 152
 153         /*
 154          * Configure PFC (Pin Function Control) registers
 155          * UART0: 4 pins
 156          */
 157         mtsdr(SDR0_PFC1, 0x00040000);
 158
 159         /* Enable PCI host functionality in SDR0_PCI0 */
 160         mtsdr(SDR0_PCI0, 0xe0000000);
 161
 162 #if !defined(CONFIG_ARCHES)
 163         /* Enable ethernet and take out of reset */
 164         out_8((void *)CONFIG_SYS_BCSR_BASE + 6, 0);
 165
 166         /* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */
 167         out_8((void *)CONFIG_SYS_BCSR_BASE + 5, 0);
 168
 169         /* Enable USB host & USB-OTG */
 170         out_8((void *)CONFIG_SYS_BCSR_BASE + 7, 0);
 171
 172         mtsdr(SDR0_SRST1, 0);   /* Pull AHB out of reset default=1 */
 173
 174         /* Setup PLB4-AHB bridge based on the system address map */
 175         mtdcr(AHB_TOP, 0x8000004B);
 176         mtdcr(AHB_BOT, 0x8000004B);
 177
 178         if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA)) {
 179                 /*
 180                  * Configure USB-STP pins as alternate and not GPIO
 181                  * It seems to be neccessary to configure the STP pins as GPIO
 182                  * input at powerup (perhaps while USB reset is asserted). So
 183                  * we configure those pins to their "real" function now.
 184                  */
 185                 gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
 186                 gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
 187         }
 188 #endif
 189
 190         return 0;
 191 }
 192
 193 #if !defined(CONFIG_ARCHES)
 194 static void canyonlands_sata_init(int board_type)
 195 {
 196         u32 reg;
 197
 198         if (board_type == BOARD_CANYONLANDS_SATA) {
 199                 /* Put SATA in reset */
 200                 SDR_WRITE(SDR0_SRST1, 0x00020001);
 201
 202                 /* Set the phy for SATA, not PCI-E port 0 */
 203                 reg = SDR_READ(PESDR0_PHY_CTL_RST);
 204                 SDR_WRITE(PESDR0_PHY_CTL_RST, (reg & 0xeffffffc) | 0x00000001);
 205                 reg = SDR_READ(PESDR0_L0CLK);
 206                 SDR_WRITE(PESDR0_L0CLK, (reg & 0xfffffff8) | 0x00000007);
 207                 SDR_WRITE(PESDR0_L0CDRCTL, 0x00003111);
 208                 SDR_WRITE(PESDR0_L0DRV, 0x00000104);
 209
 210                 /* Bring SATA out of reset */
 211                 SDR_WRITE(SDR0_SRST1, 0x00000000);
 212         }
 213 }
 214 #endif  /* !defined(CONFIG_ARCHES) */
 215
 216 int get_cpu_num(void)
 217 {
 218         int cpu = NA_OR_UNKNOWN_CPU;
 219
 220 #if defined(CONFIG_ARCHES)
 221         int cpu_num;
 222
 223         cpu_num = board_fpga_read(0x3);
 224
 225         /* sanity check; assume cpu numbering starts and increments from 0 */
 226         if ((cpu_num >= 0) && (cpu_num < CONFIG_BD_NUM_CPUS))
 227                 cpu = cpu_num;
 228 #endif
 229
 230         return cpu;
 231 }
 232
 233 #if !defined(CONFIG_ARCHES)
 234 int checkboard(void)
 235 {
 236         char *s = getenv("serial#");
 237         u32 pvr = get_pvr();
 238
 239         if ((pvr == PVR_460GT_RA) || (pvr == PVR_460GT_SE_RA)) {
 240                 printf("Board: Glacier - AMCC PPC460GT Evaluation Board");
 241                 gd->board_type = BOARD_GLACIER;
 242         } else {
 243                 printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
 244                 if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 3)) & CONFIG_SYS_BCSR3_PCIE)
 245                         gd->board_type = BOARD_CANYONLANDS_PCIE;
 246                 else
 247                         gd->board_type = BOARD_CANYONLANDS_SATA;
 248         }
 249
 250         switch (gd->board_type) {
 251         case BOARD_CANYONLANDS_PCIE:
 252         case BOARD_GLACIER:
 253                 puts(", 2*PCIe");
 254                 break;
 255
 256         case BOARD_CANYONLANDS_SATA:
 257                 puts(", 1*PCIe/1*SATA");
 258                 break;
 259         }
 260
 261         printf(", Rev. %X", in_8((void *)(CONFIG_SYS_BCSR_BASE + 0)));
 262
 263         if (s != NULL) {
 264                 puts(", serial# ");
 265                 puts(s);
 266         }
 267         putc('\n');
 268
 269         canyonlands_sata_init(gd->board_type);
 270
 271         return (0);
 272 }
 273
 274 #else   /* defined(CONFIG_ARCHES) */
 275
 276 int checkboard(void)
 277 {
 278         char *s = getenv("serial#");
 279
 280         printf("Board: Arches - AMCC DUAL PPC460GT Reference Design\n");
 281         printf("       Revision %02x.%02x ",
 282                                 board_fpga_read(0x0), board_fpga_read(0x1));
 283
 284         gd->board_type = BOARD_ARCHES;
 285
 286         /* Only CPU0 has access to CPLD registers */
 287         if (get_cpu_num() == 0) {
 288                 u8 cfg_sw = board_cpld_read(0x1);
 289                 printf("(FPGA=%02x, CPLD=%02x)\n",
 290                                 board_fpga_read(0x2), board_cpld_read(0x0));
 291                 printf("       Configuration Switch %d%d%d%d\n",
 292                                 ((cfg_sw >> 3) & 0x01),
 293                                 ((cfg_sw >> 2) & 0x01),
 294                                 ((cfg_sw >> 1) & 0x01),
 295                                 ((cfg_sw >> 0) & 0x01));
 296         } else
 297                 printf("(FPGA=%02x, CPLD=xx)\n", board_fpga_read(0x2));
 298
 299
 300         if (s != NULL)
 301                 printf("       Serial# %s\n", s);
 302
 303         return 0;
 304 }
 305 #endif  /* !defined(CONFIG_ARCHES) */
 306
 307 #if defined(CONFIG_NAND_U_BOOT)
 308 /*
 309  * NAND booting U-Boot version uses a fixed initialization, since the whole
 310  * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot
 311  * code.
 312  */
 313 phys_size_t initdram(int board_type)
 314 {
 315         return CONFIG_SYS_MBYTES_SDRAM << 20;
 316 }
 317 #endif
 318
 319 /*
 320  *  pci_target_init
 321  *
 322  *      The bootstrap configuration provides default settings for the pci
 323  *      inbound map (PIM). But the bootstrap config choices are limited and
 324  *      may not be sufficient for a given board.
 325  */
 326 #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
 327 void pci_target_init(struct pci_controller * hose )
 328 {
 329         /*
 330          * Disable everything
 331          */
 332         out_le32((void *)PCIX0_PIM0SA, 0); /* disable */
 333         out_le32((void *)PCIX0_PIM1SA, 0); /* disable */
 334         out_le32((void *)PCIX0_PIM2SA, 0); /* disable */
 335         out_le32((void *)PCIX0_EROMBA, 0); /* disable expansion rom */
 336
 337         /*
 338          * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
 339          * strapping options to not support sizes such as 128/256 MB.
 340          */
 341         out_le32((void *)PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
 342         out_le32((void *)PCIX0_PIM0LAH, 0);
 343         out_le32((void *)PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
 344         out_le32((void *)PCIX0_BAR0, 0);
 345
 346         /*
 347          * Program the board's subsystem id/vendor id
 348          */
 349         out_le16((void *)PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
 350         out_le16((void *)PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
 351
 352         out_le16((void *)PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
 353 }
 354 #endif  /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 355
 356 #if defined(CONFIG_PCI)
 357 /*
 358  * is_pci_host
 359  *
 360  * This routine is called to determine if a pci scan should be
 361  * performed. With various hardware environments (especially cPCI and
 362  * PPMC) it's insufficient to depend on the state of the arbiter enable
 363  * bit in the strap register, or generic host/adapter assumptions.
 364  *
 365  * Rather than hard-code a bad assumption in the general 440 code, the
 366  * 440 pci code requires the board to decide at runtime.
 367  *
 368  * Return 0 for adapter mode, non-zero for host (monarch) mode.
 369  */
 370 int is_pci_host(struct pci_controller *hose)
 371 {
 372         /* Board is always configured as host. */
 373         return (1);
 374 }
 375
 376 static struct pci_controller pcie_hose[2] = {{0},{0}};
 377
 378 void pcie_setup_hoses(int busno)
 379 {
 380         struct pci_controller *hose;
 381         int i, bus;
 382         int ret = 0;
 383         char *env;
 384         unsigned int delay;
 385         int start;
 386
 387         /*
 388          * assume we're called after the PCIX hose is initialized, which takes
 389          * bus ID 0 and therefore start numbering PCIe's from 1.
 390          */
 391         bus = busno;
 392
 393         /*
 394          * Canyonlands with SATA enabled has only one PCIe slot
 395          * (2nd one).
 396          */
 397         if (gd->board_type == BOARD_CANYONLANDS_SATA)
 398                 start = 1;
 399         else
 400                 start = 0;
 401
 402         for (i = start; i <= 1; i++) {
 403
 404                 if (is_end_point(i))
 405                         ret = ppc4xx_init_pcie_endport(i);
 406                 else
 407                         ret = ppc4xx_init_pcie_rootport(i);
 408                 if (ret) {
 409                         printf("PCIE%d: initialization as %s failed\n", i,
 410                                is_end_point(i) ? "endpoint" : "root-complex");
 411                         continue;
 412                 }
 413
 414                 hose = &pcie_hose[i];
 415                 hose->first_busno = bus;
 416                 hose->last_busno = bus;
 417                 hose->current_busno = bus;
 418
 419                 /* setup mem resource */
 420                 pci_set_region(hose->regions + 0,
 421                                CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
 422                                CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
 423                                CONFIG_SYS_PCIE_MEMSIZE,
 424                                PCI_REGION_MEM);
 425                 hose->region_count = 1;
 426                 pci_register_hose(hose);
 427
 428                 if (is_end_point(i)) {
 429                         ppc4xx_setup_pcie_endpoint(hose, i);
 430                         /*
 431                          * Reson for no scanning is endpoint can not generate
 432                          * upstream configuration accesses.
 433                          */
 434                 } else {
 435                         ppc4xx_setup_pcie_rootpoint(hose, i);
 436                         env = getenv ("pciscandelay");
 437                         if (env != NULL) {
 438                                 delay = simple_strtoul(env, NULL, 10);
 439                                 if (delay > 5)
 440                                         printf("Warning, expect noticable delay before "
 441                                                "PCIe scan due to 'pciscandelay' value!\n");
 442                                 mdelay(delay * 1000);
 443                         }
 444
 445                         /*
 446                          * Config access can only go down stream
 447                          */
 448                         hose->last_busno = pci_hose_scan(hose);
 449                         bus = hose->last_busno + 1;
 450                 }
 451         }
 452 }
 453 #endif /* CONFIG_PCI */
 454
 455 int board_early_init_r (void)
 456 {
 457         /*
 458          * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
 459          * boot EBC mapping only supports a maximum of 16MBytes
 460          * (4.ff00.0000 - 4.ffff.ffff).
 461          * To solve this problem, the FLASH has to get remapped to another
 462          * EBC address which accepts bigger regions:
 463          *
 464          * 0xfc00.0000 -> 4.cc00.0000
 465          */
 466
 467         /* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
 468 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
 469         mtebc(pb3cr, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
 470 #else
 471         mtebc(pb0cr, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
 472 #endif
 473
 474         /* Remove TLB entry of boot EBC mapping */
 475         remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
 476
 477         /* Add TLB entry for 0xfc00.0000 -> 0x4.cc00.0000 */
 478         program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE,
 479                     TLB_WORD2_I_ENABLE);
 480
 481         /*
 482          * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
 483          * 0xfc00.0000 is possible
 484          */
 485
 486         /*
 487          * Clear potential errors resulting from auto-calibration.
 488          * If not done, then we could get an interrupt later on when
 489          * exceptions are enabled.
 490          */
 491         set_mcsr(get_mcsr());
 492
 493         return 0;
 494 }
 495
 496 #if !defined(CONFIG_ARCHES)
 497 int misc_init_r(void)
 498 {
 499         u32 sdr0_srst1 = 0;
 500         u32 eth_cfg;
 501         u32 pvr = get_pvr();
 502         u8 val;
 503
 504         /*
 505          * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
 506          * This is board specific, so let's do it here.
 507          */
 508         mfsdr(SDR0_ETH_CFG, eth_cfg);
 509         /* disable SGMII mode */
 510         eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE |
 511                      SDR0_ETH_CFG_SGMII1_ENABLE |
 512                      SDR0_ETH_CFG_SGMII0_ENABLE);
 513         /* Set the for 2 RGMII mode */
 514         /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
 515         eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
 516         if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA))
 517                 eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
 518         else
 519                 eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
 520         mtsdr(SDR0_ETH_CFG, eth_cfg);
 521
 522         /*
 523          * The AHB Bridge core is held in reset after power-on or reset
 524          * so enable it now
 525          */
 526         mfsdr(SDR0_SRST1, sdr0_srst1);
 527         sdr0_srst1 &= ~SDR0_SRST1_AHB;
 528         mtsdr(SDR0_SRST1, sdr0_srst1);
 529
 530         /*
 531          * RTC/M41T62:
 532          * Disable square wave output: Batterie will be drained
 533          * quickly, when this output is not disabled
 534          */
 535         val = i2c_reg_read(CONFIG_SYS_I2C_RTC_ADDR, 0xa);
 536         val &= ~0x40;
 537         i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR, 0xa, val);
 538
 539         return 0;
 540 }
 541
 542 #else   /* defined(CONFIG_ARCHES) */
 543
 544 int misc_init_r(void)
 545 {
 546         u32 eth_cfg = 0;
 547         u32 eth_pll;
 548         u32 reg;
 549
 550         /*
 551          * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
 552          * This is board specific, so let's do it here.
 553          */
 554
 555         /* enable SGMII mode */
 556         eth_cfg |= (SDR0_ETH_CFG_SGMII0_ENABLE |
 557                         SDR0_ETH_CFG_SGMII1_ENABLE |
 558                         SDR0_ETH_CFG_SGMII2_ENABLE);
 559
 560         /* Set EMAC for MDIO */
 561         eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0;
 562
 563         /* bypass the TAHOE0/TAHOE1 cores for U-Boot */
 564         eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
 565
 566         mtsdr(SDR0_ETH_CFG, eth_cfg);
 567
 568         /* reset all SGMII interfaces */
 569         mfsdr(SDR0_SRST1,   reg);
 570         reg |= (SDR0_SRST1_SGMII0 | SDR0_SRST1_SGMII1 | SDR0_SRST1_SGMII2);
 571         mtsdr(SDR0_SRST1, reg);
 572         mtsdr(SDR0_ETH_STS, 0xFFFFFFFF);
 573         mtsdr(SDR0_SRST1,   0x00000000);
 574
 575         do {
 576                 mfsdr(SDR0_ETH_PLL, eth_pll);
 577         } while (!(eth_pll & SDR0_ETH_PLL_PLLLOCK));
 578
 579         return 0;
 580 }
 581 #endif  /* !defined(CONFIG_ARCHES) */
 582
 583 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 584 extern void __ft_board_setup(void *blob, bd_t *bd);
 585
 586 void ft_board_setup(void *blob, bd_t *bd)
 587 {
 588         u32 val[4];
 589         int rc;
 590
 591         __ft_board_setup(blob, bd);
 592
 593         /* Fixup NOR mapping */
 594         val[0] = CONFIG_SYS_NOR_CS;             /* chip select number */
 595         val[1] = 0;                             /* always 0 */
 596         val[2] = CONFIG_SYS_FLASH_BASE_PHYS_L;          /* we fixed up this address */
 597         val[3] = gd->bd->bi_flashsize;
 598         rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
 599                                   val, sizeof(val), 1);
 600         if (rc) {
 601                 printf("Unable to update property NOR mapping, err=%s\n",
 602                        fdt_strerror(rc));
 603         }
 604
 605         if (gd->board_type == BOARD_CANYONLANDS_SATA) {
 606                 /*
 607                  * When SATA is selected we need to disable the first PCIe
 608                  * node in the device tree, so that Linux doesn't initialize
 609                  * it.
 610                  */
 611                 fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status",
 612                                      "disabled", sizeof("disabled"), 1);
 613         }
 614
 615         if (gd->board_type == BOARD_CANYONLANDS_PCIE) {
 616                 /*
 617                  * When PCIe is selected we need to disable the SATA
 618                  * node in the device tree, so that Linux doesn't initialize
 619                  * it.
 620                  */
 621                 fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status",
 622                                      "disabled", sizeof("disabled"), 1);
 623         }
 624 }
 625 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */