board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c

   1 /*
   2  * Copyright 2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <command.h>
   9 #include <hwconfig.h>
  10 #include <pci.h>
  11 #include <i2c.h>
  12 #include <asm/processor.h>
  13 #include <asm/mmu.h>
  14 #include <asm/cache.h>
  15 #include <asm/immap_85xx.h>
  16 #include <asm/fsl_pci.h>
  17 #include <fsl_ddr_sdram.h>
  18 #include <asm/io.h>
  19 #include <asm/fsl_law.h>
  20 #include <asm/fsl_lbc.h>
  21 #include <asm/mp.h>
  22 #include <miiphy.h>
  23 #include <libfdt.h>
  24 #include <fdt_support.h>
  25 #include <fsl_mdio.h>
  26 #include <tsec.h>
  27 #include <vsc7385.h>
  28 #include <ioports.h>
  29 #include <asm/fsl_serdes.h>
  30 #include <netdev.h>
  31
  32 #ifdef CONFIG_QE
  33
  34 #define GPIO_GETH_SW_PORT       1
  35 #define GPIO_GETH_SW_PIN        29
  36 #define GPIO_GETH_SW_DATA       (1 << (31 - GPIO_GETH_SW_PIN))
  37
  38 #define GPIO_SLIC_PORT          1
  39 #define GPIO_SLIC_PIN           30
  40 #define GPIO_SLIC_DATA          (1 << (31 - GPIO_SLIC_PIN))
  41
  42 #if defined(CONFIG_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
  43 #define GPIO_DDR_RST_PORT       1
  44 #define GPIO_DDR_RST_PIN        8
  45 #define GPIO_DDR_RST_DATA       (1 << (31 - GPIO_DDR_RST_PIN))
  46
  47 #define GPIO_2BIT_MASK          (0x3 << (32 - (GPIO_DDR_RST_PIN + 1) * 2))
  48 #endif
  49
  50 #if defined(CONFIG_P1025RDB) || defined(CONFIG_P1021RDB)
  51 #define PCA_IOPORT_I2C_ADDR             0x23
  52 #define PCA_IOPORT_OUTPUT_CMD           0x2
  53 #define PCA_IOPORT_CFG_CMD              0x6
  54 #define PCA_IOPORT_QE_PIN_ENABLE        0xf8
  55 #define PCA_IOPORT_QE_TDM_ENABLE        0xf6
  56 #endif
  57
  58 const qe_iop_conf_t qe_iop_conf_tab[] = {
  59         /* GPIO */
  60         {1,   1, 2, 0, 0}, /* GPIO7/PB1   - LOAD_DEFAULT_N */
  61 #if defined(CONFIG_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
  62         {1,   8, 1, 1, 0}, /* GPIO10/PB8  - DDR_RST */
  63 #endif
  64         {0,  15, 1, 0, 0}, /* GPIO11/A15  - WDI */
  65         {GPIO_GETH_SW_PORT, GPIO_GETH_SW_PIN, 1, 0, 0}, /* RST_GETH_SW_N */
  66         {GPIO_SLIC_PORT, GPIO_SLIC_PIN, 1, 0, 0},       /* RST_SLIC_N */
  67
  68 #ifdef CONFIG_P1025RDB
  69         /* QE_MUX_MDC */
  70         {1,  19, 1, 0, 1}, /* QE_MUX_MDC               */
  71
  72         /* QE_MUX_MDIO */
  73         {1,  20, 3, 0, 1}, /* QE_MUX_MDIO              */
  74
  75         /* UCC_1_MII */
  76         {0, 23, 2, 0, 2}, /* CLK12 */
  77         {0, 24, 2, 0, 1}, /* CLK9 */
  78         {0,  7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0      */
  79         {0,  9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1      */
  80         {0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2      */
  81         {0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3      */
  82         {0,  6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0      */
  83         {0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1      */
  84         {0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2      */
  85         {0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3      */
  86         {0,  5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B    */
  87         {0, 13, 1, 0, 2}, /* ENET1_TX_ER               */
  88         {0,  4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B    */
  89         {0,  8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B    */
  90         {0, 17, 2, 0, 2}, /* ENET1_CRS    */
  91         {0, 16, 2, 0, 2}, /* ENET1_COL    */
  92
  93         /* UCC_5_RMII */
  94         {1, 11, 2, 0, 1}, /* CLK13 */
  95         {1, 7,  1, 0, 2}, /* ENET5_TXD0_SER5_TXD0      */
  96         {1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1      */
  97         {1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0      */
  98         {1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1      */
  99         {1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B    */
 100         {1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B    */
 101         {1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B    */
 102 #endif
 103
 104         {0,  0, 0, 0, QE_IOP_TAB_END} /* END of table */
 105 };
 106 #endif
 107
 108 struct cpld_data {
 109         u8 cpld_rev_major;
 110         u8 pcba_rev;
 111         u8 wd_cfg;
 112         u8 rst_bps_sw;
 113         u8 load_default_n;
 114         u8 rst_bps_wd;
 115         u8 bypass_enable;
 116         u8 bps_led;
 117         u8 status_led;                  /* offset: 0x8 */
 118         u8 fxo_led;                     /* offset: 0x9 */
 119         u8 fxs_led;                     /* offset: 0xa */
 120         u8 rev4[2];
 121         u8 system_rst;                  /* offset: 0xd */
 122         u8 bps_out;
 123         u8 rev5[3];
 124         u8 cpld_rev_minor;
 125 };
 126
 127 #define CPLD_WD_CFG     0x03
 128 #define CPLD_RST_BSW    0x00
 129 #define CPLD_RST_BWD    0x00
 130 #define CPLD_BYPASS_EN  0x03
 131 #define CPLD_STATUS_LED 0x01
 132 #define CPLD_FXO_LED    0x01
 133 #define CPLD_FXS_LED    0x0F
 134 #define CPLD_SYS_RST    0x00
 135
 136 void board_cpld_init(void)
 137 {
 138         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 139
 140         out_8(&cpld_data->wd_cfg, CPLD_WD_CFG);
 141         out_8(&cpld_data->status_led, CPLD_STATUS_LED);
 142         out_8(&cpld_data->fxo_led, CPLD_FXO_LED);
 143         out_8(&cpld_data->fxs_led, CPLD_FXS_LED);
 144         out_8(&cpld_data->system_rst, CPLD_SYS_RST);
 145 }
 146
 147 void board_gpio_init(void)
 148 {
 149 #ifdef CONFIG_QE
 150         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 151         par_io_t *par_io = (par_io_t *) &(gur->qe_par_io);
 152
 153 #if defined(CONFIG_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
 154         /* reset DDR3 */
 155         setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
 156         udelay(1000);
 157         clrbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
 158         udelay(1000);
 159         setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
 160         /* disable CE_PB8 */
 161         clrbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdir1, GPIO_2BIT_MASK);
 162 #endif
 163         /* Enable VSC7385 switch */
 164         setbits_be32(&par_io[GPIO_GETH_SW_PORT].cpdat, GPIO_GETH_SW_DATA);
 165
 166         /* Enable SLIC */
 167         setbits_be32(&par_io[GPIO_SLIC_PORT].cpdat, GPIO_SLIC_DATA);
 168 #else
 169
 170         ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
 171
 172         /*
 173          * GPIO10 DDR Reset, open drain
 174          * GPIO7  LOAD_DEFAULT_N          Input
 175          * GPIO11  WDI (watchdog input)
 176          * GPIO12  Ethernet Switch Reset
 177          * GPIO13  SLIC Reset
 178          */
 179
 180         setbits_be32(&pgpio->gpdir, 0x02130000);
 181 #if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SPL)
 182         /* init DDR3 reset signal */
 183         setbits_be32(&pgpio->gpdir, 0x00200000);
 184         setbits_be32(&pgpio->gpodr, 0x00200000);
 185         clrbits_be32(&pgpio->gpdat, 0x00200000);
 186         udelay(1000);
 187         setbits_be32(&pgpio->gpdat, 0x00200000);
 188         udelay(1000);
 189         clrbits_be32(&pgpio->gpdir, 0x00200000);
 190 #endif
 191
 192 #ifdef CONFIG_VSC7385_ENET
 193         /* reset VSC7385 Switch */
 194         setbits_be32(&pgpio->gpdir, 0x00080000);
 195         setbits_be32(&pgpio->gpdat, 0x00080000);
 196 #endif
 197
 198 #ifdef CONFIG_SLIC
 199         /* reset SLIC */
 200         setbits_be32(&pgpio->gpdir, 0x00040000);
 201         setbits_be32(&pgpio->gpdat, 0x00040000);
 202 #endif
 203 #endif
 204 }
 205
 206 int board_early_init_f(void)
 207 {
 208         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 209
 210         setbits_be32(&gur->pmuxcr,
 211                         (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
 212         clrbits_be32(&gur->sdhcdcr, SDHCDCR_CD_INV);
 213
 214         clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
 215         setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TDM_ENA);
 216
 217         board_gpio_init();
 218         board_cpld_init();
 219
 220         return 0;
 221 }
 222
 223 int checkboard(void)
 224 {
 225         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 226         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 227         u8 in, out, io_config, val;
 228
 229         printf("Board: %s CPLD: V%d.%d PCBA: V%d.0\n", CONFIG_BOARDNAME,
 230                 in_8(&cpld_data->cpld_rev_major) & 0x0F,
 231                 in_8(&cpld_data->cpld_rev_minor) & 0x0F,
 232                 in_8(&cpld_data->pcba_rev) & 0x0F);
 233
 234         /* Initialize i2c early for rom_loc and flash bank information */
 235         i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
 236
 237         if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 ||
 238             i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 ||
 239             i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 3, 1, &io_config, 1) < 0) {
 240                 printf("Error reading i2c boot information!\n");
 241                 return 0; /* Don't want to hang() on this error */
 242         }
 243
 244         val = (in & io_config) | (out & (~io_config));
 245
 246         puts("rom_loc: ");
 247         if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD) {
 248                 puts("sd");
 249 #ifdef __SW_BOOT_SPI
 250         } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SPI) {
 251                 puts("spi");
 252 #endif
 253 #ifdef __SW_BOOT_NAND
 254         } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_NAND) {
 255                 puts("nand");
 256 #endif
 257 #ifdef __SW_BOOT_PCIE
 258         } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_PCIE) {
 259                 puts("pcie");
 260 #endif
 261         } else {
 262                 if (val & 0x2)
 263                         puts("nor lower bank");
 264                 else
 265                         puts("nor upper bank");
 266         }
 267         puts("\n");
 268
 269         if (val & 0x1) {
 270                 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
 271                 puts("SD/MMC : 8-bit Mode\n");
 272                 puts("eSPI : Disabled\n");
 273         } else {
 274                 puts("SD/MMC : 4-bit Mode\n");
 275                 puts("eSPI : Enabled\n");
 276         }
 277
 278         return 0;
 279 }
 280
 281 #ifdef CONFIG_PCI
 282 void pci_init_board(void)
 283 {
 284         fsl_pcie_init_board(0);
 285 }
 286 #endif
 287
 288 int board_early_init_r(void)
 289 {
 290         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 291         const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
 292
 293         /*
 294          * Remap Boot flash region to caching-inhibited
 295          * so that flash can be erased properly.
 296          */
 297
 298         /* Flush d-cache and invalidate i-cache of any FLASH data */
 299         flush_dcache();
 300         invalidate_icache();
 301
 302         /* invalidate existing TLB entry for flash */
 303         disable_tlb(flash_esel);
 304
 305         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
 306                 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,/* perms, wimge */
 307                 0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
 308         return 0;
 309 }
 310
 311 int board_eth_init(bd_t *bis)
 312 {
 313         struct fsl_pq_mdio_info mdio_info;
 314         struct tsec_info_struct tsec_info[4];
 315         ccsr_gur_t *gur __attribute__((unused)) =
 316                 (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 317         int num = 0;
 318 #ifdef CONFIG_VSC7385_ENET
 319         char *tmp;
 320         unsigned int vscfw_addr;
 321 #endif
 322
 323 #ifdef CONFIG_TSEC1
 324         SET_STD_TSEC_INFO(tsec_info[num], 1);
 325         num++;
 326 #endif
 327 #ifdef CONFIG_TSEC2
 328         SET_STD_TSEC_INFO(tsec_info[num], 2);
 329         if (is_serdes_configured(SGMII_TSEC2)) {
 330                 printf("eTSEC2 is in sgmii mode.\n");
 331                 tsec_info[num].flags |= TSEC_SGMII;
 332         }
 333         num++;
 334 #endif
 335 #ifdef CONFIG_TSEC3
 336         SET_STD_TSEC_INFO(tsec_info[num], 3);
 337         num++;
 338 #endif
 339
 340         if (!num) {
 341                 printf("No TSECs initialized\n");
 342                 return 0;
 343         }
 344
 345 #ifdef CONFIG_VSC7385_ENET
 346         /* If a VSC7385 microcode image is present, then upload it. */
 347         if ((tmp = getenv("vscfw_addr")) != NULL) {
 348                 vscfw_addr = simple_strtoul(tmp, NULL, 16);
 349                 printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
 350                 if (vsc7385_upload_firmware((void *) vscfw_addr,
 351                                         CONFIG_VSC7385_IMAGE_SIZE))
 352                         puts("Failure uploading VSC7385 microcode.\n");
 353         } else
 354                 puts("No address specified for VSC7385 microcode.\n");
 355 #endif
 356
 357         mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
 358         mdio_info.name = DEFAULT_MII_NAME;
 359
 360         fsl_pq_mdio_init(bis, &mdio_info);
 361
 362         tsec_eth_init(bis, tsec_info, num);
 363
 364 #if defined(CONFIG_UEC_ETH)
 365         /*  QE0 and QE3 need to be exposed for UCC1 and UCC5 Eth mode */
 366         setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE0);
 367         setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE3);
 368
 369         uec_standard_init(bis);
 370 #endif
 371
 372         return pci_eth_init(bis);
 373 }
 374
 375 #if defined(CONFIG_QE) && \
 376         (defined(CONFIG_P1025RDB) || defined(CONFIG_P1021RDB))
 377 static void fdt_board_fixup_qe_pins(void *blob)
 378 {
 379         unsigned int oldbus;
 380         u8 val8;
 381         int node;
 382         fsl_lbc_t *lbc = LBC_BASE_ADDR;
 383
 384         if (hwconfig("qe")) {
 385                 /* For QE and eLBC pins multiplexing,
 386                  * there is a PCA9555 device on P1025RDB.
 387                  * It control the multiplex pins' functions,
 388                  * and setting the PCA9555 can switch the
 389                  * function between QE and eLBC.
 390                  */
 391                 oldbus = i2c_get_bus_num();
 392                 i2c_set_bus_num(0);
 393                 if (hwconfig("tdm"))
 394                         val8 = PCA_IOPORT_QE_TDM_ENABLE;
 395                 else
 396                         val8 = PCA_IOPORT_QE_PIN_ENABLE;
 397                 i2c_write(PCA_IOPORT_I2C_ADDR, PCA_IOPORT_CFG_CMD,
 398                                 1, &val8, 1);
 399                 i2c_write(PCA_IOPORT_I2C_ADDR, PCA_IOPORT_OUTPUT_CMD,
 400                                 1, &val8, 1);
 401                 i2c_set_bus_num(oldbus);
 402                 /* if run QE TDM, Set ABSWP to implement
 403                  * conversion of addresses in the eLBC.
 404                  */
 405                 if (hwconfig("tdm")) {
 406                         set_lbc_or(2, CONFIG_PMC_OR_PRELIM);
 407                         set_lbc_br(2, CONFIG_PMC_BR_PRELIM);
 408                         setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
 409                 }
 410         } else {
 411                 node = fdt_path_offset(blob, "/qe");
 412                 if (node >= 0)
 413                         fdt_del_node(blob, node);
 414         }
 415
 416         return;
 417 }
 418 #endif
 419
 420 #ifdef CONFIG_OF_BOARD_SETUP
 421 void ft_board_setup(void *blob, bd_t *bd)
 422 {
 423         phys_addr_t base;
 424         phys_size_t size;
 425         const char *soc_usb_compat = "fsl-usb2-dr";
 426         int err, usb1_off, usb2_off;
 427
 428         ft_cpu_setup(blob, bd);
 429
 430         base = getenv_bootm_low();
 431         size = getenv_bootm_size();
 432
 433         fdt_fixup_memory(blob, (u64)base, (u64)size);
 434
 435         FT_FSL_PCI_SETUP;
 436
 437 #ifdef CONFIG_QE
 438         do_fixup_by_compat(blob, "fsl,qe", "status", "okay",
 439                         sizeof("okay"), 0);
 440 #if defined(CONFIG_P1025RDB) || defined(CONFIG_P1021RDB)
 441         fdt_board_fixup_qe_pins(blob);
 442 #endif
 443 #endif
 444
 445 #if defined(CONFIG_HAS_FSL_DR_USB)
 446         fdt_fixup_dr_usb(blob, bd);
 447 #endif
 448
 449 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
 450         /* Delete eLBC node as it is muxed with USB2 controller */
 451         if (hwconfig("usb2")) {
 452                 const char *soc_elbc_compat = "fsl,p1020-elbc";
 453                 int off = fdt_node_offset_by_compatible(blob, -1,
 454                                 soc_elbc_compat);
 455                 if (off < 0) {
 456                         printf("WARNING: could not find compatible node %s: %s.\n",
 457                                soc_elbc_compat,
 458                                fdt_strerror(off));
 459                                 return;
 460                 }
 461                 err = fdt_del_node(blob, off);
 462                 if (err < 0) {
 463                         printf("WARNING: could not remove %s: %s.\n",
 464                                soc_elbc_compat, fdt_strerror(err));
 465                 }
 466                 return;
 467         }
 468 #endif
 469
 470 /* Delete USB2 node as it is muxed with eLBC */
 471         usb1_off = fdt_node_offset_by_compatible(blob, -1,
 472                 soc_usb_compat);
 473         if (usb1_off < 0) {
 474                 printf("WARNING: could not find compatible node %s: %s.\n",
 475                        soc_usb_compat,
 476                        fdt_strerror(usb1_off));
 477                 return;
 478         }
 479         usb2_off = fdt_node_offset_by_compatible(blob, usb1_off,
 480                         soc_usb_compat);
 481         if (usb2_off < 0) {
 482                 printf("WARNING: could not find compatible node %s: %s.\n",
 483                        soc_usb_compat,
 484                        fdt_strerror(usb2_off));
 485                 return;
 486         }
 487         err = fdt_del_node(blob, usb2_off);
 488         if (err < 0) {
 489                 printf("WARNING: could not remove %s: %s.\n",
 490                        soc_usb_compat, fdt_strerror(err));
 491         }
 492
 493 }
 494 #endif