board/gdsys/p1022/controlcenterd.c

   1 /*
   2  * (C) Copyright 2013
   3  * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <command.h>
  26 #include <pci.h>
  27 #include <asm/processor.h>
  28 #include <asm/mmu.h>
  29 #include <asm/cache.h>
  30 #include <asm/immap_85xx.h>
  31 #include <asm/fsl_pci.h>
  32 #include <fsl_ddr_sdram.h>
  33 #include <asm/fsl_serdes.h>
  34 #include <asm/io.h>
  35 #include <libfdt.h>
  36 #include <fdt_support.h>
  37 #include <fsl_mdio.h>
  38 #include <tsec.h>
  39 #include <asm/fsl_law.h>
  40 #include <netdev.h>
  41 #include <i2c.h>
  42 #include <pca9698.h>
  43 #include <watchdog.h>
  44 #include "../common/dp501.h"
  45 #include "controlcenterd-id.h"
  46
  47 DECLARE_GLOBAL_DATA_PTR;
  48
  49 enum {
  50         HWVER_100 = 0,
  51         HWVER_110 = 1,
  52         HWVER_120 = 2,
  53 };
  54
  55 struct ihs_fpga {
  56         u32 reflection_low;     /* 0x0000 */
  57         u32 versions;           /* 0x0004 */
  58         u32 fpga_version;       /* 0x0008 */
  59         u32 fpga_features;      /* 0x000c */
  60 };
  61
  62 #ifndef CONFIG_TRAILBLAZER
  63 static struct pci_device_id hydra_supported[] = {
  64         { 0x6d5e, 0xcdc0 },
  65         {}
  66 };
  67
  68 static void hydra_initialize(void);
  69 #endif
  70
  71 int board_early_init_f(void)
  72 {
  73         ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  74         ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO3_ADDR);
  75
  76         /* Reset eLBC_DIU and SPI_eLBC in case we are booting from SD */
  77         clrsetbits_be32(&gur->pmuxcr, 0x00600000, 0x80000000);
  78
  79         /* Set pmuxcr to allow both i2c1 and i2c2 */
  80         setbits_be32(&gur->pmuxcr, 0x00001000);
  81
  82         /* Set pmuxcr to enable GPIO 3_11-3_13 */
  83         setbits_be32(&gur->pmuxcr, 0x00000010);
  84
  85         /* Set pmuxcr to enable GPIO 2_31,3_9+10 */
  86         setbits_be32(&gur->pmuxcr, 0x00000020);
  87
  88         /* Set pmuxcr to enable GPIO 2_28-2_30 */
  89         setbits_be32(&gur->pmuxcr, 0x000000c0);
  90
  91         /* Set pmuxcr to enable GPIO 3_20-3_22 */
  92         setbits_be32(&gur->pmuxcr2, 0x03000000);
  93
  94         /* Set pmuxcr to enable IRQ0-2 */
  95         clrbits_be32(&gur->pmuxcr, 0x00000300);
  96
  97         /* Set pmuxcr to disable IRQ3-11 */
  98         setbits_be32(&gur->pmuxcr, 0x000000F0);
  99
 100         /* Read back the register to synchronize the write. */
 101         in_be32(&gur->pmuxcr);
 102
 103         /* Set the pin muxing to enable ETSEC2. */
 104         clrbits_be32(&gur->pmuxcr2, 0x001F8000);
 105
 106 #ifdef CONFIG_TRAILBLAZER
 107         /*
 108          * GPIO3_10 SPERRTRIGGER
 109          */
 110         setbits_be32(&pgpio->gpdir, 0x00200000);
 111         clrbits_be32(&pgpio->gpdat, 0x00200000);
 112         udelay(100);
 113         setbits_be32(&pgpio->gpdat, 0x00200000);
 114         udelay(100);
 115         clrbits_be32(&pgpio->gpdat, 0x00200000);
 116 #endif
 117
 118         /*
 119          * GPIO3_11 CPU-TO-FPGA-RESET#
 120          */
 121         setbits_be32(&pgpio->gpdir, 0x00100000);
 122         clrbits_be32(&pgpio->gpdat, 0x00100000);
 123
 124         /*
 125          * GPIO3_21 CPU-STATUS-WATCHDOG-TRIGGER#
 126          */
 127         setbits_be32(&pgpio->gpdir, 0x00000400);
 128
 129         return 0;
 130 }
 131
 132 int checkboard(void)
 133 {
 134         printf("Board: ControlCenter DIGITAL\n");
 135
 136         return 0;
 137 }
 138
 139 int misc_init_r(void)
 140 {
 141         return 0;
 142 }
 143
 144 /*
 145  * A list of PCI and SATA slots
 146  */
 147 enum slot_id {
 148         SLOT_PCIE1 = 1,
 149         SLOT_PCIE2,
 150         SLOT_PCIE3,
 151         SLOT_PCIE4,
 152         SLOT_PCIE5,
 153         SLOT_SATA1,
 154         SLOT_SATA2
 155 };
 156
 157 /*
 158  * This array maps the slot identifiers to their names on the P1022DS board.
 159  */
 160 static const char * const slot_names[] = {
 161         [SLOT_PCIE1] = "Slot 1",
 162         [SLOT_PCIE2] = "Slot 2",
 163         [SLOT_PCIE3] = "Slot 3",
 164         [SLOT_PCIE4] = "Slot 4",
 165         [SLOT_PCIE5] = "Mini-PCIe",
 166         [SLOT_SATA1] = "SATA 1",
 167         [SLOT_SATA2] = "SATA 2",
 168 };
 169
 170 /*
 171  * This array maps a given SERDES configuration and SERDES device to the PCI or
 172  * SATA slot that it connects to.  This mapping is hard-coded in the FPGA.
 173  */
 174 static u8 serdes_dev_slot[][SATA2 + 1] = {
 175         [0x01] = { [PCIE3] = SLOT_PCIE4, [PCIE2] = SLOT_PCIE5 },
 176         [0x02] = { [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
 177         [0x09] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE4,
 178                    [PCIE2] = SLOT_PCIE5 },
 179         [0x16] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
 180                    [PCIE2] = SLOT_PCIE3,
 181                    [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
 182         [0x17] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
 183                    [PCIE2] = SLOT_PCIE3 },
 184         [0x1a] = { [PCIE1] = SLOT_PCIE1, [PCIE2] = SLOT_PCIE3,
 185                    [PCIE2] = SLOT_PCIE3,
 186                    [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
 187         [0x1c] = { [PCIE1] = SLOT_PCIE1,
 188                    [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
 189         [0x1e] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE3 },
 190         [0x1f] = { [PCIE1] = SLOT_PCIE1 },
 191 };
 192
 193
 194 /*
 195  * Returns the name of the slot to which the PCIe or SATA controller is
 196  * connected
 197  */
 198 const char *board_serdes_name(enum srds_prtcl device)
 199 {
 200         ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
 201         u32 pordevsr = in_be32(&gur->pordevsr);
 202         unsigned int srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
 203                                 MPC85xx_PORDEVSR_IO_SEL_SHIFT;
 204         enum slot_id slot = serdes_dev_slot[srds_cfg][device];
 205         const char *name = slot_names[slot];
 206
 207         if (name)
 208                 return name;
 209         else
 210                 return "Nothing";
 211 }
 212
 213 void hw_watchdog_reset(void)
 214 {
 215         ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO3_ADDR);
 216
 217         clrbits_be32(&pgpio->gpdat, 0x00000400);
 218         setbits_be32(&pgpio->gpdat, 0x00000400);
 219 }
 220
 221 #ifdef CONFIG_TRAILBLAZER
 222 int do_bootd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 223 {
 224         int rcode = 0;
 225
 226         if (run_command(getenv("bootcmd"), flag) < 0)
 227                 rcode = 1;
 228         return rcode;
 229 }
 230
 231 int board_early_init_r(void)
 232 {
 233         ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO3_ADDR);
 234
 235         /*
 236          * GPIO3_12 PPC_SYSTEMREADY#
 237          */
 238         setbits_be32(&pgpio->gpdir, 0x00080000);
 239         setbits_be32(&pgpio->gpodr, 0x00080000);
 240         clrbits_be32(&pgpio->gpdat, 0x00080000);
 241
 242         return ccdm_compute_self_hash();
 243 }
 244
 245 int last_stage_init(void)
 246 {
 247         startup_ccdm_id_module();
 248         return 0;
 249 }
 250
 251 #else
 252 void pci_init_board(void)
 253 {
 254         fsl_pcie_init_board(0);
 255
 256         hydra_initialize();
 257 }
 258
 259 int board_early_init_r(void)
 260 {
 261         unsigned int k = 0;
 262         ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO3_ADDR);
 263
 264         /* wait for FPGA configuration to finish */
 265         while (!pca9698_get_value(0x22, 11) && (k++ < 30))
 266                 udelay(100000);
 267
 268         if (k > 30) {
 269                 puts("FPGA configuration timed out.\n");
 270         } else {
 271                 /* clear FPGA reset */
 272                 udelay(1000);
 273                 setbits_be32(&pgpio->gpdat, 0x00100000);
 274         }
 275
 276         /* give time for PCIe link training */
 277         udelay(100000);
 278
 279         /*
 280          * GPIO3_12 PPC_SYSTEMREADY#
 281          */
 282         setbits_be32(&pgpio->gpdir, 0x00080000);
 283         setbits_be32(&pgpio->gpodr, 0x00080000);
 284         clrbits_be32(&pgpio->gpdat, 0x00080000);
 285
 286         return 0;
 287 }
 288
 289 int last_stage_init(void)
 290 {
 291         /* Turn on Parade DP501 */
 292         pca9698_direction_output(0x22, 7, 1);
 293         udelay(500000);
 294
 295         dp501_powerup(0x08);
 296
 297         startup_ccdm_id_module();
 298
 299         return 0;
 300 }
 301
 302 /*
 303  * Initialize on-board and/or PCI Ethernet devices
 304  *
 305  * Returns:
 306  *      <0, error
 307  *       0, no ethernet devices found
 308  *      >0, number of ethernet devices initialized
 309  */
 310 int board_eth_init(bd_t *bis)
 311 {
 312         struct fsl_pq_mdio_info mdio_info;
 313         struct tsec_info_struct tsec_info[2];
 314         unsigned int num = 0;
 315
 316 #ifdef CONFIG_TSEC1
 317         SET_STD_TSEC_INFO(tsec_info[num], 1);
 318         num++;
 319 #endif
 320 #ifdef CONFIG_TSEC2
 321         SET_STD_TSEC_INFO(tsec_info[num], 2);
 322         num++;
 323 #endif
 324
 325         mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
 326         mdio_info.name = DEFAULT_MII_NAME;
 327         fsl_pq_mdio_init(bis, &mdio_info);
 328
 329         return tsec_eth_init(bis, tsec_info, num) + pci_eth_init(bis);
 330 }
 331
 332 #ifdef CONFIG_OF_BOARD_SETUP
 333 void ft_board_setup(void *blob, bd_t *bd)
 334 {
 335         phys_addr_t base;
 336         phys_size_t size;
 337
 338         ft_cpu_setup(blob, bd);
 339
 340         base = getenv_bootm_low();
 341         size = getenv_bootm_size();
 342
 343         fdt_fixup_memory(blob, (u64)base, (u64)size);
 344
 345 #ifdef CONFIG_HAS_FSL_DR_USB
 346         fdt_fixup_dr_usb(blob, bd);
 347 #endif
 348
 349         FT_FSL_PCI_SETUP;
 350 }
 351 #endif
 352
 353 static void hydra_initialize(void)
 354 {
 355         unsigned int i;
 356         pci_dev_t devno;
 357
 358         /* Find and probe all the matching PCI devices */
 359         for (i = 0; (devno = pci_find_devices(hydra_supported, i)) >= 0; i++) {
 360                 u32 val;
 361                 struct ihs_fpga *fpga;
 362                 u32 versions;
 363                 u32 fpga_version;
 364                 u32 fpga_features;
 365
 366                 unsigned hardware_version;
 367                 unsigned feature_uart_channels;
 368                 unsigned feature_sb_channels;
 369
 370                 /* Try to enable I/O accesses and bus-mastering */
 371                 val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
 372                 pci_write_config_dword(devno, PCI_COMMAND, val);
 373
 374                 /* Make sure it worked */
 375                 pci_read_config_dword(devno, PCI_COMMAND, &val);
 376                 if (!(val & PCI_COMMAND_MEMORY)) {
 377                         puts("Can't enable I/O memory\n");
 378                         continue;
 379                 }
 380                 if (!(val & PCI_COMMAND_MASTER)) {
 381                         puts("Can't enable bus-mastering\n");
 382                         continue;
 383                 }
 384
 385                 /* read FPGA details */
 386                 fpga = pci_map_bar(devno, PCI_BASE_ADDRESS_0,
 387                         PCI_REGION_MEM);
 388
 389                 versions = readl(fpga->versions);
 390                 fpga_version = readl(fpga->fpga_version);
 391                 fpga_features = readl(fpga->fpga_features);
 392
 393                 hardware_version = versions & 0xf;
 394                 feature_uart_channels = (fpga_features >> 6) & 0x1f;
 395                 feature_sb_channels = fpga_features & 0x1f;
 396
 397                 printf("FPGA%d: ", i);
 398
 399                 switch (hardware_version) {
 400                 case HWVER_100:
 401                         printf("HW-Ver 1.00\n");
 402                         break;
 403
 404                 case HWVER_110:
 405                         printf("HW-Ver 1.10\n");
 406                         break;
 407
 408                 case HWVER_120:
 409                         printf("HW-Ver 1.20\n");
 410                         break;
 411
 412                 default:
 413                         printf("HW-Ver %d(not supported)\n",
 414                                hardware_version);
 415                         break;
 416                 }
 417
 418                 printf("       FPGA V %d.%02d, features:",
 419                        fpga_version / 100, fpga_version % 100);
 420
 421                 printf(" %d uart channel(s)", feature_uart_channels);
 422                 printf(" %d sideband channel(s)\n", feature_sb_channels);
 423         }
 424 }
 425 #endif