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board:samsung:trats: add env variables describing platform
[people/ms/u-boot.git] / board / samsung / trats / trats.c
1 /*
2 * Copyright (C) 2011 Samsung Electronics
3 * Heungjun Kim <riverful.kim@samsung.com>
4 * Kyungmin Park <kyungmin.park@samsung.com>
5 * Donghwa Lee <dh09.lee@samsung.com>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10 #include <common.h>
11 #include <lcd.h>
12 #include <asm/io.h>
13 #include <asm/arch/cpu.h>
14 #include <asm/arch/gpio.h>
15 #include <asm/arch/mmc.h>
16 #include <asm/arch/pinmux.h>
17 #include <asm/arch/clock.h>
18 #include <asm/arch/clk.h>
19 #include <asm/arch/mipi_dsim.h>
20 #include <asm/arch/watchdog.h>
21 #include <asm/arch/power.h>
22 #include <power/pmic.h>
23 #include <usb/s3c_udc.h>
24 #include <power/max8997_pmic.h>
25 #include <libtizen.h>
26 #include <power/max8997_muic.h>
27 #include <power/battery.h>
28 #include <power/max17042_fg.h>
29 #include <usb.h>
30 #include <usb_mass_storage.h>
31 #include <samsung/misc.h>
32
33 #include "setup.h"
34
35 DECLARE_GLOBAL_DATA_PTR;
36
37 unsigned int board_rev;
38
39 #ifdef CONFIG_REVISION_TAG
40 u32 get_board_rev(void)
41 {
42 return board_rev;
43 }
44 #endif
45
46 static void check_hw_revision(void);
47 struct s3c_plat_otg_data s5pc210_otg_data;
48
49 int board_init(void)
50 {
51 gd->bd->bi_boot_params = CONFIG_SYS_SPL_ARGS_ADDR;
52
53 check_hw_revision();
54 printf("HW Revision:\t0x%x\n", board_rev);
55
56 return 0;
57 }
58
59 void i2c_init_board(void)
60 {
61 int err;
62 struct exynos4_gpio_part2 *gpio2 =
63 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
64
65 /* I2C_5 -> PMIC */
66 err = exynos_pinmux_config(PERIPH_ID_I2C5, PINMUX_FLAG_NONE);
67 if (err) {
68 debug("I2C%d not configured\n", (I2C_5));
69 return;
70 }
71
72 /* I2C_8 -> FG */
73 s5p_gpio_direction_output(&gpio2->y4, 0, 1);
74 s5p_gpio_direction_output(&gpio2->y4, 1, 1);
75 }
76
77 static void trats_low_power_mode(void)
78 {
79 struct exynos4_clock *clk =
80 (struct exynos4_clock *)samsung_get_base_clock();
81 struct exynos4_power *pwr =
82 (struct exynos4_power *)samsung_get_base_power();
83
84 /* Power down CORE1 */
85 /* LOCAL_PWR_CFG [1:0] 0x3 EN, 0x0 DIS */
86 writel(0x0, &pwr->arm_core1_configuration);
87
88 /* Change the APLL frequency */
89 /* ENABLE (1 enable) | LOCKED (1 locked) */
90 /* [31] | [29] */
91 /* FSEL | MDIV | PDIV | SDIV */
92 /* [27] | [25:16] | [13:8] | [2:0] */
93 writel(0xa0c80604, &clk->apll_con0);
94
95 /* Change CPU0 clock divider */
96 /* CORE2_RATIO | APLL_RATIO | PCLK_DBG_RATIO | ATB_RATIO */
97 /* [30:28] | [26:24] | [22:20] | [18:16] */
98 /* PERIPH_RATIO | COREM1_RATIO | COREM0_RATIO | CORE_RATIO */
99 /* [14:12] | [10:8] | [6:4] | [2:0] */
100 writel(0x00000100, &clk->div_cpu0);
101
102 /* CLK_DIV_STAT_CPU0 - wait until clock gets stable (0 = stable) */
103 while (readl(&clk->div_stat_cpu0) & 0x1111111)
104 continue;
105
106 /* Change clock divider ratio for DMC */
107 /* DMCP_RATIO | DMCD_RATIO */
108 /* [22:20] | [18:16] */
109 /* DMC_RATIO | DPHY_RATIO | ACP_PCLK_RATIO | ACP_RATIO */
110 /* [14:12] | [10:8] | [6:4] | [2:0] */
111 writel(0x13113117, &clk->div_dmc0);
112
113 /* CLK_DIV_STAT_DMC0 - wait until clock gets stable (0 = stable) */
114 while (readl(&clk->div_stat_dmc0) & 0x11111111)
115 continue;
116
117 /* Turn off unnecessary power domains */
118 writel(0x0, &pwr->xxti_configuration); /* XXTI */
119 writel(0x0, &pwr->cam_configuration); /* CAM */
120 writel(0x0, &pwr->tv_configuration); /* TV */
121 writel(0x0, &pwr->mfc_configuration); /* MFC */
122 writel(0x0, &pwr->g3d_configuration); /* G3D */
123 writel(0x0, &pwr->gps_configuration); /* GPS */
124 writel(0x0, &pwr->gps_alive_configuration); /* GPS_ALIVE */
125
126 /* Turn off unnecessary clocks */
127 writel(0x0, &clk->gate_ip_cam); /* CAM */
128 writel(0x0, &clk->gate_ip_tv); /* TV */
129 writel(0x0, &clk->gate_ip_mfc); /* MFC */
130 writel(0x0, &clk->gate_ip_g3d); /* G3D */
131 writel(0x0, &clk->gate_ip_image); /* IMAGE */
132 writel(0x0, &clk->gate_ip_gps); /* GPS */
133 }
134
135 static int pmic_init_max8997(void)
136 {
137 struct pmic *p = pmic_get("MAX8997_PMIC");
138 int i = 0, ret = 0;
139 u32 val;
140
141 if (pmic_probe(p))
142 return -1;
143
144 /* BUCK1 VARM: 1.2V */
145 val = (1200000 - 650000) / 25000;
146 ret |= pmic_reg_write(p, MAX8997_REG_BUCK1DVS1, val);
147 val = ENBUCK | ACTIVE_DISCHARGE; /* DVS OFF */
148 ret |= pmic_reg_write(p, MAX8997_REG_BUCK1CTRL, val);
149
150 /* BUCK2 VINT: 1.1V */
151 val = (1100000 - 650000) / 25000;
152 ret |= pmic_reg_write(p, MAX8997_REG_BUCK2DVS1, val);
153 val = ENBUCK | ACTIVE_DISCHARGE; /* DVS OFF */
154 ret |= pmic_reg_write(p, MAX8997_REG_BUCK2CTRL, val);
155
156
157 /* BUCK3 G3D: 1.1V - OFF */
158 ret |= pmic_reg_read(p, MAX8997_REG_BUCK3CTRL, &val);
159 val &= ~ENBUCK;
160 ret |= pmic_reg_write(p, MAX8997_REG_BUCK3CTRL, val);
161
162 val = (1100000 - 750000) / 50000;
163 ret |= pmic_reg_write(p, MAX8997_REG_BUCK3DVS, val);
164
165 /* BUCK4 CAMISP: 1.2V - OFF */
166 ret |= pmic_reg_read(p, MAX8997_REG_BUCK4CTRL, &val);
167 val &= ~ENBUCK;
168 ret |= pmic_reg_write(p, MAX8997_REG_BUCK4CTRL, val);
169
170 val = (1200000 - 650000) / 25000;
171 ret |= pmic_reg_write(p, MAX8997_REG_BUCK4DVS, val);
172
173 /* BUCK5 VMEM: 1.2V */
174 val = (1200000 - 650000) / 25000;
175 for (i = 0; i < 8; i++)
176 ret |= pmic_reg_write(p, MAX8997_REG_BUCK5DVS1 + i, val);
177
178 val = ENBUCK | ACTIVE_DISCHARGE; /* DVS OFF */
179 ret |= pmic_reg_write(p, MAX8997_REG_BUCK5CTRL, val);
180
181 /* BUCK6 CAM AF: 2.8V */
182 /* No Voltage Setting Register */
183 /* GNSLCT 3.0X */
184 val = GNSLCT;
185 ret |= pmic_reg_write(p, MAX8997_REG_BUCK6CTRL, val);
186
187 /* BUCK7 VCC_SUB: 2.0V */
188 val = (2000000 - 750000) / 50000;
189 ret |= pmic_reg_write(p, MAX8997_REG_BUCK7DVS, val);
190
191 /* LDO1 VADC: 3.3V */
192 val = max8997_reg_ldo(3300000) | DIS_LDO; /* OFF */
193 ret |= pmic_reg_write(p, MAX8997_REG_LDO1CTRL, val);
194
195 /* LDO1 Disable active discharging */
196 ret |= pmic_reg_read(p, MAX8997_REG_LDO1CONFIG, &val);
197 val &= ~LDO_ADE;
198 ret |= pmic_reg_write(p, MAX8997_REG_LDO1CONFIG, val);
199
200 /* LDO2 VALIVE: 1.1V */
201 val = max8997_reg_ldo(1100000) | EN_LDO;
202 ret |= pmic_reg_write(p, MAX8997_REG_LDO2CTRL, val);
203
204 /* LDO3 VUSB/MIPI: 1.1V */
205 val = max8997_reg_ldo(1100000) | DIS_LDO; /* OFF */
206 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, val);
207
208 /* LDO4 VMIPI: 1.8V */
209 val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */
210 ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, val);
211
212 /* LDO5 VHSIC: 1.2V */
213 val = max8997_reg_ldo(1200000) | DIS_LDO; /* OFF */
214 ret |= pmic_reg_write(p, MAX8997_REG_LDO5CTRL, val);
215
216 /* LDO6 VCC_1.8V_PDA: 1.8V */
217 val = max8997_reg_ldo(1800000) | EN_LDO;
218 ret |= pmic_reg_write(p, MAX8997_REG_LDO6CTRL, val);
219
220 /* LDO7 CAM_ISP: 1.8V */
221 val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */
222 ret |= pmic_reg_write(p, MAX8997_REG_LDO7CTRL, val);
223
224 /* LDO8 VDAC/VUSB: 3.3V */
225 val = max8997_reg_ldo(3300000) | DIS_LDO; /* OFF */
226 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, val);
227
228 /* LDO9 VCC_2.8V_PDA: 2.8V */
229 val = max8997_reg_ldo(2800000) | EN_LDO;
230 ret |= pmic_reg_write(p, MAX8997_REG_LDO9CTRL, val);
231
232 /* LDO10 VPLL: 1.1V */
233 val = max8997_reg_ldo(1100000) | EN_LDO;
234 ret |= pmic_reg_write(p, MAX8997_REG_LDO10CTRL, val);
235
236 /* LDO11 TOUCH: 2.8V */
237 val = max8997_reg_ldo(2800000) | DIS_LDO; /* OFF */
238 ret |= pmic_reg_write(p, MAX8997_REG_LDO11CTRL, val);
239
240 /* LDO12 VTCAM: 1.8V */
241 val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */
242 ret |= pmic_reg_write(p, MAX8997_REG_LDO12CTRL, val);
243
244 /* LDO13 VCC_3.0_LCD: 3.0V */
245 val = max8997_reg_ldo(3000000) | DIS_LDO; /* OFF */
246 ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, val);
247
248 /* LDO14 MOTOR: 3.0V */
249 val = max8997_reg_ldo(3000000) | DIS_LDO; /* OFF */
250 ret |= pmic_reg_write(p, MAX8997_REG_LDO14CTRL, val);
251
252 /* LDO15 LED_A: 2.8V */
253 val = max8997_reg_ldo(2800000) | DIS_LDO; /* OFF */
254 ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, val);
255
256 /* LDO16 CAM_SENSOR: 1.8V */
257 val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */
258 ret |= pmic_reg_write(p, MAX8997_REG_LDO16CTRL, val);
259
260 /* LDO17 VTF: 2.8V */
261 val = max8997_reg_ldo(2800000) | DIS_LDO; /* OFF */
262 ret |= pmic_reg_write(p, MAX8997_REG_LDO17CTRL, val);
263
264 /* LDO18 TOUCH_LED 3.3V */
265 val = max8997_reg_ldo(3300000) | DIS_LDO; /* OFF */
266 ret |= pmic_reg_write(p, MAX8997_REG_LDO18CTRL, val);
267
268 /* LDO21 VDDQ: 1.2V */
269 val = max8997_reg_ldo(1200000) | EN_LDO;
270 ret |= pmic_reg_write(p, MAX8997_REG_LDO21CTRL, val);
271
272 /* SAFEOUT for both 1 and 2: 4.9V, Active discharge, Enable */
273 val = (SAFEOUT_4_90V << 0) | (SAFEOUT_4_90V << 2) |
274 ACTDISSAFEO1 | ACTDISSAFEO2 | ENSAFEOUT1 | ENSAFEOUT2;
275 ret |= pmic_reg_write(p, MAX8997_REG_SAFEOUTCTRL, val);
276
277 if (ret) {
278 puts("MAX8997 PMIC setting error!\n");
279 return -1;
280 }
281 return 0;
282 }
283
284 int power_init_board(void)
285 {
286 int chrg, ret;
287 struct power_battery *pb;
288 struct pmic *p_fg, *p_chrg, *p_muic, *p_bat;
289
290 /*
291 * For PMIC/MUIC the I2C bus is named as I2C5, but it is connected
292 * to logical I2C adapter 0
293 *
294 * The FUEL_GAUGE is marked as I2C9 on the schematic, but connected
295 * to logical I2C adapter 1
296 */
297 ret = pmic_init(I2C_5);
298 ret |= pmic_init_max8997();
299 ret |= power_fg_init(I2C_9);
300 ret |= power_muic_init(I2C_5);
301 ret |= power_bat_init(0);
302 if (ret)
303 return ret;
304
305 p_fg = pmic_get("MAX17042_FG");
306 if (!p_fg) {
307 puts("MAX17042_FG: Not found\n");
308 return -ENODEV;
309 }
310
311 p_chrg = pmic_get("MAX8997_PMIC");
312 if (!p_chrg) {
313 puts("MAX8997_PMIC: Not found\n");
314 return -ENODEV;
315 }
316
317 p_muic = pmic_get("MAX8997_MUIC");
318 if (!p_muic) {
319 puts("MAX8997_MUIC: Not found\n");
320 return -ENODEV;
321 }
322
323 p_bat = pmic_get("BAT_TRATS");
324 if (!p_bat) {
325 puts("BAT_TRATS: Not found\n");
326 return -ENODEV;
327 }
328
329 p_fg->parent = p_bat;
330 p_chrg->parent = p_bat;
331 p_muic->parent = p_bat;
332
333 p_bat->low_power_mode = trats_low_power_mode;
334 p_bat->pbat->battery_init(p_bat, p_fg, p_chrg, p_muic);
335
336 pb = p_bat->pbat;
337 chrg = p_muic->chrg->chrg_type(p_muic);
338 debug("CHARGER TYPE: %d\n", chrg);
339
340 if (!p_chrg->chrg->chrg_bat_present(p_chrg)) {
341 puts("No battery detected\n");
342 return -1;
343 }
344
345 p_fg->fg->fg_battery_check(p_fg, p_bat);
346
347 if (pb->bat->state == CHARGE && chrg == CHARGER_USB)
348 puts("CHARGE Battery !\n");
349
350 return 0;
351 }
352
353 int dram_init(void)
354 {
355 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
356 get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) +
357 get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) +
358 get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE);
359
360 return 0;
361 }
362
363 void dram_init_banksize(void)
364 {
365 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
366 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
367 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
368 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
369 gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
370 gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
371 gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
372 gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
373 }
374
375 static unsigned int get_hw_revision(void)
376 {
377 struct exynos4_gpio_part1 *gpio =
378 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
379 int hwrev = 0;
380 int i;
381
382 /* hw_rev[3:0] == GPE1[3:0] */
383 for (i = 0; i < 4; i++) {
384 s5p_gpio_cfg_pin(&gpio->e1, i, GPIO_INPUT);
385 s5p_gpio_set_pull(&gpio->e1, i, GPIO_PULL_NONE);
386 }
387
388 udelay(1);
389
390 for (i = 0; i < 4; i++)
391 hwrev |= (s5p_gpio_get_value(&gpio->e1, i) << i);
392
393 debug("hwrev 0x%x\n", hwrev);
394
395 return hwrev;
396 }
397
398 static void check_hw_revision(void)
399 {
400 int hwrev;
401
402 hwrev = get_hw_revision();
403
404 board_rev |= hwrev;
405 }
406
407 #ifdef CONFIG_DISPLAY_BOARDINFO
408 int checkboard(void)
409 {
410 puts("Board:\tTRATS\n");
411 return 0;
412 }
413 #endif
414
415 #ifdef CONFIG_GENERIC_MMC
416 int board_mmc_init(bd_t *bis)
417 {
418 struct exynos4_gpio_part2 *gpio =
419 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
420 int err;
421
422 /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */
423 s5p_gpio_direction_output(&gpio->k0, 2, 1);
424 s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE);
425
426 /*
427 * MMC device init
428 * mmc0 : eMMC (8-bit buswidth)
429 * mmc2 : SD card (4-bit buswidth)
430 */
431 err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
432 if (err)
433 debug("SDMMC0 not configured\n");
434 else
435 err = s5p_mmc_init(0, 8);
436
437 /* T-flash detect */
438 s5p_gpio_cfg_pin(&gpio->x3, 4, 0xf);
439 s5p_gpio_set_pull(&gpio->x3, 4, GPIO_PULL_UP);
440
441 /*
442 * Check the T-flash detect pin
443 * GPX3[4] T-flash detect pin
444 */
445 if (!s5p_gpio_get_value(&gpio->x3, 4)) {
446 err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
447 if (err)
448 debug("SDMMC2 not configured\n");
449 else
450 err = s5p_mmc_init(2, 4);
451 }
452
453 return err;
454 }
455 #endif
456
457 #ifdef CONFIG_USB_GADGET
458 static int s5pc210_phy_control(int on)
459 {
460 int ret = 0;
461 u32 val = 0;
462 struct pmic *p = pmic_get("MAX8997_PMIC");
463 if (!p)
464 return -ENODEV;
465
466 if (pmic_probe(p))
467 return -1;
468
469 if (on) {
470 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
471 ENSAFEOUT1, LDO_ON);
472 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
473 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO | val);
474
475 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
476 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO | val);
477 } else {
478 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
479 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO | val);
480
481 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
482 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO | val);
483 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
484 ENSAFEOUT1, LDO_OFF);
485 }
486
487 if (ret) {
488 puts("MAX8997 LDO setting error!\n");
489 return -1;
490 }
491
492 return 0;
493 }
494
495 struct s3c_plat_otg_data s5pc210_otg_data = {
496 .phy_control = s5pc210_phy_control,
497 .regs_phy = EXYNOS4_USBPHY_BASE,
498 .regs_otg = EXYNOS4_USBOTG_BASE,
499 .usb_phy_ctrl = EXYNOS4_USBPHY_CONTROL,
500 .usb_flags = PHY0_SLEEP,
501 };
502
503 int board_usb_init(int index, enum usb_init_type init)
504 {
505 debug("USB_udc_probe\n");
506 return s3c_udc_probe(&s5pc210_otg_data);
507 }
508
509 #ifdef CONFIG_USB_CABLE_CHECK
510 int usb_cable_connected(void)
511 {
512 struct pmic *muic = pmic_get("MAX8997_MUIC");
513 if (!muic)
514 return 0;
515
516 return !!muic->chrg->chrg_type(muic);
517 }
518 #endif
519 #endif
520
521 static void pmic_reset(void)
522 {
523 struct exynos4_gpio_part2 *gpio =
524 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
525
526 s5p_gpio_direction_output(&gpio->x0, 7, 1);
527 s5p_gpio_set_pull(&gpio->x2, 7, GPIO_PULL_NONE);
528 }
529
530 static void board_clock_init(void)
531 {
532 struct exynos4_clock *clk =
533 (struct exynos4_clock *)samsung_get_base_clock();
534
535 writel(CLK_SRC_CPU_VAL, (unsigned int)&clk->src_cpu);
536 writel(CLK_SRC_TOP0_VAL, (unsigned int)&clk->src_top0);
537 writel(CLK_SRC_FSYS_VAL, (unsigned int)&clk->src_fsys);
538 writel(CLK_SRC_PERIL0_VAL, (unsigned int)&clk->src_peril0);
539
540 writel(CLK_DIV_CPU0_VAL, (unsigned int)&clk->div_cpu0);
541 writel(CLK_DIV_CPU1_VAL, (unsigned int)&clk->div_cpu1);
542 writel(CLK_DIV_DMC0_VAL, (unsigned int)&clk->div_dmc0);
543 writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1);
544 writel(CLK_DIV_LEFTBUS_VAL, (unsigned int)&clk->div_leftbus);
545 writel(CLK_DIV_RIGHTBUS_VAL, (unsigned int)&clk->div_rightbus);
546 writel(CLK_DIV_TOP_VAL, (unsigned int)&clk->div_top);
547 writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1);
548 writel(CLK_DIV_FSYS2_VAL, (unsigned int)&clk->div_fsys2);
549 writel(CLK_DIV_FSYS3_VAL, (unsigned int)&clk->div_fsys3);
550 writel(CLK_DIV_PERIL0_VAL, (unsigned int)&clk->div_peril0);
551 writel(CLK_DIV_PERIL3_VAL, (unsigned int)&clk->div_peril3);
552
553 writel(PLL_LOCKTIME, (unsigned int)&clk->apll_lock);
554 writel(PLL_LOCKTIME, (unsigned int)&clk->mpll_lock);
555 writel(PLL_LOCKTIME, (unsigned int)&clk->epll_lock);
556 writel(PLL_LOCKTIME, (unsigned int)&clk->vpll_lock);
557 writel(APLL_CON1_VAL, (unsigned int)&clk->apll_con1);
558 writel(APLL_CON0_VAL, (unsigned int)&clk->apll_con0);
559 writel(MPLL_CON1_VAL, (unsigned int)&clk->mpll_con1);
560 writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0);
561 writel(EPLL_CON1_VAL, (unsigned int)&clk->epll_con1);
562 writel(EPLL_CON0_VAL, (unsigned int)&clk->epll_con0);
563 writel(VPLL_CON1_VAL, (unsigned int)&clk->vpll_con1);
564 writel(VPLL_CON0_VAL, (unsigned int)&clk->vpll_con0);
565
566 writel(CLK_GATE_IP_CAM_VAL, (unsigned int)&clk->gate_ip_cam);
567 writel(CLK_GATE_IP_VP_VAL, (unsigned int)&clk->gate_ip_tv);
568 writel(CLK_GATE_IP_MFC_VAL, (unsigned int)&clk->gate_ip_mfc);
569 writel(CLK_GATE_IP_G3D_VAL, (unsigned int)&clk->gate_ip_g3d);
570 writel(CLK_GATE_IP_IMAGE_VAL, (unsigned int)&clk->gate_ip_image);
571 writel(CLK_GATE_IP_LCD0_VAL, (unsigned int)&clk->gate_ip_lcd0);
572 writel(CLK_GATE_IP_LCD1_VAL, (unsigned int)&clk->gate_ip_lcd1);
573 writel(CLK_GATE_IP_FSYS_VAL, (unsigned int)&clk->gate_ip_fsys);
574 writel(CLK_GATE_IP_GPS_VAL, (unsigned int)&clk->gate_ip_gps);
575 writel(CLK_GATE_IP_PERIL_VAL, (unsigned int)&clk->gate_ip_peril);
576 writel(CLK_GATE_IP_PERIR_VAL, (unsigned int)&clk->gate_ip_perir);
577 writel(CLK_GATE_BLOCK_VAL, (unsigned int)&clk->gate_block);
578 }
579
580 static void board_power_init(void)
581 {
582 struct exynos4_power *pwr =
583 (struct exynos4_power *)samsung_get_base_power();
584
585 /* PS HOLD */
586 writel(EXYNOS4_PS_HOLD_CON_VAL, (unsigned int)&pwr->ps_hold_control);
587
588 /* Set power down */
589 writel(0, (unsigned int)&pwr->cam_configuration);
590 writel(0, (unsigned int)&pwr->tv_configuration);
591 writel(0, (unsigned int)&pwr->mfc_configuration);
592 writel(0, (unsigned int)&pwr->g3d_configuration);
593 writel(0, (unsigned int)&pwr->lcd1_configuration);
594 writel(0, (unsigned int)&pwr->gps_configuration);
595 writel(0, (unsigned int)&pwr->gps_alive_configuration);
596
597 /* It is necessary to power down core 1 */
598 /* to successfully boot CPU1 in kernel */
599 writel(0, (unsigned int)&pwr->arm_core1_configuration);
600 }
601
602 static void board_uart_init(void)
603 {
604 struct exynos4_gpio_part1 *gpio1 =
605 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
606 struct exynos4_gpio_part2 *gpio2 =
607 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
608 int i;
609
610 /*
611 * UART2 GPIOs
612 * GPA1CON[0] = UART_2_RXD(2)
613 * GPA1CON[1] = UART_2_TXD(2)
614 * GPA1CON[2] = I2C_3_SDA (3)
615 * GPA1CON[3] = I2C_3_SCL (3)
616 */
617
618 for (i = 0; i < 4; i++) {
619 s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE);
620 s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC((i > 1) ? 0x3 : 0x2));
621 }
622
623 /* UART_SEL GPY4[7] (part2) at EXYNOS4 */
624 s5p_gpio_set_pull(&gpio2->y4, 7, GPIO_PULL_UP);
625 s5p_gpio_direction_output(&gpio2->y4, 7, 1);
626 }
627
628 int board_early_init_f(void)
629 {
630 wdt_stop();
631 pmic_reset();
632 board_clock_init();
633 board_uart_init();
634 board_power_init();
635
636 return 0;
637 }
638
639 void exynos_reset_lcd(void)
640 {
641 struct exynos4_gpio_part2 *gpio2 =
642 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
643
644 s5p_gpio_direction_output(&gpio2->y4, 5, 1);
645 udelay(10000);
646 s5p_gpio_direction_output(&gpio2->y4, 5, 0);
647 udelay(10000);
648 s5p_gpio_direction_output(&gpio2->y4, 5, 1);
649 }
650
651 static int lcd_power(void)
652 {
653 int ret = 0;
654 struct pmic *p = pmic_get("MAX8997_PMIC");
655 if (!p)
656 return -ENODEV;
657
658 if (pmic_probe(p))
659 return 0;
660
661 /* LDO15 voltage: 2.2v */
662 ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, 0x1c | EN_LDO);
663 /* LDO13 voltage: 3.0v */
664 ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, 0x2c | EN_LDO);
665
666 if (ret) {
667 puts("MAX8997 LDO setting error!\n");
668 return -1;
669 }
670
671 return 0;
672 }
673
674 static struct mipi_dsim_config dsim_config = {
675 .e_interface = DSIM_VIDEO,
676 .e_virtual_ch = DSIM_VIRTUAL_CH_0,
677 .e_pixel_format = DSIM_24BPP_888,
678 .e_burst_mode = DSIM_BURST_SYNC_EVENT,
679 .e_no_data_lane = DSIM_DATA_LANE_4,
680 .e_byte_clk = DSIM_PLL_OUT_DIV8,
681 .hfp = 1,
682
683 .p = 3,
684 .m = 120,
685 .s = 1,
686
687 /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */
688 .pll_stable_time = 500,
689
690 /* escape clk : 10MHz */
691 .esc_clk = 20 * 1000000,
692
693 /* stop state holding counter after bta change count 0 ~ 0xfff */
694 .stop_holding_cnt = 0x7ff,
695 /* bta timeout 0 ~ 0xff */
696 .bta_timeout = 0xff,
697 /* lp rx timeout 0 ~ 0xffff */
698 .rx_timeout = 0xffff,
699 };
700
701 static struct exynos_platform_mipi_dsim s6e8ax0_platform_data = {
702 .lcd_panel_info = NULL,
703 .dsim_config = &dsim_config,
704 };
705
706 static struct mipi_dsim_lcd_device mipi_lcd_device = {
707 .name = "s6e8ax0",
708 .id = -1,
709 .bus_id = 0,
710 .platform_data = (void *)&s6e8ax0_platform_data,
711 };
712
713 static int mipi_power(void)
714 {
715 int ret = 0;
716 struct pmic *p = pmic_get("MAX8997_PMIC");
717 if (!p)
718 return -ENODEV;
719
720 if (pmic_probe(p))
721 return 0;
722
723 /* LDO3 voltage: 1.1v */
724 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, 0x6 | EN_LDO);
725 /* LDO4 voltage: 1.8v */
726 ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, 0x14 | EN_LDO);
727
728 if (ret) {
729 puts("MAX8997 LDO setting error!\n");
730 return -1;
731 }
732
733 return 0;
734 }
735
736 vidinfo_t panel_info = {
737 .vl_freq = 60,
738 .vl_col = 720,
739 .vl_row = 1280,
740 .vl_width = 720,
741 .vl_height = 1280,
742 .vl_clkp = CONFIG_SYS_HIGH,
743 .vl_hsp = CONFIG_SYS_LOW,
744 .vl_vsp = CONFIG_SYS_LOW,
745 .vl_dp = CONFIG_SYS_LOW,
746 .vl_bpix = 4, /* Bits per pixel, 2^4 = 16 */
747
748 /* s6e8ax0 Panel infomation */
749 .vl_hspw = 5,
750 .vl_hbpd = 10,
751 .vl_hfpd = 10,
752
753 .vl_vspw = 2,
754 .vl_vbpd = 1,
755 .vl_vfpd = 13,
756 .vl_cmd_allow_len = 0xf,
757
758 .win_id = 3,
759 .dual_lcd_enabled = 0,
760
761 .init_delay = 0,
762 .power_on_delay = 0,
763 .reset_delay = 0,
764 .interface_mode = FIMD_RGB_INTERFACE,
765 .mipi_enabled = 1,
766 };
767
768 void init_panel_info(vidinfo_t *vid)
769 {
770 vid->logo_on = 1,
771 vid->resolution = HD_RESOLUTION,
772 vid->rgb_mode = MODE_RGB_P,
773
774 #ifdef CONFIG_TIZEN
775 get_tizen_logo_info(vid);
776 #endif
777 mipi_lcd_device.reverse_panel = 1;
778
779 strcpy(s6e8ax0_platform_data.lcd_panel_name, mipi_lcd_device.name);
780 s6e8ax0_platform_data.lcd_power = lcd_power;
781 s6e8ax0_platform_data.mipi_power = mipi_power;
782 s6e8ax0_platform_data.phy_enable = set_mipi_phy_ctrl;
783 s6e8ax0_platform_data.lcd_panel_info = (void *)vid;
784 exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device);
785 s6e8ax0_init();
786 exynos_set_dsim_platform_data(&s6e8ax0_platform_data);
787
788 setenv("lcdinfo", "lcd=s6e8ax0");
789 }
790
791 #ifdef CONFIG_MISC_INIT_R
792 int misc_init_r(void)
793 {
794 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
795 set_board_info();
796 #endif
797 #ifdef CONFIG_LCD_MENU
798 keys_init();
799 check_boot_mode();
800 #endif
801 #ifdef CONFIG_CMD_BMP
802 if (panel_info.logo_on)
803 draw_logo();
804 #endif
805 return 0;
806 }
807 #endif
"Das U-Boot" Source Tree