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Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'
[people/ms/u-boot.git] / board / samsung / trats / trats.c
1 /*
2 * Copyright (C) 2011 Samsung Electronics
3 * Heungjun Kim <riverful.kim@samsung.com>
4 * Kyungmin Park <kyungmin.park@samsung.com>
5 * Donghwa Lee <dh09.lee@samsung.com>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10 #include <common.h>
11 #include <lcd.h>
12 #include <asm/io.h>
13 #include <asm/arch/cpu.h>
14 #include <asm/arch/gpio.h>
15 #include <asm/arch/mmc.h>
16 #include <asm/arch/pinmux.h>
17 #include <asm/arch/clock.h>
18 #include <asm/arch/clk.h>
19 #include <asm/arch/mipi_dsim.h>
20 #include <asm/arch/watchdog.h>
21 #include <asm/arch/power.h>
22 #include <power/pmic.h>
23 #include <usb/s3c_udc.h>
24 #include <power/max8997_pmic.h>
25 #include <libtizen.h>
26 #include <power/max8997_muic.h>
27 #include <power/battery.h>
28 #include <power/max17042_fg.h>
29 #include <usb_mass_storage.h>
30
31 #include "setup.h"
32
33 DECLARE_GLOBAL_DATA_PTR;
34
35 unsigned int board_rev;
36
37 #ifdef CONFIG_REVISION_TAG
38 u32 get_board_rev(void)
39 {
40 return board_rev;
41 }
42 #endif
43
44 static void check_hw_revision(void);
45 struct s3c_plat_otg_data s5pc210_otg_data;
46
47 int board_init(void)
48 {
49 gd->bd->bi_boot_params = CONFIG_SYS_SPL_ARGS_ADDR;
50
51 check_hw_revision();
52 printf("HW Revision:\t0x%x\n", board_rev);
53
54 return 0;
55 }
56
57 void i2c_init_board(void)
58 {
59 struct exynos4_gpio_part1 *gpio1 =
60 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
61 struct exynos4_gpio_part2 *gpio2 =
62 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
63
64 /* I2C_5 -> PMIC -> Adapter 0 */
65 s5p_gpio_direction_output(&gpio1->b, 7, 1);
66 s5p_gpio_direction_output(&gpio1->b, 6, 1);
67 /* I2C_9 -> FG -> Adapter 1 */
68 s5p_gpio_direction_output(&gpio2->y4, 0, 1);
69 s5p_gpio_direction_output(&gpio2->y4, 1, 1);
70 }
71
72 static void trats_low_power_mode(void)
73 {
74 struct exynos4_clock *clk =
75 (struct exynos4_clock *)samsung_get_base_clock();
76 struct exynos4_power *pwr =
77 (struct exynos4_power *)samsung_get_base_power();
78
79 /* Power down CORE1 */
80 /* LOCAL_PWR_CFG [1:0] 0x3 EN, 0x0 DIS */
81 writel(0x0, &pwr->arm_core1_configuration);
82
83 /* Change the APLL frequency */
84 /* ENABLE (1 enable) | LOCKED (1 locked) */
85 /* [31] | [29] */
86 /* FSEL | MDIV | PDIV | SDIV */
87 /* [27] | [25:16] | [13:8] | [2:0] */
88 writel(0xa0c80604, &clk->apll_con0);
89
90 /* Change CPU0 clock divider */
91 /* CORE2_RATIO | APLL_RATIO | PCLK_DBG_RATIO | ATB_RATIO */
92 /* [30:28] | [26:24] | [22:20] | [18:16] */
93 /* PERIPH_RATIO | COREM1_RATIO | COREM0_RATIO | CORE_RATIO */
94 /* [14:12] | [10:8] | [6:4] | [2:0] */
95 writel(0x00000100, &clk->div_cpu0);
96
97 /* CLK_DIV_STAT_CPU0 - wait until clock gets stable (0 = stable) */
98 while (readl(&clk->div_stat_cpu0) & 0x1111111)
99 continue;
100
101 /* Change clock divider ratio for DMC */
102 /* DMCP_RATIO | DMCD_RATIO */
103 /* [22:20] | [18:16] */
104 /* DMC_RATIO | DPHY_RATIO | ACP_PCLK_RATIO | ACP_RATIO */
105 /* [14:12] | [10:8] | [6:4] | [2:0] */
106 writel(0x13113117, &clk->div_dmc0);
107
108 /* CLK_DIV_STAT_DMC0 - wait until clock gets stable (0 = stable) */
109 while (readl(&clk->div_stat_dmc0) & 0x11111111)
110 continue;
111
112 /* Turn off unnecessary power domains */
113 writel(0x0, &pwr->xxti_configuration); /* XXTI */
114 writel(0x0, &pwr->cam_configuration); /* CAM */
115 writel(0x0, &pwr->tv_configuration); /* TV */
116 writel(0x0, &pwr->mfc_configuration); /* MFC */
117 writel(0x0, &pwr->g3d_configuration); /* G3D */
118 writel(0x0, &pwr->gps_configuration); /* GPS */
119 writel(0x0, &pwr->gps_alive_configuration); /* GPS_ALIVE */
120
121 /* Turn off unnecessary clocks */
122 writel(0x0, &clk->gate_ip_cam); /* CAM */
123 writel(0x0, &clk->gate_ip_tv); /* TV */
124 writel(0x0, &clk->gate_ip_mfc); /* MFC */
125 writel(0x0, &clk->gate_ip_g3d); /* G3D */
126 writel(0x0, &clk->gate_ip_image); /* IMAGE */
127 writel(0x0, &clk->gate_ip_gps); /* GPS */
128 }
129
130 static int pmic_init_max8997(void)
131 {
132 struct pmic *p = pmic_get("MAX8997_PMIC");
133 int i = 0, ret = 0;
134 u32 val;
135
136 if (pmic_probe(p))
137 return -1;
138
139 /* BUCK1 VARM: 1.2V */
140 val = (1200000 - 650000) / 25000;
141 ret |= pmic_reg_write(p, MAX8997_REG_BUCK1DVS1, val);
142 val = ENBUCK | ACTIVE_DISCHARGE; /* DVS OFF */
143 ret |= pmic_reg_write(p, MAX8997_REG_BUCK1CTRL, val);
144
145 /* BUCK2 VINT: 1.1V */
146 val = (1100000 - 650000) / 25000;
147 ret |= pmic_reg_write(p, MAX8997_REG_BUCK2DVS1, val);
148 val = ENBUCK | ACTIVE_DISCHARGE; /* DVS OFF */
149 ret |= pmic_reg_write(p, MAX8997_REG_BUCK2CTRL, val);
150
151
152 /* BUCK3 G3D: 1.1V - OFF */
153 ret |= pmic_reg_read(p, MAX8997_REG_BUCK3CTRL, &val);
154 val &= ~ENBUCK;
155 ret |= pmic_reg_write(p, MAX8997_REG_BUCK3CTRL, val);
156
157 val = (1100000 - 750000) / 50000;
158 ret |= pmic_reg_write(p, MAX8997_REG_BUCK3DVS, val);
159
160 /* BUCK4 CAMISP: 1.2V - OFF */
161 ret |= pmic_reg_read(p, MAX8997_REG_BUCK4CTRL, &val);
162 val &= ~ENBUCK;
163 ret |= pmic_reg_write(p, MAX8997_REG_BUCK4CTRL, val);
164
165 val = (1200000 - 650000) / 25000;
166 ret |= pmic_reg_write(p, MAX8997_REG_BUCK4DVS, val);
167
168 /* BUCK5 VMEM: 1.2V */
169 val = (1200000 - 650000) / 25000;
170 for (i = 0; i < 8; i++)
171 ret |= pmic_reg_write(p, MAX8997_REG_BUCK5DVS1 + i, val);
172
173 val = ENBUCK | ACTIVE_DISCHARGE; /* DVS OFF */
174 ret |= pmic_reg_write(p, MAX8997_REG_BUCK5CTRL, val);
175
176 /* BUCK6 CAM AF: 2.8V */
177 /* No Voltage Setting Register */
178 /* GNSLCT 3.0X */
179 val = GNSLCT;
180 ret |= pmic_reg_write(p, MAX8997_REG_BUCK6CTRL, val);
181
182 /* BUCK7 VCC_SUB: 2.0V */
183 val = (2000000 - 750000) / 50000;
184 ret |= pmic_reg_write(p, MAX8997_REG_BUCK7DVS, val);
185
186 /* LDO1 VADC: 3.3V */
187 val = max8997_reg_ldo(3300000) | DIS_LDO; /* OFF */
188 ret |= pmic_reg_write(p, MAX8997_REG_LDO1CTRL, val);
189
190 /* LDO1 Disable active discharging */
191 ret |= pmic_reg_read(p, MAX8997_REG_LDO1CONFIG, &val);
192 val &= ~LDO_ADE;
193 ret |= pmic_reg_write(p, MAX8997_REG_LDO1CONFIG, val);
194
195 /* LDO2 VALIVE: 1.1V */
196 val = max8997_reg_ldo(1100000) | EN_LDO;
197 ret |= pmic_reg_write(p, MAX8997_REG_LDO2CTRL, val);
198
199 /* LDO3 VUSB/MIPI: 1.1V */
200 val = max8997_reg_ldo(1100000) | DIS_LDO; /* OFF */
201 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, val);
202
203 /* LDO4 VMIPI: 1.8V */
204 val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */
205 ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, val);
206
207 /* LDO5 VHSIC: 1.2V */
208 val = max8997_reg_ldo(1200000) | DIS_LDO; /* OFF */
209 ret |= pmic_reg_write(p, MAX8997_REG_LDO5CTRL, val);
210
211 /* LDO6 VCC_1.8V_PDA: 1.8V */
212 val = max8997_reg_ldo(1800000) | EN_LDO;
213 ret |= pmic_reg_write(p, MAX8997_REG_LDO6CTRL, val);
214
215 /* LDO7 CAM_ISP: 1.8V */
216 val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */
217 ret |= pmic_reg_write(p, MAX8997_REG_LDO7CTRL, val);
218
219 /* LDO8 VDAC/VUSB: 3.3V */
220 val = max8997_reg_ldo(3300000) | DIS_LDO; /* OFF */
221 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, val);
222
223 /* LDO9 VCC_2.8V_PDA: 2.8V */
224 val = max8997_reg_ldo(2800000) | EN_LDO;
225 ret |= pmic_reg_write(p, MAX8997_REG_LDO9CTRL, val);
226
227 /* LDO10 VPLL: 1.1V */
228 val = max8997_reg_ldo(1100000) | EN_LDO;
229 ret |= pmic_reg_write(p, MAX8997_REG_LDO10CTRL, val);
230
231 /* LDO11 TOUCH: 2.8V */
232 val = max8997_reg_ldo(2800000) | DIS_LDO; /* OFF */
233 ret |= pmic_reg_write(p, MAX8997_REG_LDO11CTRL, val);
234
235 /* LDO12 VTCAM: 1.8V */
236 val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */
237 ret |= pmic_reg_write(p, MAX8997_REG_LDO12CTRL, val);
238
239 /* LDO13 VCC_3.0_LCD: 3.0V */
240 val = max8997_reg_ldo(3000000) | DIS_LDO; /* OFF */
241 ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, val);
242
243 /* LDO14 MOTOR: 3.0V */
244 val = max8997_reg_ldo(3000000) | DIS_LDO; /* OFF */
245 ret |= pmic_reg_write(p, MAX8997_REG_LDO14CTRL, val);
246
247 /* LDO15 LED_A: 2.8V */
248 val = max8997_reg_ldo(2800000) | DIS_LDO; /* OFF */
249 ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, val);
250
251 /* LDO16 CAM_SENSOR: 1.8V */
252 val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */
253 ret |= pmic_reg_write(p, MAX8997_REG_LDO16CTRL, val);
254
255 /* LDO17 VTF: 2.8V */
256 val = max8997_reg_ldo(2800000) | DIS_LDO; /* OFF */
257 ret |= pmic_reg_write(p, MAX8997_REG_LDO17CTRL, val);
258
259 /* LDO18 TOUCH_LED 3.3V */
260 val = max8997_reg_ldo(3300000) | DIS_LDO; /* OFF */
261 ret |= pmic_reg_write(p, MAX8997_REG_LDO18CTRL, val);
262
263 /* LDO21 VDDQ: 1.2V */
264 val = max8997_reg_ldo(1200000) | EN_LDO;
265 ret |= pmic_reg_write(p, MAX8997_REG_LDO21CTRL, val);
266
267 /* SAFEOUT for both 1 and 2: 4.9V, Active discharge, Enable */
268 val = (SAFEOUT_4_90V << 0) | (SAFEOUT_4_90V << 2) |
269 ACTDISSAFEO1 | ACTDISSAFEO2 | ENSAFEOUT1 | ENSAFEOUT2;
270 ret |= pmic_reg_write(p, MAX8997_REG_SAFEOUTCTRL, val);
271
272 if (ret) {
273 puts("MAX8997 PMIC setting error!\n");
274 return -1;
275 }
276 return 0;
277 }
278
279 int power_init_board(void)
280 {
281 int chrg, ret;
282 struct power_battery *pb;
283 struct pmic *p_fg, *p_chrg, *p_muic, *p_bat;
284
285 /*
286 * For PMIC/MUIC the I2C bus is named as I2C5, but it is connected
287 * to logical I2C adapter 0
288 *
289 * The FUEL_GAUGE is marked as I2C9 on the schematic, but connected
290 * to logical I2C adapter 1
291 */
292 ret = pmic_init(I2C_0);
293 ret |= pmic_init_max8997();
294 ret |= power_fg_init(I2C_1);
295 ret |= power_muic_init(I2C_0);
296 ret |= power_bat_init(0);
297 if (ret)
298 return ret;
299
300 p_fg = pmic_get("MAX17042_FG");
301 if (!p_fg) {
302 puts("MAX17042_FG: Not found\n");
303 return -ENODEV;
304 }
305
306 p_chrg = pmic_get("MAX8997_PMIC");
307 if (!p_chrg) {
308 puts("MAX8997_PMIC: Not found\n");
309 return -ENODEV;
310 }
311
312 p_muic = pmic_get("MAX8997_MUIC");
313 if (!p_muic) {
314 puts("MAX8997_MUIC: Not found\n");
315 return -ENODEV;
316 }
317
318 p_bat = pmic_get("BAT_TRATS");
319 if (!p_bat) {
320 puts("BAT_TRATS: Not found\n");
321 return -ENODEV;
322 }
323
324 p_fg->parent = p_bat;
325 p_chrg->parent = p_bat;
326 p_muic->parent = p_bat;
327
328 p_bat->low_power_mode = trats_low_power_mode;
329 p_bat->pbat->battery_init(p_bat, p_fg, p_chrg, p_muic);
330
331 pb = p_bat->pbat;
332 chrg = p_muic->chrg->chrg_type(p_muic);
333 debug("CHARGER TYPE: %d\n", chrg);
334
335 if (!p_chrg->chrg->chrg_bat_present(p_chrg)) {
336 puts("No battery detected\n");
337 return -1;
338 }
339
340 p_fg->fg->fg_battery_check(p_fg, p_bat);
341
342 if (pb->bat->state == CHARGE && chrg == CHARGER_USB)
343 puts("CHARGE Battery !\n");
344
345 return 0;
346 }
347
348 int dram_init(void)
349 {
350 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
351 get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) +
352 get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) +
353 get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE);
354
355 return 0;
356 }
357
358 void dram_init_banksize(void)
359 {
360 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
361 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
362 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
363 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
364 gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
365 gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
366 gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
367 gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
368 }
369
370 static unsigned int get_hw_revision(void)
371 {
372 struct exynos4_gpio_part1 *gpio =
373 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
374 int hwrev = 0;
375 int i;
376
377 /* hw_rev[3:0] == GPE1[3:0] */
378 for (i = 0; i < 4; i++) {
379 s5p_gpio_cfg_pin(&gpio->e1, i, GPIO_INPUT);
380 s5p_gpio_set_pull(&gpio->e1, i, GPIO_PULL_NONE);
381 }
382
383 udelay(1);
384
385 for (i = 0; i < 4; i++)
386 hwrev |= (s5p_gpio_get_value(&gpio->e1, i) << i);
387
388 debug("hwrev 0x%x\n", hwrev);
389
390 return hwrev;
391 }
392
393 static void check_hw_revision(void)
394 {
395 int hwrev;
396
397 hwrev = get_hw_revision();
398
399 board_rev |= hwrev;
400 }
401
402 #ifdef CONFIG_DISPLAY_BOARDINFO
403 int checkboard(void)
404 {
405 puts("Board:\tTRATS\n");
406 return 0;
407 }
408 #endif
409
410 #ifdef CONFIG_GENERIC_MMC
411 int board_mmc_init(bd_t *bis)
412 {
413 struct exynos4_gpio_part2 *gpio =
414 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
415 int err;
416
417 /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */
418 s5p_gpio_direction_output(&gpio->k0, 2, 1);
419 s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE);
420
421 /*
422 * MMC device init
423 * mmc0 : eMMC (8-bit buswidth)
424 * mmc2 : SD card (4-bit buswidth)
425 */
426 err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
427 if (err)
428 debug("SDMMC0 not configured\n");
429 else
430 err = s5p_mmc_init(0, 8);
431
432 /* T-flash detect */
433 s5p_gpio_cfg_pin(&gpio->x3, 4, 0xf);
434 s5p_gpio_set_pull(&gpio->x3, 4, GPIO_PULL_UP);
435
436 /*
437 * Check the T-flash detect pin
438 * GPX3[4] T-flash detect pin
439 */
440 if (!s5p_gpio_get_value(&gpio->x3, 4)) {
441 err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
442 if (err)
443 debug("SDMMC2 not configured\n");
444 else
445 err = s5p_mmc_init(2, 4);
446 }
447
448 return err;
449 }
450 #endif
451
452 #ifdef CONFIG_USB_GADGET
453 static int s5pc210_phy_control(int on)
454 {
455 int ret = 0;
456 u32 val = 0;
457 struct pmic *p = pmic_get("MAX8997_PMIC");
458 if (!p)
459 return -ENODEV;
460
461 if (pmic_probe(p))
462 return -1;
463
464 if (on) {
465 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
466 ENSAFEOUT1, LDO_ON);
467 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
468 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO | val);
469
470 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
471 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO | val);
472 } else {
473 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
474 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO | val);
475
476 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
477 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO | val);
478 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
479 ENSAFEOUT1, LDO_OFF);
480 }
481
482 if (ret) {
483 puts("MAX8997 LDO setting error!\n");
484 return -1;
485 }
486
487 return 0;
488 }
489
490 struct s3c_plat_otg_data s5pc210_otg_data = {
491 .phy_control = s5pc210_phy_control,
492 .regs_phy = EXYNOS4_USBPHY_BASE,
493 .regs_otg = EXYNOS4_USBOTG_BASE,
494 .usb_phy_ctrl = EXYNOS4_USBPHY_CONTROL,
495 .usb_flags = PHY0_SLEEP,
496 };
497
498 void board_usb_init(void)
499 {
500 debug("USB_udc_probe\n");
501 s3c_udc_probe(&s5pc210_otg_data);
502 }
503 #endif
504
505 static void pmic_reset(void)
506 {
507 struct exynos4_gpio_part2 *gpio =
508 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
509
510 s5p_gpio_direction_output(&gpio->x0, 7, 1);
511 s5p_gpio_set_pull(&gpio->x2, 7, GPIO_PULL_NONE);
512 }
513
514 static void board_clock_init(void)
515 {
516 struct exynos4_clock *clk =
517 (struct exynos4_clock *)samsung_get_base_clock();
518
519 writel(CLK_SRC_CPU_VAL, (unsigned int)&clk->src_cpu);
520 writel(CLK_SRC_TOP0_VAL, (unsigned int)&clk->src_top0);
521 writel(CLK_SRC_FSYS_VAL, (unsigned int)&clk->src_fsys);
522 writel(CLK_SRC_PERIL0_VAL, (unsigned int)&clk->src_peril0);
523
524 writel(CLK_DIV_CPU0_VAL, (unsigned int)&clk->div_cpu0);
525 writel(CLK_DIV_CPU1_VAL, (unsigned int)&clk->div_cpu1);
526 writel(CLK_DIV_DMC0_VAL, (unsigned int)&clk->div_dmc0);
527 writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1);
528 writel(CLK_DIV_LEFTBUS_VAL, (unsigned int)&clk->div_leftbus);
529 writel(CLK_DIV_RIGHTBUS_VAL, (unsigned int)&clk->div_rightbus);
530 writel(CLK_DIV_TOP_VAL, (unsigned int)&clk->div_top);
531 writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1);
532 writel(CLK_DIV_FSYS2_VAL, (unsigned int)&clk->div_fsys2);
533 writel(CLK_DIV_FSYS3_VAL, (unsigned int)&clk->div_fsys3);
534 writel(CLK_DIV_PERIL0_VAL, (unsigned int)&clk->div_peril0);
535 writel(CLK_DIV_PERIL3_VAL, (unsigned int)&clk->div_peril3);
536
537 writel(PLL_LOCKTIME, (unsigned int)&clk->apll_lock);
538 writel(PLL_LOCKTIME, (unsigned int)&clk->mpll_lock);
539 writel(PLL_LOCKTIME, (unsigned int)&clk->epll_lock);
540 writel(PLL_LOCKTIME, (unsigned int)&clk->vpll_lock);
541 writel(APLL_CON1_VAL, (unsigned int)&clk->apll_con1);
542 writel(APLL_CON0_VAL, (unsigned int)&clk->apll_con0);
543 writel(MPLL_CON1_VAL, (unsigned int)&clk->mpll_con1);
544 writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0);
545 writel(EPLL_CON1_VAL, (unsigned int)&clk->epll_con1);
546 writel(EPLL_CON0_VAL, (unsigned int)&clk->epll_con0);
547 writel(VPLL_CON1_VAL, (unsigned int)&clk->vpll_con1);
548 writel(VPLL_CON0_VAL, (unsigned int)&clk->vpll_con0);
549
550 writel(CLK_GATE_IP_CAM_VAL, (unsigned int)&clk->gate_ip_cam);
551 writel(CLK_GATE_IP_VP_VAL, (unsigned int)&clk->gate_ip_tv);
552 writel(CLK_GATE_IP_MFC_VAL, (unsigned int)&clk->gate_ip_mfc);
553 writel(CLK_GATE_IP_G3D_VAL, (unsigned int)&clk->gate_ip_g3d);
554 writel(CLK_GATE_IP_IMAGE_VAL, (unsigned int)&clk->gate_ip_image);
555 writel(CLK_GATE_IP_LCD0_VAL, (unsigned int)&clk->gate_ip_lcd0);
556 writel(CLK_GATE_IP_LCD1_VAL, (unsigned int)&clk->gate_ip_lcd1);
557 writel(CLK_GATE_IP_FSYS_VAL, (unsigned int)&clk->gate_ip_fsys);
558 writel(CLK_GATE_IP_GPS_VAL, (unsigned int)&clk->gate_ip_gps);
559 writel(CLK_GATE_IP_PERIL_VAL, (unsigned int)&clk->gate_ip_peril);
560 writel(CLK_GATE_IP_PERIR_VAL, (unsigned int)&clk->gate_ip_perir);
561 writel(CLK_GATE_BLOCK_VAL, (unsigned int)&clk->gate_block);
562 }
563
564 static void board_power_init(void)
565 {
566 struct exynos4_power *pwr =
567 (struct exynos4_power *)samsung_get_base_power();
568
569 /* PS HOLD */
570 writel(EXYNOS4_PS_HOLD_CON_VAL, (unsigned int)&pwr->ps_hold_control);
571
572 /* Set power down */
573 writel(0, (unsigned int)&pwr->cam_configuration);
574 writel(0, (unsigned int)&pwr->tv_configuration);
575 writel(0, (unsigned int)&pwr->mfc_configuration);
576 writel(0, (unsigned int)&pwr->g3d_configuration);
577 writel(0, (unsigned int)&pwr->lcd1_configuration);
578 writel(0, (unsigned int)&pwr->gps_configuration);
579 writel(0, (unsigned int)&pwr->gps_alive_configuration);
580
581 /* It is necessary to power down core 1 */
582 /* to successfully boot CPU1 in kernel */
583 writel(0, (unsigned int)&pwr->arm_core1_configuration);
584 }
585
586 static void board_uart_init(void)
587 {
588 struct exynos4_gpio_part1 *gpio1 =
589 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
590 struct exynos4_gpio_part2 *gpio2 =
591 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
592 int i;
593
594 /*
595 * UART2 GPIOs
596 * GPA1CON[0] = UART_2_RXD(2)
597 * GPA1CON[1] = UART_2_TXD(2)
598 * GPA1CON[2] = I2C_3_SDA (3)
599 * GPA1CON[3] = I2C_3_SCL (3)
600 */
601
602 for (i = 0; i < 4; i++) {
603 s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE);
604 s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC((i > 1) ? 0x3 : 0x2));
605 }
606
607 /* UART_SEL GPY4[7] (part2) at EXYNOS4 */
608 s5p_gpio_set_pull(&gpio2->y4, 7, GPIO_PULL_UP);
609 s5p_gpio_direction_output(&gpio2->y4, 7, 1);
610 }
611
612 int board_early_init_f(void)
613 {
614 wdt_stop();
615 pmic_reset();
616 board_clock_init();
617 board_uart_init();
618 board_power_init();
619
620 return 0;
621 }
622
623 void exynos_reset_lcd(void)
624 {
625 struct exynos4_gpio_part2 *gpio2 =
626 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
627
628 s5p_gpio_direction_output(&gpio2->y4, 5, 1);
629 udelay(10000);
630 s5p_gpio_direction_output(&gpio2->y4, 5, 0);
631 udelay(10000);
632 s5p_gpio_direction_output(&gpio2->y4, 5, 1);
633 }
634
635 static int lcd_power(void)
636 {
637 int ret = 0;
638 struct pmic *p = pmic_get("MAX8997_PMIC");
639 if (!p)
640 return -ENODEV;
641
642 if (pmic_probe(p))
643 return 0;
644
645 /* LDO15 voltage: 2.2v */
646 ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, 0x1c | EN_LDO);
647 /* LDO13 voltage: 3.0v */
648 ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, 0x2c | EN_LDO);
649
650 if (ret) {
651 puts("MAX8997 LDO setting error!\n");
652 return -1;
653 }
654
655 return 0;
656 }
657
658 static struct mipi_dsim_config dsim_config = {
659 .e_interface = DSIM_VIDEO,
660 .e_virtual_ch = DSIM_VIRTUAL_CH_0,
661 .e_pixel_format = DSIM_24BPP_888,
662 .e_burst_mode = DSIM_BURST_SYNC_EVENT,
663 .e_no_data_lane = DSIM_DATA_LANE_4,
664 .e_byte_clk = DSIM_PLL_OUT_DIV8,
665 .hfp = 1,
666
667 .p = 3,
668 .m = 120,
669 .s = 1,
670
671 /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */
672 .pll_stable_time = 500,
673
674 /* escape clk : 10MHz */
675 .esc_clk = 20 * 1000000,
676
677 /* stop state holding counter after bta change count 0 ~ 0xfff */
678 .stop_holding_cnt = 0x7ff,
679 /* bta timeout 0 ~ 0xff */
680 .bta_timeout = 0xff,
681 /* lp rx timeout 0 ~ 0xffff */
682 .rx_timeout = 0xffff,
683 };
684
685 static struct exynos_platform_mipi_dsim s6e8ax0_platform_data = {
686 .lcd_panel_info = NULL,
687 .dsim_config = &dsim_config,
688 };
689
690 static struct mipi_dsim_lcd_device mipi_lcd_device = {
691 .name = "s6e8ax0",
692 .id = -1,
693 .bus_id = 0,
694 .platform_data = (void *)&s6e8ax0_platform_data,
695 };
696
697 static int mipi_power(void)
698 {
699 int ret = 0;
700 struct pmic *p = pmic_get("MAX8997_PMIC");
701 if (!p)
702 return -ENODEV;
703
704 if (pmic_probe(p))
705 return 0;
706
707 /* LDO3 voltage: 1.1v */
708 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, 0x6 | EN_LDO);
709 /* LDO4 voltage: 1.8v */
710 ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, 0x14 | EN_LDO);
711
712 if (ret) {
713 puts("MAX8997 LDO setting error!\n");
714 return -1;
715 }
716
717 return 0;
718 }
719
720 vidinfo_t panel_info = {
721 .vl_freq = 60,
722 .vl_col = 720,
723 .vl_row = 1280,
724 .vl_width = 720,
725 .vl_height = 1280,
726 .vl_clkp = CONFIG_SYS_HIGH,
727 .vl_hsp = CONFIG_SYS_LOW,
728 .vl_vsp = CONFIG_SYS_LOW,
729 .vl_dp = CONFIG_SYS_LOW,
730 .vl_bpix = 5, /* Bits per pixel, 2^5 = 32 */
731
732 /* s6e8ax0 Panel infomation */
733 .vl_hspw = 5,
734 .vl_hbpd = 10,
735 .vl_hfpd = 10,
736
737 .vl_vspw = 2,
738 .vl_vbpd = 1,
739 .vl_vfpd = 13,
740 .vl_cmd_allow_len = 0xf,
741
742 .win_id = 3,
743 .dual_lcd_enabled = 0,
744
745 .init_delay = 0,
746 .power_on_delay = 0,
747 .reset_delay = 0,
748 .interface_mode = FIMD_RGB_INTERFACE,
749 .mipi_enabled = 1,
750 };
751
752 void init_panel_info(vidinfo_t *vid)
753 {
754 vid->logo_on = 1,
755 vid->resolution = HD_RESOLUTION,
756 vid->rgb_mode = MODE_RGB_P,
757
758 #ifdef CONFIG_TIZEN
759 get_tizen_logo_info(vid);
760 #endif
761 mipi_lcd_device.reverse_panel = 1;
762
763 strcpy(s6e8ax0_platform_data.lcd_panel_name, mipi_lcd_device.name);
764 s6e8ax0_platform_data.lcd_power = lcd_power;
765 s6e8ax0_platform_data.mipi_power = mipi_power;
766 s6e8ax0_platform_data.phy_enable = set_mipi_phy_ctrl;
767 s6e8ax0_platform_data.lcd_panel_info = (void *)vid;
768 exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device);
769 s6e8ax0_init();
770 exynos_set_dsim_platform_data(&s6e8ax0_platform_data);
771
772 setenv("lcdinfo", "lcd=s6e8ax0");
773 }
774
775 #ifdef CONFIG_USB_GADGET_MASS_STORAGE
776 static int ums_read_sector(struct ums_device *ums_dev,
777 ulong start, lbaint_t blkcnt, void *buf)
778 {
779 if (ums_dev->mmc->block_dev.block_read(ums_dev->dev_num,
780 start + ums_dev->offset, blkcnt, buf) != blkcnt)
781 return -1;
782
783 return 0;
784 }
785
786 static int ums_write_sector(struct ums_device *ums_dev,
787 ulong start, lbaint_t blkcnt, const void *buf)
788 {
789 if (ums_dev->mmc->block_dev.block_write(ums_dev->dev_num,
790 start + ums_dev->offset, blkcnt, buf) != blkcnt)
791 return -1;
792
793 return 0;
794 }
795
796 static void ums_get_capacity(struct ums_device *ums_dev,
797 long long int *capacity)
798 {
799 long long int tmp_capacity;
800
801 tmp_capacity = (long long int) ((ums_dev->offset + ums_dev->part_size)
802 * SECTOR_SIZE);
803 *capacity = ums_dev->mmc->capacity - tmp_capacity;
804 }
805
806 static struct ums_board_info ums_board = {
807 .read_sector = ums_read_sector,
808 .write_sector = ums_write_sector,
809 .get_capacity = ums_get_capacity,
810 .name = "TRATS UMS disk",
811 .ums_dev = {
812 .mmc = NULL,
813 .dev_num = 0,
814 .offset = 0,
815 .part_size = 0.
816 },
817 };
818
819 struct ums_board_info *board_ums_init(unsigned int dev_num, unsigned int offset,
820 unsigned int part_size)
821 {
822 struct mmc *mmc;
823
824 mmc = find_mmc_device(dev_num);
825 if (!mmc)
826 return NULL;
827
828 ums_board.ums_dev.mmc = mmc;
829 ums_board.ums_dev.dev_num = dev_num;
830 ums_board.ums_dev.offset = offset;
831 ums_board.ums_dev.part_size = part_size;
832
833 return &ums_board;
834 }
835 #endif
"Das U-Boot" Source Tree