board/socrates/sdram.c

   1 /*
   2  * (C) Copyright 2008
   3  * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/processor.h>
  10 #include <asm/immap_85xx.h>
  11 #include <fsl_ddr_sdram.h>
  12 #include <asm/processor.h>
  13 #include <asm/mmu.h>
  14 #include <spd_sdram.h>
  15
  16
  17 #if !defined(CONFIG_SPD_EEPROM)
  18 /*
  19  * Autodetect onboard DDR SDRAM on 85xx platforms
  20  *
  21  * NOTE: Some of the hardcoded values are hardware dependant,
  22  *       so this should be extended for other future boards
  23  *       using this routine!
  24  */
  25 phys_size_t fixed_sdram(void)
  26 {
  27         volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_FSL_DDR_ADDR);
  28
  29         /*
  30          * Disable memory controller.
  31          */
  32         ddr->cs0_config = 0;
  33         ddr->sdram_cfg = 0;
  34
  35         ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
  36         ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
  37         ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
  38         ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
  39         ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
  40         ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
  41         ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
  42         ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONFIG_2;
  43         ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CONTROL;
  44
  45         asm ("sync;isync;msync");
  46         udelay(1000);
  47
  48         ddr->sdram_cfg = CONFIG_SYS_DDR_CONFIG;
  49         asm ("sync; isync; msync");
  50         udelay(1000);
  51
  52         if (get_ram_size(0, CONFIG_SYS_SDRAM_SIZE<<20) == CONFIG_SYS_SDRAM_SIZE<<20) {
  53                 /*
  54                  * OK, size detected -> all done
  55                  */
  56                 return CONFIG_SYS_SDRAM_SIZE<<20;
  57         }
  58
  59         return 0;                               /* nothing found !              */
  60 }
  61 #endif
  62
  63 #if defined(CONFIG_SYS_DRAM_TEST)
  64 int testdram (void)
  65 {
  66         uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
  67         uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
  68         uint *p;
  69
  70         printf ("SDRAM test phase 1:\n");
  71         for (p = pstart; p < pend; p++)
  72                 *p = 0xaaaaaaaa;
  73
  74         for (p = pstart; p < pend; p++) {
  75                 if (*p != 0xaaaaaaaa) {
  76                         printf ("SDRAM test fails at: %08x\n", (uint) p);
  77                         return 1;
  78                 }
  79         }
  80
  81         printf ("SDRAM test phase 2:\n");
  82         for (p = pstart; p < pend; p++)
  83                 *p = 0x55555555;
  84
  85         for (p = pstart; p < pend; p++) {
  86                 if (*p != 0x55555555) {
  87                         printf ("SDRAM test fails at: %08x\n", (uint) p);
  88                         return 1;
  89                 }
  90         }
  91
  92         printf ("SDRAM test passed.\n");
  93         return 0;
  94 }
  95 #endif