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1 /*
2 * (C) Copyright 2000, 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 /*
9 * Support for read and write access to EEPROM like memory devices. This
10 * includes regular EEPROM as well as FRAM (ferroelectic nonvolaile RAM).
11 * FRAM devices read and write data at bus speed. In particular, there is no
12 * write delay. Also, there is no limit imposed on the number of bytes that can
13 * be transferred with a single read or write.
14 *
15 * Use the following configuration options to ensure no unneeded performance
16 * degradation (typical for EEPROM) is incured for FRAM memory:
17 *
18 * #define CONFIG_SYS_I2C_FRAM
19 * #undef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS
20 *
21 */
22
23 #include <common.h>
24 #include <config.h>
25 #include <command.h>
26 #include <i2c.h>
27
28 #ifndef CONFIG_SYS_I2C_SPEED
29 #define CONFIG_SYS_I2C_SPEED 50000
30 #endif
31
32 /* Maximum number of times to poll for acknowledge after write */
33 #if defined(CONFIG_SYS_EEPROM_X40430)
34 #define MAX_ACKNOWLEDGE_POLLS 10
35 #endif
36
37 /*
38 * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is
39 * 0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM.
40 *
41 * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is
42 * 0x00000nxx for EEPROM address selectors and page number at n.
43 */
44 #if !defined(CONFIG_SPI) || defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
45 #if !defined(CONFIG_SYS_I2C_EEPROM_ADDR_LEN) || \
46 (CONFIG_SYS_I2C_EEPROM_ADDR_LEN < 1) || \
47 (CONFIG_SYS_I2C_EEPROM_ADDR_LEN > 2)
48 #error CONFIG_SYS_I2C_EEPROM_ADDR_LEN must be 1 or 2
49 #endif
50 #endif
51
52 #if defined(CONFIG_SYS_EEPROM_WREN)
53 extern int eeprom_write_enable (unsigned dev_addr, int state);
54 #endif
55
56 void eeprom_init(void)
57 {
58 /* SPI EEPROM */
59 #if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
60 spi_init_f ();
61 #endif
62
63 /* I2C EEPROM */
64 #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT)
65 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
66 #endif
67 }
68
69 int eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt)
70 {
71 unsigned end = offset + cnt;
72 unsigned blk_off;
73 int rcode = 0;
74
75 /*
76 * Read data until done or would cross a page boundary.
77 * We must write the address again when changing pages
78 * because the next page may be in a different device.
79 */
80 while (offset < end) {
81 unsigned alen, len;
82 #if !defined(CONFIG_SYS_I2C_FRAM)
83 unsigned maxlen;
84 #endif
85
86 #if CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
87 uchar addr[2];
88
89 blk_off = offset & 0xFF; /* block offset */
90
91 addr[0] = offset >> 8; /* block number */
92 addr[1] = blk_off; /* block offset */
93 alen = 2;
94 #else
95 uchar addr[3];
96
97 blk_off = offset & 0xFF; /* block offset */
98
99 addr[0] = offset >> 16; /* block number */
100 addr[1] = offset >> 8; /* upper address octet */
101 addr[2] = blk_off; /* lower address octet */
102 alen = 3;
103 #endif /* CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */
104
105 addr[0] |= dev_addr; /* insert device address */
106
107 len = end - offset;
108
109 /*
110 * For a FRAM device there is no limit on the number of the
111 * bytes that can be ccessed with the single read or write
112 * operation.
113 */
114 #if !defined(CONFIG_SYS_I2C_FRAM)
115 maxlen = 0x100 - blk_off;
116 if (maxlen > I2C_RXTX_LEN)
117 maxlen = I2C_RXTX_LEN;
118 if (len > maxlen)
119 len = maxlen;
120 #endif
121
122 #if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
123 spi_read (addr, alen, buffer, len);
124 #else
125 #if defined(CONFIG_SYS_I2C_EEPROM_BUS)
126 i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS);
127 #endif
128 if (i2c_read(addr[0], offset, alen - 1, buffer, len))
129 rcode = 1;
130 #endif
131 buffer += len;
132 offset += len;
133 }
134
135 return rcode;
136 }
137
138 int eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt)
139 {
140 unsigned end = offset + cnt;
141 unsigned blk_off;
142 int rcode = 0;
143
144 #if defined(CONFIG_SYS_EEPROM_X40430)
145 uchar contr_r_addr[2];
146 uchar addr_void[2];
147 uchar contr_reg[2];
148 uchar ctrl_reg_v;
149 int i;
150 #endif
151
152 #if defined(CONFIG_SYS_EEPROM_WREN)
153 eeprom_write_enable (dev_addr,1);
154 #endif
155 /*
156 * Write data until done or would cross a write page boundary.
157 * We must write the address again when changing pages
158 * because the address counter only increments within a page.
159 */
160
161 while (offset < end) {
162 unsigned alen, len;
163 #if !defined(CONFIG_SYS_I2C_FRAM)
164 unsigned maxlen;
165 #endif
166
167 #if CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
168 uchar addr[2];
169
170 blk_off = offset & 0xFF; /* block offset */
171
172 addr[0] = offset >> 8; /* block number */
173 addr[1] = blk_off; /* block offset */
174 alen = 2;
175 #else
176 uchar addr[3];
177
178 blk_off = offset & 0xFF; /* block offset */
179
180 addr[0] = offset >> 16; /* block number */
181 addr[1] = offset >> 8; /* upper address octet */
182 addr[2] = blk_off; /* lower address octet */
183 alen = 3;
184 #endif /* CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */
185
186 addr[0] |= dev_addr; /* insert device address */
187
188 len = end - offset;
189
190 /*
191 * For a FRAM device there is no limit on the number of the
192 * bytes that can be accessed with the single read or write
193 * operation.
194 */
195 #if !defined(CONFIG_SYS_I2C_FRAM)
196
197 #if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_BITS)
198
199 #define EEPROM_PAGE_SIZE (1 << CONFIG_SYS_EEPROM_PAGE_WRITE_BITS)
200 #define EEPROM_PAGE_OFFSET(x) ((x) & (EEPROM_PAGE_SIZE - 1))
201
202 maxlen = EEPROM_PAGE_SIZE - EEPROM_PAGE_OFFSET(blk_off);
203 #else
204 maxlen = 0x100 - blk_off;
205 #endif
206 if (maxlen > I2C_RXTX_LEN)
207 maxlen = I2C_RXTX_LEN;
208
209 if (len > maxlen)
210 len = maxlen;
211 #endif
212
213 #if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
214 spi_write (addr, alen, buffer, len);
215 #else
216 #if defined(CONFIG_SYS_EEPROM_X40430)
217 /* Get the value of the control register.
218 * Set current address (internal pointer in the x40430)
219 * to 0x1ff.
220 */
221 contr_r_addr[0] = 9;
222 contr_r_addr[1] = 0xff;
223 addr_void[0] = 0;
224 addr_void[1] = addr[1];
225 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR
226 contr_r_addr[0] |= CONFIG_SYS_I2C_EEPROM_ADDR;
227 addr_void[0] |= CONFIG_SYS_I2C_EEPROM_ADDR;
228 #endif
229 contr_reg[0] = 0xff;
230 if (i2c_read (contr_r_addr[0], contr_r_addr[1], 1, contr_reg, 1) != 0) {
231 rcode = 1;
232 }
233 ctrl_reg_v = contr_reg[0];
234
235 /* Are any of the eeprom blocks write protected?
236 */
237 if (ctrl_reg_v & 0x18) {
238 ctrl_reg_v &= ~0x18; /* reset block protect bits */
239 ctrl_reg_v |= 0x02; /* set write enable latch */
240 ctrl_reg_v &= ~0x04; /* clear RWEL */
241
242 /* Set write enable latch.
243 */
244 contr_reg[0] = 0x02;
245 if (i2c_write (contr_r_addr[0], 0xff, 1, contr_reg, 1) != 0) {
246 rcode = 1;
247 }
248
249 /* Set register write enable latch.
250 */
251 contr_reg[0] = 0x06;
252 if (i2c_write (contr_r_addr[0], 0xFF, 1, contr_reg, 1) != 0) {
253 rcode = 1;
254 }
255
256 /* Modify ctrl register.
257 */
258 contr_reg[0] = ctrl_reg_v;
259 if (i2c_write (contr_r_addr[0], 0xFF, 1, contr_reg, 1) != 0) {
260 rcode = 1;
261 }
262
263 /* The write (above) is an operation on NV memory.
264 * These can take some time (~5ms), and the device
265 * will not respond to further I2C messages till
266 * it's completed the write.
267 * So poll device for an I2C acknowledge.
268 * When we get one we know we can continue with other
269 * operations.
270 */
271 contr_reg[0] = 0;
272 for (i = 0; i < MAX_ACKNOWLEDGE_POLLS; i++) {
273 if (i2c_read (addr_void[0], addr_void[1], 1, contr_reg, 1) == 0)
274 break; /* got ack */
275 #if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
276 udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
277 #endif
278 }
279 if (i == MAX_ACKNOWLEDGE_POLLS) {
280 puts ("EEPROM poll acknowledge failed\n");
281 rcode = 1;
282 }
283 }
284
285 /* Is the write enable latch on?.
286 */
287 else if (!(ctrl_reg_v & 0x02)) {
288 /* Set write enable latch.
289 */
290 contr_reg[0] = 0x02;
291 if (i2c_write (contr_r_addr[0], 0xFF, 1, contr_reg, 1) != 0) {
292 rcode = 1;
293 }
294 }
295 /* Write is enabled ... now write eeprom value.
296 */
297 #endif
298 #if defined(CONFIG_SYS_I2C_EEPROM_BUS)
299 i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS);
300 #endif
301 if (i2c_write(addr[0], offset, alen - 1, buffer, len))
302 rcode = 1;
303
304 #endif
305 buffer += len;
306 offset += len;
307
308 #if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
309 udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
310 #endif
311 }
312 #if defined(CONFIG_SYS_EEPROM_WREN)
313 eeprom_write_enable (dev_addr,0);
314 #endif
315 return rcode;
316 }
317
318 #if !defined(CONFIG_SPI) || defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
319 int eeprom_probe(unsigned dev_addr, unsigned offset)
320 {
321 unsigned char chip;
322
323 /* Probe the chip address
324 */
325 #if CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
326 chip = offset >> 8; /* block number */
327 #else
328 chip = offset >> 16; /* block number */
329 #endif /* CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */
330
331 chip |= dev_addr; /* insert device address */
332
333 return (i2c_probe (chip));
334 }
335 #endif
336
337 static int do_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
338 {
339 const char *const fmt =
340 "\nEEPROM @0x%lX %s: addr %08lx off %04lx count %ld ... ";
341
342 #if defined(CONFIG_SYS_I2C_MULTI_EEPROMS)
343 if (argc == 6) {
344 ulong dev_addr = simple_strtoul (argv[2], NULL, 16);
345 ulong addr = simple_strtoul (argv[3], NULL, 16);
346 ulong off = simple_strtoul (argv[4], NULL, 16);
347 ulong cnt = simple_strtoul (argv[5], NULL, 16);
348 #else
349 if (argc == 5) {
350 ulong dev_addr = CONFIG_SYS_DEF_EEPROM_ADDR;
351 ulong addr = simple_strtoul (argv[2], NULL, 16);
352 ulong off = simple_strtoul (argv[3], NULL, 16);
353 ulong cnt = simple_strtoul (argv[4], NULL, 16);
354 #endif /* CONFIG_SYS_I2C_MULTI_EEPROMS */
355
356 # if !defined(CONFIG_SPI) || defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
357 eeprom_init ();
358 # endif /* !CONFIG_SPI */
359
360 if (strcmp (argv[1], "read") == 0) {
361 int rcode;
362
363 printf (fmt, dev_addr, argv[1], addr, off, cnt);
364
365 rcode = eeprom_read (dev_addr, off, (uchar *) addr, cnt);
366
367 puts ("done\n");
368 return rcode;
369 } else if (strcmp (argv[1], "write") == 0) {
370 int rcode;
371
372 printf (fmt, dev_addr, argv[1], addr, off, cnt);
373
374 rcode = eeprom_write (dev_addr, off, (uchar *) addr, cnt);
375
376 puts ("done\n");
377 return rcode;
378 }
379 }
380
381 return CMD_RET_USAGE;
382 }
383
384 #ifdef CONFIG_SYS_I2C_MULTI_EEPROMS
385 U_BOOT_CMD(
386 eeprom, 6, 1, do_eeprom,
387 "EEPROM sub-system",
388 "read devaddr addr off cnt\n"
389 "eeprom write devaddr addr off cnt\n"
390 " - read/write `cnt' bytes from `devaddr` EEPROM at offset `off'"
391 )
392 #else /* One EEPROM */
393 U_BOOT_CMD(
394 eeprom, 5, 1, do_eeprom,
395 "EEPROM sub-system",
396 "read addr off cnt\n"
397 "eeprom write addr off cnt\n"
398 " - read/write `cnt' bytes at EEPROM offset `off'"
399 )
400 #endif /* CONFIG_SYS_I2C_MULTI_EEPROMS */