1 /*-----------------------------------------------------------------------------+
2 * This source code is dual-licensed. You may use it under the terms of
3 * the GNU General Public license version 2, or under the license below.
5 * This source code has been made available to you by IBM on an AS-IS
6 * basis. Anyone receiving this source is licensed under IBM
7 * copyrights to use it in any way he or she deems fit, including
8 * copying it, modifying it, compiling it, and redistributing it either
9 * with or without modifications. No license under IBM patents or
10 * patent applications is to be implied by the copyright license.
12 * Any user of this software should understand that IBM cannot provide
13 * technical support for this software and will not be responsible for
14 * any consequences resulting from the use of this software.
16 * Any person who transfers this source code or any derivative work
17 * must include the IBM copyright notice, this paragraph, and the
18 * preceding two paragraphs in the transferred software.
20 * COPYRIGHT I B M CORPORATION 1995
21 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
22 *-----------------------------------------------------------------------------*/
23 /*----------------------------------------------------------------------------+
25 * File Name: 405gp_pci.c
27 * Function: Initialization code for the 405GP PCI Configuration regs.
33 * Date Description of Change BY
34 * --------- --------------------- ---
35 * 09-Sep-98 Created MCG
36 * 02-Nov-98 Removed External arbiter selected message JWB
37 * 27-Nov-98 Zero out PTMBAR2 and disable in PTM2MS JWB
38 * 04-Jan-99 Zero out other unused PMM and PTM regs. Change bus scan MCG
39 * from (0 to n) to (1 to n).
40 * 17-May-99 Port to Walnut JWB
41 * 17-Jun-99 Updated for VGA support JWB
42 * 21-Jun-99 Updated to allow SRAM region to be a target from PCI bus JWB
43 * 19-Jul-99 Updated for 405GP pass 1 errata #26 (Low PCI subsequent MCG
44 * target latency timer values are not supported).
45 * Should be fixed in pass 2.
46 * 09-Sep-99 Removed use of PTM2 since the SRAM region no longer needs JWB
47 * to be a PCI target. Zero out PTMBAR2 and disable in PTM2MS.
48 * 10-Dec-99 Updated PCI_Write_CFG_Reg for pass2 errata #6 JWB
49 * 11-Jan-00 Ensure PMMxMAs disabled before setting PMMxLAs. This is not
50 * really required after a reset since PMMxMAs are already
51 * disabled but is a good practice nonetheless. JWB
52 * 12-Jun-01 stefan.roese@esd-electronics.com
53 * - PCI host/adapter handling reworked
54 * 09-Jul-01 stefan.roese@esd-electronics.com
55 * - PCI host now configures from device 0 (not 1) to max_dev,
56 * (host configures itself)
57 * - On CPCI-405 pci base address and size is generated from
58 * SDRAM and FLASH size (CFG regs not used anymore)
59 * - Some minor changes for CPCI-405-A (adapter version)
60 * 14-Sep-01 stefan.roese@esd-electronics.com
61 * - CONFIG_PCI_SCAN_SHOW added to print pci devices upon startup
62 * 28-Sep-01 stefan.roese@esd-electronics.com
63 * - Changed pci master configuration for linux compatibility
64 * (no need for bios_fixup() anymore)
65 * 26-Feb-02 stefan.roese@esd-electronics.com
66 * - Bug fixed in pci configuration (Andrew May)
67 * - Removed pci class code init for CPCI405 board
68 * 15-May-02 stefan.roese@esd-electronics.com
69 * - New vga device handling
70 * 29-May-02 stefan.roese@esd-electronics.com
71 * - PCI class code init added (if defined)
72 *----------------------------------------------------------------------------*/
76 #if !defined(CONFIG_440)
77 #include <asm/4xx_pci.h>
79 #include <asm/processor.h>
84 DECLARE_GLOBAL_DATA_PTR
;
87 * Board-specific pci initialization
88 * Platform code can reimplement pci_pre_init() if needed
90 int __pci_pre_init(struct pci_controller
*hose
)
92 #if defined (CONFIG_405EP)
94 * Enable the internal PCI arbiter by default.
96 * On 405EP CPUs the internal arbiter can be controlled
97 * by the I2C strapping EEPROM. If you want to do so
98 * or if you want to disable the arbiter pci_pre_init()
99 * must be reimplemented without enabling the arbiter.
100 * The arbiter is enabled in this place because of
101 * compatibility reasons.
103 mtdcr(CPC0_PCI
, mfdcr(CPC0_PCI
) | CPC0_PCI_ARBIT_EN
);
104 #endif /* CONFIG_405EP */
108 int pci_pre_init(struct pci_controller
*hose
) __attribute__((weak
, alias("__pci_pre_init")));
110 #if defined(CONFIG_405GP) || defined(CONFIG_405EP)
112 #if defined(CONFIG_PMC405)
113 ushort
pmc405_pci_subsys_deviceid(void);
118 int __is_pci_host(struct pci_controller
*hose
)
120 #if defined(CONFIG_405GP)
121 if (mfdcr(CPC0_PSR
) & PSR_PCI_ARBIT_EN
)
123 #elif defined (CONFIG_405EP)
124 if (mfdcr(CPC0_PCI
) & CPC0_PCI_ARBIT_EN
)
129 int is_pci_host(struct pci_controller
*hose
) __attribute__((weak
, alias("__is_pci_host")));
131 /*-----------------------------------------------------------------------------+
132 * pci_init. Initializes the 405GP PCI Configuration regs.
133 *-----------------------------------------------------------------------------*/
134 void pci_405gp_init(struct pci_controller
*hose
)
139 unsigned short temp_short
;
140 unsigned long ptmpcila
[2] = {CONFIG_SYS_PCI_PTM1PCI
, CONFIG_SYS_PCI_PTM2PCI
};
141 #if defined(CONFIG_PCI_4xx_PTM_OVERWRITE)
142 char *ptmla_str
, *ptmms_str
;
144 unsigned long ptmla
[2] = {CONFIG_SYS_PCI_PTM1LA
, CONFIG_SYS_PCI_PTM2LA
};
145 unsigned long ptmms
[2] = {CONFIG_SYS_PCI_PTM1MS
, CONFIG_SYS_PCI_PTM2MS
};
146 #if defined(CONFIG_PIP405) || defined (CONFIG_MIP405)
147 unsigned long pmmla
[3] = {0x80000000, 0xA0000000, 0};
148 unsigned long pmmma
[3] = {0xE0000001, 0xE0000001, 0};
149 unsigned long pmmpcila
[3] = {0x80000000, 0x00000000, 0};
150 unsigned long pmmpciha
[3] = {0x00000000, 0x00000000, 0};
152 unsigned long pmmla
[3] = {0x80000000, 0,0};
153 unsigned long pmmma
[3] = {0xC0000001, 0,0};
154 unsigned long pmmpcila
[3] = {0x80000000, 0,0};
155 unsigned long pmmpciha
[3] = {0x00000000, 0,0};
157 #ifdef CONFIG_PCI_PNP
158 #if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
163 #if defined(CONFIG_PCI_4xx_PTM_OVERWRITE)
164 ptmla_str
= getenv("ptm1la");
165 ptmms_str
= getenv("ptm1ms");
166 if(NULL
!= ptmla_str
&& NULL
!= ptmms_str
) {
167 ptmla
[0] = simple_strtoul (ptmla_str
, NULL
, 16);
168 ptmms
[0] = simple_strtoul (ptmms_str
, NULL
, 16);
171 ptmla_str
= getenv("ptm2la");
172 ptmms_str
= getenv("ptm2ms");
173 if(NULL
!= ptmla_str
&& NULL
!= ptmms_str
) {
174 ptmla
[1] = simple_strtoul (ptmla_str
, NULL
, 16);
175 ptmms
[1] = simple_strtoul (ptmms_str
, NULL
, 16);
182 hose
->first_busno
= 0;
183 hose
->last_busno
= 0xff;
185 /* ISA/PCI I/O space */
186 pci_set_region(hose
->regions
+ reg_num
++,
193 pci_set_region(hose
->regions
+ reg_num
++,
205 if (!i
) hose
->pci_fb
= hose
->regions
+ reg_num
;
207 pci_set_region(hose
->regions
+ reg_num
++,
208 ptmpcila
[i
], ptmla
[i
],
209 ~(ptmms
[i
] & 0xfffff000) + 1,
211 PCI_REGION_SYS_MEMORY
);
214 /* PCI memory spaces */
218 pci_set_region(hose
->regions
+ reg_num
++,
219 pmmpcila
[i
], pmmla
[i
],
220 ~(pmmma
[i
] & 0xfffff000) + 1,
224 hose
->region_count
= reg_num
;
226 pci_setup_indirect(hose
,
231 pciauto_region_init(hose
->pci_fb
);
233 /* Let board change/modify hose & do initial checks */
234 if (pci_pre_init (hose
) == 0) {
235 printf("PCI: Board-specific initialization failed.\n");
236 printf("PCI: Configuration aborted.\n");
240 pci_register_hose(hose
);
242 /*--------------------------------------------------------------------------+
243 * 405GP PCI Master configuration.
244 * Map one 512 MB range of PLB/processor addresses to PCI memory space.
245 * PLB address 0x80000000-0xBFFFFFFF ==> PCI address 0x80000000-0xBFFFFFFF
246 * Use byte reversed out routines to handle endianess.
247 *--------------------------------------------------------------------------*/
248 out32r(PMM0MA
, (pmmma
[0]&~0x1)); /* disable, configure PMMxLA, PMMxPCILA first */
249 out32r(PMM0LA
, pmmla
[0]);
250 out32r(PMM0PCILA
, pmmpcila
[0]);
251 out32r(PMM0PCIHA
, pmmpciha
[0]);
252 out32r(PMM0MA
, pmmma
[0]);
254 /*--------------------------------------------------------------------------+
255 * PMM1 is not used. Initialize them to zero.
256 *--------------------------------------------------------------------------*/
257 out32r(PMM1MA
, (pmmma
[1]&~0x1));
258 out32r(PMM1LA
, pmmla
[1]);
259 out32r(PMM1PCILA
, pmmpcila
[1]);
260 out32r(PMM1PCIHA
, pmmpciha
[1]);
261 out32r(PMM1MA
, pmmma
[1]);
263 /*--------------------------------------------------------------------------+
264 * PMM2 is not used. Initialize them to zero.
265 *--------------------------------------------------------------------------*/
266 out32r(PMM2MA
, (pmmma
[2]&~0x1));
267 out32r(PMM2LA
, pmmla
[2]);
268 out32r(PMM2PCILA
, pmmpcila
[2]);
269 out32r(PMM2PCIHA
, pmmpciha
[2]);
270 out32r(PMM2MA
, pmmma
[2]);
272 /*--------------------------------------------------------------------------+
273 * 405GP PCI Target configuration. (PTM1)
274 * Note: PTM1MS is hardwire enabled but we set the enable bit anyway.
275 *--------------------------------------------------------------------------*/
276 out32r(PTM1LA
, ptmla
[0]); /* insert address */
277 out32r(PTM1MS
, ptmms
[0]); /* insert size, enable bit is 1 */
278 pci_write_config_dword(PCIDEVID_405GP
, PCI_BASE_ADDRESS_1
, ptmpcila
[0]);
280 /*--------------------------------------------------------------------------+
281 * 405GP PCI Target configuration. (PTM2)
282 *--------------------------------------------------------------------------*/
283 out32r(PTM2LA
, ptmla
[1]); /* insert address */
284 pci_write_config_dword(PCIDEVID_405GP
, PCI_BASE_ADDRESS_2
, ptmpcila
[1]);
288 out32r(PTM2MS
, 0x00000001); /* set enable bit */
289 pci_write_config_dword(PCIDEVID_405GP
, PCI_BASE_ADDRESS_2
, 0x00000000);
290 out32r(PTM2MS
, 0x00000000); /* disable */
294 out32r(PTM2MS
, ptmms
[1]); /* insert size, enable bit is 1 */
298 * Insert Subsystem Vendor and Device ID
300 pci_write_config_word(PCIDEVID_405GP
, PCI_SUBSYSTEM_VENDOR_ID
, CONFIG_SYS_PCI_SUBSYS_VENDORID
);
301 #ifdef CONFIG_CPCI405
302 if (is_pci_host(hose
))
303 pci_write_config_word(PCIDEVID_405GP
, PCI_SUBSYSTEM_ID
, CONFIG_SYS_PCI_SUBSYS_DEVICEID
);
305 pci_write_config_word(PCIDEVID_405GP
, PCI_SUBSYSTEM_ID
, CONFIG_SYS_PCI_SUBSYS_DEVICEID2
);
307 pci_write_config_word(PCIDEVID_405GP
, PCI_SUBSYSTEM_ID
, CONFIG_SYS_PCI_SUBSYS_DEVICEID
);
313 #ifdef CONFIG_SYS_PCI_CLASSCODE
314 pci_write_config_word(PCIDEVID_405GP
, PCI_CLASS_SUB_CODE
, CONFIG_SYS_PCI_CLASSCODE
);
315 #endif /* CONFIG_SYS_PCI_CLASSCODE */
317 /*--------------------------------------------------------------------------+
318 * If PCI speed = 66MHz, set 66MHz capable bit.
319 *--------------------------------------------------------------------------*/
320 if (bd
->bi_pci_busfreq
>= 66000000) {
321 pci_read_config_word(PCIDEVID_405GP
, PCI_STATUS
, &temp_short
);
322 pci_write_config_word(PCIDEVID_405GP
,PCI_STATUS
,(temp_short
|PCI_STATUS_66MHZ
));
325 #if (CONFIG_PCI_HOST != PCI_HOST_ADAPTER)
326 #if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
327 if (is_pci_host(hose
) ||
328 (((s
= getenv("pciscan")) != NULL
) && (strcmp(s
, "yes") == 0)))
331 /*--------------------------------------------------------------------------+
332 * Write the 405GP PCI Configuration regs.
333 * Enable 405GP to be a master on the PCI bus (PMM).
334 * Enable 405GP to act as a PCI memory target (PTM).
335 *--------------------------------------------------------------------------*/
336 pci_read_config_word(PCIDEVID_405GP
, PCI_COMMAND
, &temp_short
);
337 pci_write_config_word(PCIDEVID_405GP
, PCI_COMMAND
, temp_short
|
338 PCI_COMMAND_MASTER
| PCI_COMMAND_MEMORY
);
342 #if defined(CONFIG_405EP)
344 * on ppc405ep vendor/device id is not set
345 * The user manual says 0x1014 (IBM) / 0x0156 (405GP!)
346 * are the correct values.
348 pci_write_config_word(PCIDEVID_405GP
, PCI_VENDOR_ID
, PCI_VENDOR_ID_IBM
);
349 pci_write_config_word(PCIDEVID_405GP
,
350 PCI_DEVICE_ID
, PCI_DEVICE_ID_IBM_405GP
);
354 * Set HCE bit (Host Configuration Enabled)
356 pci_read_config_word(PCIDEVID_405GP
, PCIBRDGOPT2
, &temp_short
);
357 pci_write_config_word(PCIDEVID_405GP
, PCIBRDGOPT2
, (temp_short
| 0x0001));
359 #ifdef CONFIG_PCI_PNP
360 /*--------------------------------------------------------------------------+
361 * Scan the PCI bus and configure devices found.
362 *--------------------------------------------------------------------------*/
363 #if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
364 if (is_pci_host(hose
) ||
365 (((s
= getenv("pciscan")) != NULL
) && (strcmp(s
, "yes") == 0)))
368 #ifdef CONFIG_PCI_SCAN_SHOW
369 printf("PCI: Bus Dev VenId DevId Class Int\n");
371 hose
->last_busno
= pci_hose_scan(hose
);
373 #endif /* CONFIG_PCI_PNP */
378 * drivers/pci/pci.c skips every host bridge but the 405GP since it could
379 * be set as an Adapter.
381 * I (Andrew May) don't know what we should do here, but I don't want
382 * the auto setup of a PCI device disabling what is done pci_405gp_init
383 * as has happened before.
385 void pci_405gp_setup_bridge(struct pci_controller
*hose
, pci_dev_t dev
,
386 struct pci_config_table
*entry
)
389 printf("405gp_setup_bridge\n");
397 void pci_405gp_fixup_irq(struct pci_controller
*hose
, pci_dev_t dev
)
399 unsigned char int_line
= 0xff;
402 * Write pci interrupt line register (cpci405 specific)
404 switch (PCI_DEV(dev
) & 0x03)
420 pci_hose_write_config_byte(hose
, dev
, PCI_INTERRUPT_LINE
, int_line
);
423 void pci_405gp_setup_vga(struct pci_controller
*hose
, pci_dev_t dev
,
424 struct pci_config_table
*entry
)
426 unsigned int cmdstat
= 0;
428 pciauto_setup_device(hose
, dev
, 6, hose
->pci_mem
, hose
->pci_prefetch
, hose
->pci_io
);
430 /* always enable io space on vga boards */
431 pci_hose_read_config_dword(hose
, dev
, PCI_COMMAND
, &cmdstat
);
432 cmdstat
|= PCI_COMMAND_IO
;
433 pci_hose_write_config_dword(hose
, dev
, PCI_COMMAND
, cmdstat
);
436 #if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405)) && !(defined (CONFIG_SC3))
439 *As is these functs get called out of flash Not a horrible
440 *thing, but something to keep in mind. (no statics?)
442 static struct pci_config_table pci_405gp_config_table
[] = {
443 /*if VendID is 0 it terminates the table search (ie Walnut)*/
444 #ifdef CONFIG_SYS_PCI_SUBSYS_VENDORID
445 {CONFIG_SYS_PCI_SUBSYS_VENDORID
, PCI_ANY_ID
, PCI_CLASS_BRIDGE_HOST
,
446 PCI_ANY_ID
, PCI_ANY_ID
, PCI_ANY_ID
, pci_405gp_setup_bridge
},
448 {PCI_ANY_ID
, PCI_ANY_ID
, PCI_CLASS_DISPLAY_VGA
,
449 PCI_ANY_ID
, PCI_ANY_ID
, PCI_ANY_ID
, pci_405gp_setup_vga
},
451 {PCI_ANY_ID
, PCI_ANY_ID
, PCI_CLASS_NOT_DEFINED_VGA
,
452 PCI_ANY_ID
, PCI_ANY_ID
, PCI_ANY_ID
, pci_405gp_setup_vga
},
457 static struct pci_controller hose
= {
458 fixup_irq
: pci_405gp_fixup_irq
,
459 config_table
: pci_405gp_config_table
,
462 void pci_init_board(void)
464 /*we want the ptrs to RAM not flash (ie don't use init list)*/
465 hose
.fixup_irq
= pci_405gp_fixup_irq
;
466 hose
.config_table
= pci_405gp_config_table
;
467 pci_405gp_init(&hose
);
472 #endif /* CONFIG_405GP */
474 /*-----------------------------------------------------------------------------+
476 *-----------------------------------------------------------------------------*/
477 #if defined(CONFIG_440)
479 static struct pci_controller ppc440_hose
= {0};
482 int pci_440_init (struct pci_controller
*hose
)
486 #ifndef CONFIG_DISABLE_PISE_TEST
487 /*--------------------------------------------------------------------------+
488 * The PCI initialization sequence enable bit must be set ... if not abort
489 * pci setup since updating the bit requires chip reset.
490 *--------------------------------------------------------------------------*/
491 #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
494 mfsdr(SDR0_SDSTP1
,strap
);
495 if ((strap
& SDR0_SDSTP1_PISE_MASK
) == 0) {
496 printf("PCI: SDR0_STRP1[PISE] not set.\n");
497 printf("PCI: Configuration aborted.\n");
500 #elif defined(CONFIG_440GP)
503 strap
= mfdcr(CPC0_STRP1
);
504 if ((strap
& CPC0_STRP1_PISE_MASK
) == 0) {
505 printf("PCI: CPC0_STRP1[PISE] not set.\n");
506 printf("PCI: Configuration aborted.\n");
510 #endif /* CONFIG_DISABLE_PISE_TEST */
512 /*--------------------------------------------------------------------------+
513 * PCI controller init
514 *--------------------------------------------------------------------------*/
515 hose
->first_busno
= 0;
516 hose
->last_busno
= 0;
519 pci_set_region(hose
->regions
+ reg_num
++,
525 /* PCI memory space */
526 pci_set_region(hose
->regions
+ reg_num
++,
527 CONFIG_SYS_PCI_TARGBASE
,
528 CONFIG_SYS_PCI_MEMBASE
,
529 #ifdef CONFIG_SYS_PCI_MEMSIZE
530 CONFIG_SYS_PCI_MEMSIZE
,
536 #if defined(CONFIG_PCI_SYS_MEM_BUS) && defined(CONFIG_PCI_SYS_MEM_PHYS) && \
537 defined(CONFIG_PCI_SYS_MEM_SIZE)
538 /* System memory space */
539 pci_set_region(hose
->regions
+ reg_num
++,
540 CONFIG_PCI_SYS_MEM_BUS
,
541 CONFIG_PCI_SYS_MEM_PHYS
,
542 CONFIG_PCI_SYS_MEM_SIZE
,
543 PCI_REGION_MEM
| PCI_REGION_SYS_MEMORY
);
546 hose
->region_count
= reg_num
;
548 pci_setup_indirect(hose
, PCIX0_CFGADR
, PCIX0_CFGDATA
);
550 /* Let board change/modify hose & do initial checks */
551 if (pci_pre_init (hose
) == 0) {
552 printf("PCI: Board-specific initialization failed.\n");
553 printf("PCI: Configuration aborted.\n");
557 pci_register_hose( hose
);
559 /*--------------------------------------------------------------------------+
561 *--------------------------------------------------------------------------*/
562 #if defined(CONFIG_SYS_PCI_TARGET_INIT)
563 pci_target_init(hose
); /* Let board setup pci target */
565 out16r( PCIX0_SBSYSVID
, CONFIG_SYS_PCI_SUBSYS_VENDORID
);
566 out16r( PCIX0_SBSYSID
, CONFIG_SYS_PCI_SUBSYS_ID
);
567 out16r( PCIX0_CLS
, 0x00060000 ); /* Bridge, host bridge */
570 #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
571 defined(CONFIG_460EX) || defined(CONFIG_460GT)
572 out32r( PCIX0_BRDGOPT1
, 0x04000060 ); /* PLB Rq pri highest */
573 out32r( PCIX0_BRDGOPT2
, in32(PCIX0_BRDGOPT2
) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1 */
574 #elif defined(PCIX0_BRDGOPT1)
575 out32r( PCIX0_BRDGOPT1
, 0x10000060 ); /* PLB Rq pri highest */
576 out32r( PCIX0_BRDGOPT2
, in32(PCIX0_BRDGOPT2
) | 1 ); /* Enable host config */
579 /*--------------------------------------------------------------------------+
580 * PCI master init: default is one 256MB region for PCI memory:
581 * 0x3_00000000 - 0x3_0FFFFFFF ==> CONFIG_SYS_PCI_MEMBASE
582 *--------------------------------------------------------------------------*/
583 #if defined(CONFIG_SYS_PCI_MASTER_INIT)
584 pci_master_init(hose
); /* Let board setup pci master */
586 out32r( PCIX0_POM0SA
, 0 ); /* disable */
587 out32r( PCIX0_POM1SA
, 0 ); /* disable */
588 out32r( PCIX0_POM2SA
, 0 ); /* disable */
589 #if defined(CONFIG_440SPE)
590 out32r( PCIX0_POM0LAL
, 0x10000000 );
591 out32r( PCIX0_POM0LAH
, 0x0000000c );
592 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
593 out32r( PCIX0_POM0LAL
, 0x20000000 );
594 out32r( PCIX0_POM0LAH
, 0x0000000c );
596 out32r( PCIX0_POM0LAL
, 0x00000000 );
597 out32r( PCIX0_POM0LAH
, 0x00000003 );
599 out32r( PCIX0_POM0PCIAL
, CONFIG_SYS_PCI_MEMBASE
);
600 out32r( PCIX0_POM0PCIAH
, 0x00000000 );
601 out32r( PCIX0_POM0SA
, 0xf0000001 ); /* 256MB, enabled */
602 out32r( PCIX0_STS
, in32r( PCIX0_STS
) & ~0x0000fff8 );
605 /*--------------------------------------------------------------------------+
606 * PCI host configuration -- we don't make any assumptions here ... the
607 * _board_must_indicate_ what to do -- there's just too many runtime
608 * scenarios in environments like cPCI, PPMC, etc. to make a determination
609 * based on hard-coded values or state of arbiter enable.
610 *--------------------------------------------------------------------------*/
611 if (is_pci_host(hose
)) {
612 #ifdef CONFIG_PCI_SCAN_SHOW
613 printf("PCI: Bus Dev VenId DevId Class Int\n");
615 #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \
616 !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
617 out16r( PCIX0_CMD
, in16r( PCIX0_CMD
) | PCI_COMMAND_MASTER
);
619 hose
->last_busno
= pci_hose_scan(hose
);
621 return hose
->last_busno
;
624 void pci_init_board(void)
628 busno
= pci_440_init (&ppc440_hose
);
629 #if (defined(CONFIG_440SPE) || \
630 defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \
631 !defined(CONFIG_PCI_DISABLE_PCIE)
632 pcie_setup_hoses(busno
+ 1);
636 #endif /* CONFIG_440 */
638 #if defined(CONFIG_405EX)
639 void pci_init_board(void)
641 #ifdef CONFIG_PCI_SCAN_SHOW
642 printf("PCI: Bus Dev VenId DevId Class Int\n");
646 #endif /* CONFIG_405EX */
648 #endif /* CONFIG_PCI */