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ppc4xx: Cleanup some HW register names
[people/ms/u-boot.git] / cpu / ppc4xx / 4xx_pci.c
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c609719b 1/*-----------------------------------------------------------------------------+
31773496
JB		 2 * This source code is dual-licensed. You may use it under the terms of
3 * the GNU General Public license version 2, or under the license below.
c609719b
WD		 4 *
5 * This source code has been made available to you by IBM on an AS-IS
6 * basis. Anyone receiving this source is licensed under IBM
7 * copyrights to use it in any way he or she deems fit, including
8 * copying it, modifying it, compiling it, and redistributing it either
9 * with or without modifications. No license under IBM patents or
10 * patent applications is to be implied by the copyright license.
11 *
12 * Any user of this software should understand that IBM cannot provide
13 * technical support for this software and will not be responsible for
14 * any consequences resulting from the use of this software.
15 *
16 * Any person who transfers this source code or any derivative work
17 * must include the IBM copyright notice, this paragraph, and the
18 * preceding two paragraphs in the transferred software.
19 *
20 * COPYRIGHT I B M CORPORATION 1995
21 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
22 *-----------------------------------------------------------------------------*/
23/*----------------------------------------------------------------------------+
24 *
25 * File Name: 405gp_pci.c
26 *
27 * Function: Initialization code for the 405GP PCI Configuration regs.
28 *
29 * Author: Mark Game
30 *
31 * Change Activity-
32 *
33 * Date Description of Change BY
34 * --------- --------------------- ---
35 * 09-Sep-98 Created MCG
36 * 02-Nov-98 Removed External arbiter selected message JWB
37 * 27-Nov-98 Zero out PTMBAR2 and disable in PTM2MS JWB
38 * 04-Jan-99 Zero out other unused PMM and PTM regs. Change bus scan MCG
39 * from (0 to n) to (1 to n).
40 * 17-May-99 Port to Walnut JWB
41 * 17-Jun-99 Updated for VGA support JWB
42 * 21-Jun-99 Updated to allow SRAM region to be a target from PCI bus JWB
43 * 19-Jul-99 Updated for 405GP pass 1 errata #26 (Low PCI subsequent MCG
44 * target latency timer values are not supported).
45 * Should be fixed in pass 2.
46 * 09-Sep-99 Removed use of PTM2 since the SRAM region no longer needs JWB
47 * to be a PCI target. Zero out PTMBAR2 and disable in PTM2MS.
48 * 10-Dec-99 Updated PCI_Write_CFG_Reg for pass2 errata #6 JWB
49 * 11-Jan-00 Ensure PMMxMAs disabled before setting PMMxLAs. This is not
50 * really required after a reset since PMMxMAs are already
53677ef1 51 * disabled but is a good practice nonetheless. JWB
c609719b
WD		 52 * 12-Jun-01 stefan.roese@esd-electronics.com
53 * - PCI host/adapter handling reworked
54 * 09-Jul-01 stefan.roese@esd-electronics.com
55 * - PCI host now configures from device 0 (not 1) to max_dev,
56 * (host configures itself)
57 * - On CPCI-405 pci base address and size is generated from
58 * SDRAM and FLASH size (CFG regs not used anymore)
59 * - Some minor changes for CPCI-405-A (adapter version)
60 * 14-Sep-01 stefan.roese@esd-electronics.com
61 * - CONFIG_PCI_SCAN_SHOW added to print pci devices upon startup
62 * 28-Sep-01 stefan.roese@esd-electronics.com
63 * - Changed pci master configuration for linux compatibility
64 * (no need for bios_fixup() anymore)
65 * 26-Feb-02 stefan.roese@esd-electronics.com
66 * - Bug fixed in pci configuration (Andrew May)
67 * - Removed pci class code init for CPCI405 board
68 * 15-May-02 stefan.roese@esd-electronics.com
69 * - New vga device handling
70 * 29-May-02 stefan.roese@esd-electronics.com
71 * - PCI class code init added (if defined)
72 *----------------------------------------------------------------------------*/
73
74#include <common.h>
75#include <command.h>
c609719b 76#if !defined(CONFIG_440)
3048bcbf 77#include <asm/4xx_pci.h>
c609719b
WD		 78#endif
79#include <asm/processor.h>
80#include <pci.h>
81
5a1c9ff0
MF		 82#ifdef CONFIG_PCI
83
d87080b7
WD		 84DECLARE_GLOBAL_DATA_PTR;
85
5a1c9ff0
MF		 86/*
87 * Board-specific pci initialization
88 * Platform code can reimplement pci_pre_init() if needed
89 */
90int __pci_pre_init(struct pci_controller *hose)
91{
123f102e
MF		 92#if defined (CONFIG_405EP)
93 /*
94 * Enable the internal PCI arbiter by default.
95 *
96 * On 405EP CPUs the internal arbiter can be controlled
97 * by the I2C strapping EEPROM. If you want to do so
98 * or if you want to disable the arbiter pci_pre_init()
99 * must be reimplemented without enabling the arbiter.
100 * The arbiter is enabled in this place because of
101 * compatibility reasons.
102 */
d1c3b275 103 mtdcr(CPC0_PCI, mfdcr(CPC0_PCI) | CPC0_PCI_ARBIT_EN);
123f102e
MF		 104#endif /* CONFIG_405EP */
105
5a1c9ff0
MF		 106 return 1;
107}
108int pci_pre_init(struct pci_controller *hose) __attribute__((weak, alias("__pci_pre_init")));
c609719b 109
5a1c9ff0 110#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
c609719b 111
2076d0a1
SR		 112#if defined(CONFIG_PMC405)
113ushort pmc405_pci_subsys_deviceid(void);
114#endif
115
c609719b
WD		 116/*#define DEBUG*/
117
d0a1364f
MF		 118int __is_pci_host(struct pci_controller *hose)
119{
120#if defined(CONFIG_405GP)
d1c3b275 121 if (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN)
d0a1364f
MF		 122 return 1;
123#elif defined (CONFIG_405EP)
d1c3b275 124 if (mfdcr(CPC0_PCI) & CPC0_PCI_ARBIT_EN)
d0a1364f
MF		 125 return 1;
126#endif
127 return 0;
128}
129int is_pci_host(struct pci_controller *hose) __attribute__((weak, alias("__is_pci_host")));
130
c609719b
WD		 131/*-----------------------------------------------------------------------------+
132 * pci_init. Initializes the 405GP PCI Configuration regs.
133 *-----------------------------------------------------------------------------*/
134void pci_405gp_init(struct pci_controller *hose)
135{
c609719b
WD		 136 int i, reg_num = 0;
137 bd_t *bd = gd->bd;
138
139 unsigned short temp_short;
6d0f6bcf 140 unsigned long ptmpcila[2] = {CONFIG_SYS_PCI_PTM1PCI, CONFIG_SYS_PCI_PTM2PCI};
99bcf14d 141#if defined(CONFIG_PCI_4xx_PTM_OVERWRITE)
fddae7b8 142 char *ptmla_str, *ptmms_str;
2076d0a1 143#endif
6d0f6bcf
JCPV		 144 unsigned long ptmla[2] = {CONFIG_SYS_PCI_PTM1LA, CONFIG_SYS_PCI_PTM2LA};
145 unsigned long ptmms[2] = {CONFIG_SYS_PCI_PTM1MS, CONFIG_SYS_PCI_PTM2MS};
c609719b
WD		 146#if defined(CONFIG_PIP405) || defined (CONFIG_MIP405)
147 unsigned long pmmla[3] = {0x80000000, 0xA0000000, 0};
148 unsigned long pmmma[3] = {0xE0000001, 0xE0000001, 0};
149 unsigned long pmmpcila[3] = {0x80000000, 0x00000000, 0};
150 unsigned long pmmpciha[3] = {0x00000000, 0x00000000, 0};
151#else
152 unsigned long pmmla[3] = {0x80000000, 0,0};
153 unsigned long pmmma[3] = {0xC0000001, 0,0};
154 unsigned long pmmpcila[3] = {0x80000000, 0,0};
155 unsigned long pmmpciha[3] = {0x00000000, 0,0};
5e746fce
SR		 156#endif
157#ifdef CONFIG_PCI_PNP
158#if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
159 char *s;
160#endif
c609719b
WD		 161#endif
162
99bcf14d 163#if defined(CONFIG_PCI_4xx_PTM_OVERWRITE)
fddae7b8
SR		 164 ptmla_str = getenv("ptm1la");
165 ptmms_str = getenv("ptm1ms");
166 if(NULL != ptmla_str && NULL != ptmms_str ) {
167 ptmla[0] = simple_strtoul (ptmla_str, NULL, 16);
168 ptmms[0] = simple_strtoul (ptmms_str, NULL, 16);
169 }
170
171 ptmla_str = getenv("ptm2la");
172 ptmms_str = getenv("ptm2ms");
173 if(NULL != ptmla_str && NULL != ptmms_str ) {
174 ptmla[1] = simple_strtoul (ptmla_str, NULL, 16);
175 ptmms[1] = simple_strtoul (ptmms_str, NULL, 16);
176 }
177#endif
178
c609719b
WD		 179 /*
180 * Register the hose
181 */
182 hose->first_busno = 0;
183 hose->last_busno = 0xff;
184
185 /* ISA/PCI I/O space */
186 pci_set_region(hose->regions + reg_num++,
187 MIN_PCI_PCI_IOADDR,
188 MIN_PLB_PCI_IOADDR,
189 0x10000,
190 PCI_REGION_IO);
191
192 /* PCI I/O space */
193 pci_set_region(hose->regions + reg_num++,
194 0x00800000,
195 0xe8800000,
196 0x03800000,
197 PCI_REGION_IO);
198
199 reg_num = 2;
200
201 /* Memory spaces */
202 for (i=0; i<2; i++)
203 if (ptmms[i] & 1)
204 {
205 if (!i) hose->pci_fb = hose->regions + reg_num;
206
207 pci_set_region(hose->regions + reg_num++,
208 ptmpcila[i], ptmla[i],
209 ~(ptmms[i] & 0xfffff000) + 1,
210 PCI_REGION_MEM |
ff4e66e9 211 PCI_REGION_SYS_MEMORY);
c609719b
WD		 212 }
213
214 /* PCI memory spaces */
215 for (i=0; i<3; i++)
216 if (pmmma[i] & 1)
217 {
218 pci_set_region(hose->regions + reg_num++,
219 pmmpcila[i], pmmla[i],
220 ~(pmmma[i] & 0xfffff000) + 1,
221 PCI_REGION_MEM);
222 }
223
224 hose->region_count = reg_num;
225
226 pci_setup_indirect(hose,
227 PCICFGADR,
228 PCICFGDATA);
229
230 if (hose->pci_fb)
231 pciauto_region_init(hose->pci_fb);
232
5a1c9ff0
MF		 233 /* Let board change/modify hose & do initial checks */
234 if (pci_pre_init (hose) == 0) {
235 printf("PCI: Board-specific initialization failed.\n");
236 printf("PCI: Configuration aborted.\n");
237 return;
238 }
239
c609719b
WD		 240 pci_register_hose(hose);
241
242 /*--------------------------------------------------------------------------+
243 * 405GP PCI Master configuration.
244 * Map one 512 MB range of PLB/processor addresses to PCI memory space.
245 * PLB address 0x80000000-0xBFFFFFFF ==> PCI address 0x80000000-0xBFFFFFFF
246 * Use byte reversed out routines to handle endianess.
247 *--------------------------------------------------------------------------*/
f3e0de60 248 out32r(PMM0MA, (pmmma[0]&~0x1)); /* disable, configure PMMxLA, PMMxPCILA first */
c609719b
WD		 249 out32r(PMM0LA, pmmla[0]);
250 out32r(PMM0PCILA, pmmpcila[0]);
251 out32r(PMM0PCIHA, pmmpciha[0]);
252 out32r(PMM0MA, pmmma[0]);
253
254 /*--------------------------------------------------------------------------+
255 * PMM1 is not used. Initialize them to zero.
256 *--------------------------------------------------------------------------*/
f3e0de60 257 out32r(PMM1MA, (pmmma[1]&~0x1));
c609719b
WD		 258 out32r(PMM1LA, pmmla[1]);
259 out32r(PMM1PCILA, pmmpcila[1]);
260 out32r(PMM1PCIHA, pmmpciha[1]);
261 out32r(PMM1MA, pmmma[1]);
262
263 /*--------------------------------------------------------------------------+
264 * PMM2 is not used. Initialize them to zero.
265 *--------------------------------------------------------------------------*/
8bde7f77 266 out32r(PMM2MA, (pmmma[2]&~0x1));
c609719b
WD		 267 out32r(PMM2LA, pmmla[2]);
268 out32r(PMM2PCILA, pmmpcila[2]);
269 out32r(PMM2PCIHA, pmmpciha[2]);
270 out32r(PMM2MA, pmmma[2]);
271
272 /*--------------------------------------------------------------------------+
273 * 405GP PCI Target configuration. (PTM1)
274 * Note: PTM1MS is hardwire enabled but we set the enable bit anyway.
275 *--------------------------------------------------------------------------*/
276 out32r(PTM1LA, ptmla[0]); /* insert address */
277 out32r(PTM1MS, ptmms[0]); /* insert size, enable bit is 1 */
4654af27 278 pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_1, ptmpcila[0]);
c609719b
WD		 279
280 /*--------------------------------------------------------------------------+
281 * 405GP PCI Target configuration. (PTM2)
282 *--------------------------------------------------------------------------*/
283 out32r(PTM2LA, ptmla[1]); /* insert address */
4654af27
WD		 284 pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, ptmpcila[1]);
285
c609719b
WD		 286 if (ptmms[1] == 0)
287 {
288 out32r(PTM2MS, 0x00000001); /* set enable bit */
289 pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, 0x00000000);
290 out32r(PTM2MS, 0x00000000); /* disable */
291 }
292 else
293 {
294 out32r(PTM2MS, ptmms[1]); /* insert size, enable bit is 1 */
295 }
296
297 /*
298 * Insert Subsystem Vendor and Device ID
299 */
6d0f6bcf 300 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_VENDOR_ID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
c609719b 301#ifdef CONFIG_CPCI405
d0a1364f 302 if (is_pci_host(hose))
6d0f6bcf 303 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
c609719b 304 else
6d0f6bcf 305 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID2);
c609719b 306#else
6d0f6bcf 307 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
c609719b
WD		 308#endif
309
310 /*
311 * Insert Class-code
312 */
6d0f6bcf
JCPV		 313#ifdef CONFIG_SYS_PCI_CLASSCODE
314 pci_write_config_word(PCIDEVID_405GP, PCI_CLASS_SUB_CODE, CONFIG_SYS_PCI_CLASSCODE);
315#endif /* CONFIG_SYS_PCI_CLASSCODE */
c609719b
WD		 316
317 /*--------------------------------------------------------------------------+
8ed44d91 318 * If PCI speed = 66MHz, set 66MHz capable bit.
c609719b
WD		 319 *--------------------------------------------------------------------------*/
320 if (bd->bi_pci_busfreq >= 66000000) {
321 pci_read_config_word(PCIDEVID_405GP, PCI_STATUS, &temp_short);
322 pci_write_config_word(PCIDEVID_405GP,PCI_STATUS,(temp_short|PCI_STATUS_66MHZ));
323 }
324
325#if (CONFIG_PCI_HOST != PCI_HOST_ADAPTER)
4654af27 326#if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
d0a1364f 327 if (is_pci_host(hose) ||
5e746fce 328 (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0)))
c609719b
WD		 329#endif
330 {
331 /*--------------------------------------------------------------------------+
332 * Write the 405GP PCI Configuration regs.
333 * Enable 405GP to be a master on the PCI bus (PMM).
334 * Enable 405GP to act as a PCI memory target (PTM).
335 *--------------------------------------------------------------------------*/
336 pci_read_config_word(PCIDEVID_405GP, PCI_COMMAND, &temp_short);
337 pci_write_config_word(PCIDEVID_405GP, PCI_COMMAND, temp_short |
338 PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
339 }
340#endif
341
632e9b67
MF		 342#if defined(CONFIG_405EP)
343 /*
344 * on ppc405ep vendor/device id is not set
345 * The user manual says 0x1014 (IBM) / 0x0156 (405GP!)
346 * are the correct values.
347 */
348 pci_write_config_word(PCIDEVID_405GP, PCI_VENDOR_ID, PCI_VENDOR_ID_IBM);
349 pci_write_config_word(PCIDEVID_405GP,
350 PCI_DEVICE_ID, PCI_DEVICE_ID_IBM_405GP);
428c5639
SR		 351#endif
352
c609719b
WD		 353 /*
354 * Set HCE bit (Host Configuration Enabled)
355 */
356 pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &temp_short);
357 pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (temp_short | 0x0001));
358
359#ifdef CONFIG_PCI_PNP
360 /*--------------------------------------------------------------------------+
361 * Scan the PCI bus and configure devices found.
362 *--------------------------------------------------------------------------*/
363#if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
d0a1364f 364 if (is_pci_host(hose) ||
5e746fce 365 (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0)))
c609719b
WD		 366#endif
367 {
368#ifdef CONFIG_PCI_SCAN_SHOW
369 printf("PCI: Bus Dev VenId DevId Class Int\n");
370#endif
c609719b
WD		 371 hose->last_busno = pci_hose_scan(hose);
372 }
373#endif /* CONFIG_PCI_PNP */
374
375}
376
377/*
7817cb20 378 * drivers/pci/pci.c skips every host bridge but the 405GP since it could
c609719b
WD		 379 * be set as an Adapter.
380 *
381 * I (Andrew May) don't know what we should do here, but I don't want
382 * the auto setup of a PCI device disabling what is done pci_405gp_init
383 * as has happened before.
384 */
385void pci_405gp_setup_bridge(struct pci_controller *hose, pci_dev_t dev,
386 struct pci_config_table *entry)
387{
388#ifdef DEBUG
8bde7f77 389 printf("405gp_setup_bridge\n");
c609719b
WD		 390#endif
391}
392
393/*
394 *
395 */
396
397void pci_405gp_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
398{
399 unsigned char int_line = 0xff;
400
401 /*
402 * Write pci interrupt line register (cpci405 specific)
403 */
404 switch (PCI_DEV(dev) & 0x03)
405 {
406 case 0:
407 int_line = 27 + 2;
408 break;
409 case 1:
410 int_line = 27 + 3;
411 break;
412 case 2:
413 int_line = 27 + 0;
414 break;
415 case 3:
416 int_line = 27 + 1;
417 break;
418 }
419
420 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
421}
422
423void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
424 struct pci_config_table *entry)
425{
426 unsigned int cmdstat = 0;
427
f3fecfe6 428 pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
c609719b
WD		 429
430 /* always enable io space on vga boards */
431 pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
432 cmdstat |= PCI_COMMAND_IO;
433 pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
434}
435
9045f33c 436#if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405)) && !(defined (CONFIG_SC3))
c609719b
WD		 437
438/*
439 *As is these functs get called out of flash Not a horrible
440 *thing, but something to keep in mind. (no statics?)
441 */
442static struct pci_config_table pci_405gp_config_table[] = {
443/*if VendID is 0 it terminates the table search (ie Walnut)*/
6d0f6bcf
JCPV		 444#ifdef CONFIG_SYS_PCI_SUBSYS_VENDORID
445 {CONFIG_SYS_PCI_SUBSYS_VENDORID, PCI_ANY_ID, PCI_CLASS_BRIDGE_HOST,
c609719b
WD		 446 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_bridge},
447#endif
448 {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA,
449 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},
450
451 {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NOT_DEFINED_VGA,
452 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},
453
454 { }
455};
456
457static struct pci_controller hose = {
458 fixup_irq: pci_405gp_fixup_irq,
459 config_table: pci_405gp_config_table,
460};
461
ad10dd9a 462void pci_init_board(void)
c609719b
WD		 463{
464 /*we want the ptrs to RAM not flash (ie don't use init list)*/
465 hose.fixup_irq = pci_405gp_fixup_irq;
466 hose.config_table = pci_405gp_config_table;
467 pci_405gp_init(&hose);
468}
469
470#endif
471
c609719b
WD		 472#endif /* CONFIG_405GP */
473
474/*-----------------------------------------------------------------------------+
475 * CONFIG_440
476 *-----------------------------------------------------------------------------*/
5a1c9ff0 477#if defined(CONFIG_440)
c609719b
WD		 478
479static struct pci_controller ppc440_hose = {0};
480
481
7f191393 482int pci_440_init (struct pci_controller *hose)
c609719b
WD		 483{
484 int reg_num = 0;
c609719b 485
5568e613 486#ifndef CONFIG_DISABLE_PISE_TEST
c609719b
WD		 487 /*--------------------------------------------------------------------------+
488 * The PCI initialization sequence enable bit must be set ... if not abort
3c74e32a 489 * pci setup since updating the bit requires chip reset.
c609719b 490 *--------------------------------------------------------------------------*/
6c5879f3 491#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
5568e613
SR		 492 unsigned long strap;
493
d1c3b275 494 mfsdr(SDR0_SDSTP1,strap);
6e7fb6ea 495 if ((strap & SDR0_SDSTP1_PISE_MASK) == 0) {
3c74e32a
WD		 496 printf("PCI: SDR0_STRP1[PISE] not set.\n");
497 printf("PCI: Configuration aborted.\n");
7f191393 498 return -1;
3c74e32a 499 }
5568e613
SR		 500#elif defined(CONFIG_440GP)
501 unsigned long strap;
502
d1c3b275 503 strap = mfdcr(CPC0_STRP1);
6e7fb6ea 504 if ((strap & CPC0_STRP1_PISE_MASK) == 0) {
3c74e32a
WD		 505 printf("PCI: CPC0_STRP1[PISE] not set.\n");
506 printf("PCI: Configuration aborted.\n");
7f191393 507 return -1;
3c74e32a
WD		 508 }
509#endif
5568e613
SR		 510#endif /* CONFIG_DISABLE_PISE_TEST */
511
c609719b
WD		 512 /*--------------------------------------------------------------------------+
513 * PCI controller init
514 *--------------------------------------------------------------------------*/
515 hose->first_busno = 0;
7f191393 516 hose->last_busno = 0;
c609719b 517
fbb0b559 518 /* PCI I/O space */
c609719b
WD		 519 pci_set_region(hose->regions + reg_num++,
520 0x00000000,
6e7fb6ea
SR		 521 PCIX0_IOBASE,
522 0x10000,
523 PCI_REGION_IO);
c609719b 524
fbb0b559 525 /* PCI memory space */
c609719b 526 pci_set_region(hose->regions + reg_num++,
6d0f6bcf
JCPV		 527 CONFIG_SYS_PCI_TARGBASE,
528 CONFIG_SYS_PCI_MEMBASE,
529#ifdef CONFIG_SYS_PCI_MEMSIZE
530 CONFIG_SYS_PCI_MEMSIZE,
899620c2 531#else
6e7fb6ea 532 0x10000000,
899620c2 533#endif
6e7fb6ea 534 PCI_REGION_MEM );
fbb0b559
MB		 535
536#if defined(CONFIG_PCI_SYS_MEM_BUS) && defined(CONFIG_PCI_SYS_MEM_PHYS) && \
537 defined(CONFIG_PCI_SYS_MEM_SIZE)
538 /* System memory space */
539 pci_set_region(hose->regions + reg_num++,
540 CONFIG_PCI_SYS_MEM_BUS,
541 CONFIG_PCI_SYS_MEM_PHYS,
542 CONFIG_PCI_SYS_MEM_SIZE,
ff4e66e9 543 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY );
fbb0b559
MB		 544#endif
545
c609719b
WD		 546 hose->region_count = reg_num;
547
548 pci_setup_indirect(hose, PCIX0_CFGADR, PCIX0_CFGDATA);
549
6e7fb6ea
SR		 550 /* Let board change/modify hose & do initial checks */
551 if (pci_pre_init (hose) == 0) {
552 printf("PCI: Board-specific initialization failed.\n");
553 printf("PCI: Configuration aborted.\n");
7f191393 554 return -1;
6e7fb6ea 555 }
c609719b
WD		 556
557 pci_register_hose( hose );
558
559 /*--------------------------------------------------------------------------+
560 * PCI target init
561 *--------------------------------------------------------------------------*/
6d0f6bcf 562#if defined(CONFIG_SYS_PCI_TARGET_INIT)
c609719b
WD		 563 pci_target_init(hose); /* Let board setup pci target */
564#else
6d0f6bcf
JCPV		 565 out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
566 out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_ID );
6e7fb6ea 567 out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */
c609719b
WD		 568#endif
569
8ac41e3e
SR		 570#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
571 defined(CONFIG_460EX) || defined(CONFIG_460GT)
3c74e32a
WD		 572 out32r( PCIX0_BRDGOPT1, 0x04000060 ); /* PLB Rq pri highest */
573 out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1 */
c157d8e2 574#elif defined(PCIX0_BRDGOPT1)
3c74e32a
WD		 575 out32r( PCIX0_BRDGOPT1, 0x10000060 ); /* PLB Rq pri highest */
576 out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 1 ); /* Enable host config */
577#endif
c609719b
WD		 578
579 /*--------------------------------------------------------------------------+
580 * PCI master init: default is one 256MB region for PCI memory:
6d0f6bcf 581 * 0x3_00000000 - 0x3_0FFFFFFF ==> CONFIG_SYS_PCI_MEMBASE
c609719b 582 *--------------------------------------------------------------------------*/
6d0f6bcf 583#if defined(CONFIG_SYS_PCI_MASTER_INIT)
c609719b
WD		 584 pci_master_init(hose); /* Let board setup pci master */
585#else
586 out32r( PCIX0_POM0SA, 0 ); /* disable */
587 out32r( PCIX0_POM1SA, 0 ); /* disable */
588 out32r( PCIX0_POM2SA, 0 ); /* disable */
f8853d10 589#if defined(CONFIG_440SPE)
6c5879f3
MB		 590 out32r( PCIX0_POM0LAL, 0x10000000 );
591 out32r( PCIX0_POM0LAH, 0x0000000c );
f8853d10
AG		 592#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
593 out32r( PCIX0_POM0LAL, 0x20000000 );
594 out32r( PCIX0_POM0LAH, 0x0000000c );
6c5879f3 595#else
c609719b
WD		 596 out32r( PCIX0_POM0LAL, 0x00000000 );
597 out32r( PCIX0_POM0LAH, 0x00000003 );
6c5879f3 598#endif
6d0f6bcf 599 out32r( PCIX0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE );
c609719b
WD		 600 out32r( PCIX0_POM0PCIAH, 0x00000000 );
601 out32r( PCIX0_POM0SA, 0xf0000001 ); /* 256MB, enabled */
6e7fb6ea 602 out32r( PCIX0_STS, in32r( PCIX0_STS ) & ~0x0000fff8 );
c609719b
WD		 603#endif
604
605 /*--------------------------------------------------------------------------+
606 * PCI host configuration -- we don't make any assumptions here ... the
6e7fb6ea
SR		 607 * _board_must_indicate_ what to do -- there's just too many runtime
608 * scenarios in environments like cPCI, PPMC, etc. to make a determination
609 * based on hard-coded values or state of arbiter enable.
c609719b 610 *--------------------------------------------------------------------------*/
6e7fb6ea 611 if (is_pci_host(hose)) {
c609719b 612#ifdef CONFIG_PCI_SCAN_SHOW
6e7fb6ea 613 printf("PCI: Bus Dev VenId DevId Class Int\n");
c609719b 614#endif
887e2ec9
SR		 615#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \
616 !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
6e7fb6ea 617 out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER);
c157d8e2 618#endif
6e7fb6ea
SR		 619 hose->last_busno = pci_hose_scan(hose);
620 }
7f191393 621 return hose->last_busno;
c609719b
WD		 622}
623
ad10dd9a 624void pci_init_board(void)
c609719b 625{
7f191393
GB		 626 int busno;
627
628 busno = pci_440_init (&ppc440_hose);
59d1bda7
DE		 629#if (defined(CONFIG_440SPE) || \
630 defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \
631 !defined(CONFIG_PCI_DISABLE_PCIE)
7f191393 632 pcie_setup_hoses(busno + 1);
692519b1 633#endif
c609719b
WD		 634}
635
5a1c9ff0 636#endif /* CONFIG_440 */
1d7b874e
SR		 637
638#if defined(CONFIG_405EX)
639void pci_init_board(void)
640{
641#ifdef CONFIG_PCI_SCAN_SHOW
642 printf("PCI: Bus Dev VenId DevId Class Int\n");
643#endif
644 pcie_setup_hoses(0);
645}
646#endif /* CONFIG_405EX */
647
5a1c9ff0 648#endif /* CONFIG_PCI */
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