5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
8 * Additional technical information is available on
9 * http://www.linux-mtd.infradead.org/doc/nand.html
11 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
12 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
15 * David Woodhouse for adding multichip support
17 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
18 * rework for 2K page size chips
21 * Enable cached programming for 2k page size chips
22 * Check, if mtd->ecctype should be set to MTD_ECC_HW
23 * if we have HW ECC support.
24 * BBT table is not serialized, has to be fixed
26 * This program is free software; you can redistribute it and/or modify
27 * it under the terms of the GNU General Public License version 2 as
28 * published by the Free Software Foundation.
32 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
36 #include <linux/err.h>
37 #include <linux/compat.h>
38 #include <linux/mtd/mtd.h>
39 #include <linux/mtd/nand.h>
40 #include <linux/mtd/nand_ecc.h>
41 #include <linux/mtd/nand_bch.h>
42 #ifdef CONFIG_MTD_PARTITIONS
43 #include <linux/mtd/partitions.h>
46 #include <asm/errno.h>
48 static bool is_module_text_address(unsigned long addr
) {return 0;}
50 /* Define default oob placement schemes for large and small page devices */
51 static struct nand_ecclayout nand_oob_8
= {
61 static struct nand_ecclayout nand_oob_16
= {
63 .eccpos
= {0, 1, 2, 3, 6, 7},
69 static struct nand_ecclayout nand_oob_64
= {
72 40, 41, 42, 43, 44, 45, 46, 47,
73 48, 49, 50, 51, 52, 53, 54, 55,
74 56, 57, 58, 59, 60, 61, 62, 63},
80 static struct nand_ecclayout nand_oob_128
= {
83 80, 81, 82, 83, 84, 85, 86, 87,
84 88, 89, 90, 91, 92, 93, 94, 95,
85 96, 97, 98, 99, 100, 101, 102, 103,
86 104, 105, 106, 107, 108, 109, 110, 111,
87 112, 113, 114, 115, 116, 117, 118, 119,
88 120, 121, 122, 123, 124, 125, 126, 127},
94 static int nand_get_device(struct mtd_info
*mtd
, int new_state
);
96 static int nand_do_write_oob(struct mtd_info
*mtd
, loff_t to
,
97 struct mtd_oob_ops
*ops
);
100 * For devices which display every fart in the system on a separate LED. Is
101 * compiled away when LED support is disabled.
103 DEFINE_LED_TRIGGER(nand_led_trigger
);
105 static int check_offs_len(struct mtd_info
*mtd
,
106 loff_t ofs
, uint64_t len
)
108 struct nand_chip
*chip
= mtd_to_nand(mtd
);
111 /* Start address must align on block boundary */
112 if (ofs
& ((1ULL << chip
->phys_erase_shift
) - 1)) {
113 pr_debug("%s: unaligned address\n", __func__
);
117 /* Length must align on block boundary */
118 if (len
& ((1ULL << chip
->phys_erase_shift
) - 1)) {
119 pr_debug("%s: length not block aligned\n", __func__
);
127 * nand_release_device - [GENERIC] release chip
128 * @mtd: MTD device structure
130 * Release chip lock and wake up anyone waiting on the device.
132 static void nand_release_device(struct mtd_info
*mtd
)
134 struct nand_chip
*chip
= mtd_to_nand(mtd
);
136 /* De-select the NAND device */
137 chip
->select_chip(mtd
, -1);
141 * nand_read_byte - [DEFAULT] read one byte from the chip
142 * @mtd: MTD device structure
144 * Default read function for 8bit buswidth
146 uint8_t nand_read_byte(struct mtd_info
*mtd
)
148 struct nand_chip
*chip
= mtd_to_nand(mtd
);
149 return readb(chip
->IO_ADDR_R
);
153 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
154 * @mtd: MTD device structure
156 * Default read function for 16bit buswidth with endianness conversion.
159 static uint8_t nand_read_byte16(struct mtd_info
*mtd
)
161 struct nand_chip
*chip
= mtd_to_nand(mtd
);
162 return (uint8_t) cpu_to_le16(readw(chip
->IO_ADDR_R
));
166 * nand_read_word - [DEFAULT] read one word from the chip
167 * @mtd: MTD device structure
169 * Default read function for 16bit buswidth without endianness conversion.
171 static u16
nand_read_word(struct mtd_info
*mtd
)
173 struct nand_chip
*chip
= mtd_to_nand(mtd
);
174 return readw(chip
->IO_ADDR_R
);
178 * nand_select_chip - [DEFAULT] control CE line
179 * @mtd: MTD device structure
180 * @chipnr: chipnumber to select, -1 for deselect
182 * Default select function for 1 chip devices.
184 static void nand_select_chip(struct mtd_info
*mtd
, int chipnr
)
186 struct nand_chip
*chip
= mtd_to_nand(mtd
);
190 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, 0 | NAND_CTRL_CHANGE
);
201 * nand_write_byte - [DEFAULT] write single byte to chip
202 * @mtd: MTD device structure
203 * @byte: value to write
205 * Default function to write a byte to I/O[7:0]
207 static void nand_write_byte(struct mtd_info
*mtd
, uint8_t byte
)
209 struct nand_chip
*chip
= mtd_to_nand(mtd
);
211 chip
->write_buf(mtd
, &byte
, 1);
215 * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
216 * @mtd: MTD device structure
217 * @byte: value to write
219 * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
221 static void nand_write_byte16(struct mtd_info
*mtd
, uint8_t byte
)
223 struct nand_chip
*chip
= mtd_to_nand(mtd
);
224 uint16_t word
= byte
;
227 * It's not entirely clear what should happen to I/O[15:8] when writing
228 * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
230 * When the host supports a 16-bit bus width, only data is
231 * transferred at the 16-bit width. All address and command line
232 * transfers shall use only the lower 8-bits of the data bus. During
233 * command transfers, the host may place any value on the upper
234 * 8-bits of the data bus. During address transfers, the host shall
235 * set the upper 8-bits of the data bus to 00h.
237 * One user of the write_byte callback is nand_onfi_set_features. The
238 * four parameters are specified to be written to I/O[7:0], but this is
239 * neither an address nor a command transfer. Let's assume a 0 on the
240 * upper I/O lines is OK.
242 chip
->write_buf(mtd
, (uint8_t *)&word
, 2);
245 #if !defined(CONFIG_BLACKFIN)
246 static void iowrite8_rep(void *addr
, const uint8_t *buf
, int len
)
250 for (i
= 0; i
< len
; i
++)
251 writeb(buf
[i
], addr
);
253 static void ioread8_rep(void *addr
, uint8_t *buf
, int len
)
257 for (i
= 0; i
< len
; i
++)
258 buf
[i
] = readb(addr
);
261 static void ioread16_rep(void *addr
, void *buf
, int len
)
264 u16
*p
= (u16
*) buf
;
266 for (i
= 0; i
< len
; i
++)
270 static void iowrite16_rep(void *addr
, void *buf
, int len
)
273 u16
*p
= (u16
*) buf
;
275 for (i
= 0; i
< len
; i
++)
281 * nand_write_buf - [DEFAULT] write buffer to chip
282 * @mtd: MTD device structure
284 * @len: number of bytes to write
286 * Default write function for 8bit buswidth.
288 void nand_write_buf(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
290 struct nand_chip
*chip
= mtd_to_nand(mtd
);
292 iowrite8_rep(chip
->IO_ADDR_W
, buf
, len
);
296 * nand_read_buf - [DEFAULT] read chip data into buffer
297 * @mtd: MTD device structure
298 * @buf: buffer to store date
299 * @len: number of bytes to read
301 * Default read function for 8bit buswidth.
303 void nand_read_buf(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
305 struct nand_chip
*chip
= mtd_to_nand(mtd
);
307 ioread8_rep(chip
->IO_ADDR_R
, buf
, len
);
311 * nand_write_buf16 - [DEFAULT] write buffer to chip
312 * @mtd: MTD device structure
314 * @len: number of bytes to write
316 * Default write function for 16bit buswidth.
318 void nand_write_buf16(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
320 struct nand_chip
*chip
= mtd_to_nand(mtd
);
321 u16
*p
= (u16
*) buf
;
323 iowrite16_rep(chip
->IO_ADDR_W
, p
, len
>> 1);
327 * nand_read_buf16 - [DEFAULT] read chip data into buffer
328 * @mtd: MTD device structure
329 * @buf: buffer to store date
330 * @len: number of bytes to read
332 * Default read function for 16bit buswidth.
334 void nand_read_buf16(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
336 struct nand_chip
*chip
= mtd_to_nand(mtd
);
337 u16
*p
= (u16
*) buf
;
339 ioread16_rep(chip
->IO_ADDR_R
, p
, len
>> 1);
343 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
344 * @mtd: MTD device structure
345 * @ofs: offset from device start
346 * @getchip: 0, if the chip is already selected
348 * Check, if the block is bad.
350 static int nand_block_bad(struct mtd_info
*mtd
, loff_t ofs
, int getchip
)
352 int page
, chipnr
, res
= 0, i
= 0;
353 struct nand_chip
*chip
= mtd_to_nand(mtd
);
356 if (chip
->bbt_options
& NAND_BBT_SCANLASTPAGE
)
357 ofs
+= mtd
->erasesize
- mtd
->writesize
;
359 page
= (int)(ofs
>> chip
->page_shift
) & chip
->pagemask
;
362 chipnr
= (int)(ofs
>> chip
->chip_shift
);
364 nand_get_device(mtd
, FL_READING
);
366 /* Select the NAND device */
367 chip
->select_chip(mtd
, chipnr
);
371 if (chip
->options
& NAND_BUSWIDTH_16
) {
372 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
,
373 chip
->badblockpos
& 0xFE, page
);
374 bad
= cpu_to_le16(chip
->read_word(mtd
));
375 if (chip
->badblockpos
& 0x1)
380 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, chip
->badblockpos
,
382 bad
= chip
->read_byte(mtd
);
385 if (likely(chip
->badblockbits
== 8))
388 res
= hweight8(bad
) < chip
->badblockbits
;
389 ofs
+= mtd
->writesize
;
390 page
= (int)(ofs
>> chip
->page_shift
) & chip
->pagemask
;
392 } while (!res
&& i
< 2 && (chip
->bbt_options
& NAND_BBT_SCAN2NDPAGE
));
395 chip
->select_chip(mtd
, -1);
396 nand_release_device(mtd
);
403 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
404 * @mtd: MTD device structure
405 * @ofs: offset from device start
407 * This is the default implementation, which can be overridden by a hardware
408 * specific driver. It provides the details for writing a bad block marker to a
411 static int nand_default_block_markbad(struct mtd_info
*mtd
, loff_t ofs
)
413 struct nand_chip
*chip
= mtd_to_nand(mtd
);
414 struct mtd_oob_ops ops
;
415 uint8_t buf
[2] = { 0, 0 };
416 int ret
= 0, res
, i
= 0;
418 memset(&ops
, 0, sizeof(ops
));
420 ops
.ooboffs
= chip
->badblockpos
;
421 if (chip
->options
& NAND_BUSWIDTH_16
) {
422 ops
.ooboffs
&= ~0x01;
423 ops
.len
= ops
.ooblen
= 2;
425 ops
.len
= ops
.ooblen
= 1;
427 ops
.mode
= MTD_OPS_PLACE_OOB
;
429 /* Write to first/last page(s) if necessary */
430 if (chip
->bbt_options
& NAND_BBT_SCANLASTPAGE
)
431 ofs
+= mtd
->erasesize
- mtd
->writesize
;
433 res
= nand_do_write_oob(mtd
, ofs
, &ops
);
438 ofs
+= mtd
->writesize
;
439 } while ((chip
->bbt_options
& NAND_BBT_SCAN2NDPAGE
) && i
< 2);
445 * nand_block_markbad_lowlevel - mark a block bad
446 * @mtd: MTD device structure
447 * @ofs: offset from device start
449 * This function performs the generic NAND bad block marking steps (i.e., bad
450 * block table(s) and/or marker(s)). We only allow the hardware driver to
451 * specify how to write bad block markers to OOB (chip->block_markbad).
453 * We try operations in the following order:
454 * (1) erase the affected block, to allow OOB marker to be written cleanly
455 * (2) write bad block marker to OOB area of affected block (unless flag
456 * NAND_BBT_NO_OOB_BBM is present)
458 * Note that we retain the first error encountered in (2) or (3), finish the
459 * procedures, and dump the error in the end.
461 static int nand_block_markbad_lowlevel(struct mtd_info
*mtd
, loff_t ofs
)
463 struct nand_chip
*chip
= mtd_to_nand(mtd
);
466 if (!(chip
->bbt_options
& NAND_BBT_NO_OOB_BBM
)) {
467 struct erase_info einfo
;
469 /* Attempt erase before marking OOB */
470 memset(&einfo
, 0, sizeof(einfo
));
473 einfo
.len
= 1ULL << chip
->phys_erase_shift
;
474 nand_erase_nand(mtd
, &einfo
, 0);
476 /* Write bad block marker to OOB */
477 nand_get_device(mtd
, FL_WRITING
);
478 ret
= chip
->block_markbad(mtd
, ofs
);
479 nand_release_device(mtd
);
482 /* Mark block bad in BBT */
484 res
= nand_markbad_bbt(mtd
, ofs
);
490 mtd
->ecc_stats
.badblocks
++;
496 * nand_check_wp - [GENERIC] check if the chip is write protected
497 * @mtd: MTD device structure
499 * Check, if the device is write protected. The function expects, that the
500 * device is already selected.
502 static int nand_check_wp(struct mtd_info
*mtd
)
504 struct nand_chip
*chip
= mtd_to_nand(mtd
);
506 /* Broken xD cards report WP despite being writable */
507 if (chip
->options
& NAND_BROKEN_XD
)
510 /* Check the WP bit */
511 chip
->cmdfunc(mtd
, NAND_CMD_STATUS
, -1, -1);
512 return (chip
->read_byte(mtd
) & NAND_STATUS_WP
) ? 0 : 1;
516 * nand_block_isreserved - [GENERIC] Check if a block is marked reserved.
517 * @mtd: MTD device structure
518 * @ofs: offset from device start
520 * Check if the block is marked as reserved.
522 static int nand_block_isreserved(struct mtd_info
*mtd
, loff_t ofs
)
524 struct nand_chip
*chip
= mtd_to_nand(mtd
);
528 /* Return info from the table */
529 return nand_isreserved_bbt(mtd
, ofs
);
533 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
534 * @mtd: MTD device structure
535 * @ofs: offset from device start
536 * @getchip: 0, if the chip is already selected
537 * @allowbbt: 1, if its allowed to access the bbt area
539 * Check, if the block is bad. Either by reading the bad block table or
540 * calling of the scan function.
542 static int nand_block_checkbad(struct mtd_info
*mtd
, loff_t ofs
, int getchip
,
545 struct nand_chip
*chip
= mtd_to_nand(mtd
);
547 if (!(chip
->options
& NAND_SKIP_BBTSCAN
) &&
548 !(chip
->options
& NAND_BBT_SCANNED
)) {
549 chip
->options
|= NAND_BBT_SCANNED
;
554 return chip
->block_bad(mtd
, ofs
, getchip
);
556 /* Return info from the table */
557 return nand_isbad_bbt(mtd
, ofs
, allowbbt
);
560 /* Wait for the ready pin, after a command. The timeout is caught later. */
561 void nand_wait_ready(struct mtd_info
*mtd
)
563 struct nand_chip
*chip
= mtd_to_nand(mtd
);
564 u32 timeo
= (CONFIG_SYS_HZ
* 20) / 1000;
567 time_start
= get_timer(0);
568 /* Wait until command is processed or timeout occurs */
569 while (get_timer(time_start
) < timeo
) {
571 if (chip
->dev_ready(mtd
))
575 EXPORT_SYMBOL_GPL(nand_wait_ready
);
578 * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands.
579 * @mtd: MTD device structure
580 * @timeo: Timeout in ms
582 * Wait for status ready (i.e. command done) or timeout.
584 static void nand_wait_status_ready(struct mtd_info
*mtd
, unsigned long timeo
)
586 register struct nand_chip
*chip
= mtd_to_nand(mtd
);
589 timeo
= (CONFIG_SYS_HZ
* timeo
) / 1000;
590 time_start
= get_timer(0);
591 while (get_timer(time_start
) < timeo
) {
592 if ((chip
->read_byte(mtd
) & NAND_STATUS_READY
))
599 * nand_command - [DEFAULT] Send command to NAND device
600 * @mtd: MTD device structure
601 * @command: the command to be sent
602 * @column: the column address for this command, -1 if none
603 * @page_addr: the page address for this command, -1 if none
605 * Send command to NAND device. This function is used for small page devices
606 * (512 Bytes per page).
608 static void nand_command(struct mtd_info
*mtd
, unsigned int command
,
609 int column
, int page_addr
)
611 register struct nand_chip
*chip
= mtd_to_nand(mtd
);
612 int ctrl
= NAND_CTRL_CLE
| NAND_CTRL_CHANGE
;
614 /* Write out the command to the device */
615 if (command
== NAND_CMD_SEQIN
) {
618 if (column
>= mtd
->writesize
) {
620 column
-= mtd
->writesize
;
621 readcmd
= NAND_CMD_READOOB
;
622 } else if (column
< 256) {
623 /* First 256 bytes --> READ0 */
624 readcmd
= NAND_CMD_READ0
;
627 readcmd
= NAND_CMD_READ1
;
629 chip
->cmd_ctrl(mtd
, readcmd
, ctrl
);
630 ctrl
&= ~NAND_CTRL_CHANGE
;
632 chip
->cmd_ctrl(mtd
, command
, ctrl
);
634 /* Address cycle, when necessary */
635 ctrl
= NAND_CTRL_ALE
| NAND_CTRL_CHANGE
;
636 /* Serially input address */
638 /* Adjust columns for 16 bit buswidth */
639 if (chip
->options
& NAND_BUSWIDTH_16
&&
640 !nand_opcode_8bits(command
))
642 chip
->cmd_ctrl(mtd
, column
, ctrl
);
643 ctrl
&= ~NAND_CTRL_CHANGE
;
645 if (page_addr
!= -1) {
646 chip
->cmd_ctrl(mtd
, page_addr
, ctrl
);
647 ctrl
&= ~NAND_CTRL_CHANGE
;
648 chip
->cmd_ctrl(mtd
, page_addr
>> 8, ctrl
);
649 /* One more address cycle for devices > 32MiB */
650 if (chip
->chipsize
> (32 << 20))
651 chip
->cmd_ctrl(mtd
, page_addr
>> 16, ctrl
);
653 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
656 * Program and erase have their own busy handlers status and sequential
661 case NAND_CMD_PAGEPROG
:
662 case NAND_CMD_ERASE1
:
663 case NAND_CMD_ERASE2
:
665 case NAND_CMD_STATUS
:
671 udelay(chip
->chip_delay
);
672 chip
->cmd_ctrl(mtd
, NAND_CMD_STATUS
,
673 NAND_CTRL_CLE
| NAND_CTRL_CHANGE
);
675 NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
676 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
677 nand_wait_status_ready(mtd
, 250);
680 /* This applies to read commands */
683 * If we don't have access to the busy pin, we apply the given
686 if (!chip
->dev_ready
) {
687 udelay(chip
->chip_delay
);
692 * Apply this short delay always to ensure that we do wait tWB in
693 * any case on any machine.
697 nand_wait_ready(mtd
);
701 * nand_command_lp - [DEFAULT] Send command to NAND large page device
702 * @mtd: MTD device structure
703 * @command: the command to be sent
704 * @column: the column address for this command, -1 if none
705 * @page_addr: the page address for this command, -1 if none
707 * Send command to NAND device. This is the version for the new large page
708 * devices. We don't have the separate regions as we have in the small page
709 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
711 static void nand_command_lp(struct mtd_info
*mtd
, unsigned int command
,
712 int column
, int page_addr
)
714 register struct nand_chip
*chip
= mtd_to_nand(mtd
);
716 /* Emulate NAND_CMD_READOOB */
717 if (command
== NAND_CMD_READOOB
) {
718 column
+= mtd
->writesize
;
719 command
= NAND_CMD_READ0
;
722 /* Command latch cycle */
723 chip
->cmd_ctrl(mtd
, command
, NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
725 if (column
!= -1 || page_addr
!= -1) {
726 int ctrl
= NAND_CTRL_CHANGE
| NAND_NCE
| NAND_ALE
;
728 /* Serially input address */
730 /* Adjust columns for 16 bit buswidth */
731 if (chip
->options
& NAND_BUSWIDTH_16
&&
732 !nand_opcode_8bits(command
))
734 chip
->cmd_ctrl(mtd
, column
, ctrl
);
735 ctrl
&= ~NAND_CTRL_CHANGE
;
736 chip
->cmd_ctrl(mtd
, column
>> 8, ctrl
);
738 if (page_addr
!= -1) {
739 chip
->cmd_ctrl(mtd
, page_addr
, ctrl
);
740 chip
->cmd_ctrl(mtd
, page_addr
>> 8,
741 NAND_NCE
| NAND_ALE
);
742 /* One more address cycle for devices > 128MiB */
743 if (chip
->chipsize
> (128 << 20))
744 chip
->cmd_ctrl(mtd
, page_addr
>> 16,
745 NAND_NCE
| NAND_ALE
);
748 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
751 * Program and erase have their own busy handlers status, sequential
752 * in and status need no delay.
756 case NAND_CMD_CACHEDPROG
:
757 case NAND_CMD_PAGEPROG
:
758 case NAND_CMD_ERASE1
:
759 case NAND_CMD_ERASE2
:
762 case NAND_CMD_STATUS
:
768 udelay(chip
->chip_delay
);
769 chip
->cmd_ctrl(mtd
, NAND_CMD_STATUS
,
770 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
771 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
,
772 NAND_NCE
| NAND_CTRL_CHANGE
);
773 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
774 nand_wait_status_ready(mtd
, 250);
777 case NAND_CMD_RNDOUT
:
778 /* No ready / busy check necessary */
779 chip
->cmd_ctrl(mtd
, NAND_CMD_RNDOUTSTART
,
780 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
781 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
,
782 NAND_NCE
| NAND_CTRL_CHANGE
);
786 chip
->cmd_ctrl(mtd
, NAND_CMD_READSTART
,
787 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
788 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
,
789 NAND_NCE
| NAND_CTRL_CHANGE
);
791 /* This applies to read commands */
794 * If we don't have access to the busy pin, we apply the given
797 if (!chip
->dev_ready
) {
798 udelay(chip
->chip_delay
);
804 * Apply this short delay always to ensure that we do wait tWB in
805 * any case on any machine.
809 nand_wait_ready(mtd
);
813 * panic_nand_get_device - [GENERIC] Get chip for selected access
814 * @chip: the nand chip descriptor
815 * @mtd: MTD device structure
816 * @new_state: the state which is requested
818 * Used when in panic, no locks are taken.
820 static void panic_nand_get_device(struct nand_chip
*chip
,
821 struct mtd_info
*mtd
, int new_state
)
823 /* Hardware controller shared among independent devices */
824 chip
->controller
->active
= chip
;
825 chip
->state
= new_state
;
829 * nand_get_device - [GENERIC] Get chip for selected access
830 * @mtd: MTD device structure
831 * @new_state: the state which is requested
833 * Get the device and lock it for exclusive access
836 nand_get_device(struct mtd_info
*mtd
, int new_state
)
838 struct nand_chip
*chip
= mtd_to_nand(mtd
);
839 chip
->state
= new_state
;
844 * panic_nand_wait - [GENERIC] wait until the command is done
845 * @mtd: MTD device structure
846 * @chip: NAND chip structure
849 * Wait for command done. This is a helper function for nand_wait used when
850 * we are in interrupt context. May happen when in panic and trying to write
851 * an oops through mtdoops.
853 static void panic_nand_wait(struct mtd_info
*mtd
, struct nand_chip
*chip
,
857 for (i
= 0; i
< timeo
; i
++) {
858 if (chip
->dev_ready
) {
859 if (chip
->dev_ready(mtd
))
862 if (chip
->read_byte(mtd
) & NAND_STATUS_READY
)
870 * nand_wait - [DEFAULT] wait until the command is done
871 * @mtd: MTD device structure
872 * @chip: NAND chip structure
874 * Wait for command done. This applies to erase and program only. Erase can
875 * take up to 400ms and program up to 20ms according to general NAND and
878 static int nand_wait(struct mtd_info
*mtd
, struct nand_chip
*chip
)
881 int status
, state
= chip
->state
;
882 unsigned long timeo
= (state
== FL_ERASING
? 400 : 20);
884 led_trigger_event(nand_led_trigger
, LED_FULL
);
887 * Apply this short delay always to ensure that we do wait tWB in any
888 * case on any machine.
892 chip
->cmdfunc(mtd
, NAND_CMD_STATUS
, -1, -1);
894 u32 timer
= (CONFIG_SYS_HZ
* timeo
) / 1000;
897 time_start
= get_timer(0);
898 while (get_timer(time_start
) < timer
) {
899 if (chip
->dev_ready
) {
900 if (chip
->dev_ready(mtd
))
903 if (chip
->read_byte(mtd
) & NAND_STATUS_READY
)
907 led_trigger_event(nand_led_trigger
, LED_OFF
);
909 status
= (int)chip
->read_byte(mtd
);
910 /* This can happen if in case of timeout or buggy dev_ready */
911 WARN_ON(!(status
& NAND_STATUS_READY
));
916 * nand_read_page_raw - [INTERN] read raw page data without ecc
917 * @mtd: mtd info structure
918 * @chip: nand chip info structure
919 * @buf: buffer to store read data
920 * @oob_required: caller requires OOB data read to chip->oob_poi
921 * @page: page number to read
923 * Not for syndrome calculating ECC controllers, which use a special oob layout.
925 static int nand_read_page_raw(struct mtd_info
*mtd
, struct nand_chip
*chip
,
926 uint8_t *buf
, int oob_required
, int page
)
928 chip
->read_buf(mtd
, buf
, mtd
->writesize
);
930 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
935 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
936 * @mtd: mtd info structure
937 * @chip: nand chip info structure
938 * @buf: buffer to store read data
939 * @oob_required: caller requires OOB data read to chip->oob_poi
940 * @page: page number to read
942 * We need a special oob layout and handling even when OOB isn't used.
944 static int nand_read_page_raw_syndrome(struct mtd_info
*mtd
,
945 struct nand_chip
*chip
, uint8_t *buf
,
946 int oob_required
, int page
)
948 int eccsize
= chip
->ecc
.size
;
949 int eccbytes
= chip
->ecc
.bytes
;
950 uint8_t *oob
= chip
->oob_poi
;
953 for (steps
= chip
->ecc
.steps
; steps
> 0; steps
--) {
954 chip
->read_buf(mtd
, buf
, eccsize
);
957 if (chip
->ecc
.prepad
) {
958 chip
->read_buf(mtd
, oob
, chip
->ecc
.prepad
);
959 oob
+= chip
->ecc
.prepad
;
962 chip
->read_buf(mtd
, oob
, eccbytes
);
965 if (chip
->ecc
.postpad
) {
966 chip
->read_buf(mtd
, oob
, chip
->ecc
.postpad
);
967 oob
+= chip
->ecc
.postpad
;
971 size
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
973 chip
->read_buf(mtd
, oob
, size
);
979 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
980 * @mtd: mtd info structure
981 * @chip: nand chip info structure
982 * @buf: buffer to store read data
983 * @oob_required: caller requires OOB data read to chip->oob_poi
984 * @page: page number to read
986 static int nand_read_page_swecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
987 uint8_t *buf
, int oob_required
, int page
)
989 int i
, eccsize
= chip
->ecc
.size
;
990 int eccbytes
= chip
->ecc
.bytes
;
991 int eccsteps
= chip
->ecc
.steps
;
993 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
994 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
995 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
996 unsigned int max_bitflips
= 0;
998 chip
->ecc
.read_page_raw(mtd
, chip
, buf
, 1, page
);
1000 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
)
1001 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1003 for (i
= 0; i
< chip
->ecc
.total
; i
++)
1004 ecc_code
[i
] = chip
->oob_poi
[eccpos
[i
]];
1006 eccsteps
= chip
->ecc
.steps
;
1009 for (i
= 0 ; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1012 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], &ecc_calc
[i
]);
1014 mtd
->ecc_stats
.failed
++;
1016 mtd
->ecc_stats
.corrected
+= stat
;
1017 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1020 return max_bitflips
;
1024 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
1025 * @mtd: mtd info structure
1026 * @chip: nand chip info structure
1027 * @data_offs: offset of requested data within the page
1028 * @readlen: data length
1029 * @bufpoi: buffer to store read data
1030 * @page: page number to read
1032 static int nand_read_subpage(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1033 uint32_t data_offs
, uint32_t readlen
, uint8_t *bufpoi
,
1036 int start_step
, end_step
, num_steps
;
1037 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1039 int data_col_addr
, i
, gaps
= 0;
1040 int datafrag_len
, eccfrag_len
, aligned_len
, aligned_pos
;
1041 int busw
= (chip
->options
& NAND_BUSWIDTH_16
) ? 2 : 1;
1043 unsigned int max_bitflips
= 0;
1045 /* Column address within the page aligned to ECC size (256bytes) */
1046 start_step
= data_offs
/ chip
->ecc
.size
;
1047 end_step
= (data_offs
+ readlen
- 1) / chip
->ecc
.size
;
1048 num_steps
= end_step
- start_step
+ 1;
1049 index
= start_step
* chip
->ecc
.bytes
;
1051 /* Data size aligned to ECC ecc.size */
1052 datafrag_len
= num_steps
* chip
->ecc
.size
;
1053 eccfrag_len
= num_steps
* chip
->ecc
.bytes
;
1055 data_col_addr
= start_step
* chip
->ecc
.size
;
1056 /* If we read not a page aligned data */
1057 if (data_col_addr
!= 0)
1058 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, data_col_addr
, -1);
1060 p
= bufpoi
+ data_col_addr
;
1061 chip
->read_buf(mtd
, p
, datafrag_len
);
1064 for (i
= 0; i
< eccfrag_len
; i
+= chip
->ecc
.bytes
, p
+= chip
->ecc
.size
)
1065 chip
->ecc
.calculate(mtd
, p
, &chip
->buffers
->ecccalc
[i
]);
1068 * The performance is faster if we position offsets according to
1069 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1071 for (i
= 0; i
< eccfrag_len
- 1; i
++) {
1072 if (eccpos
[i
+ index
] + 1 != eccpos
[i
+ index
+ 1]) {
1078 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, mtd
->writesize
, -1);
1079 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1082 * Send the command to read the particular ECC bytes take care
1083 * about buswidth alignment in read_buf.
1085 aligned_pos
= eccpos
[index
] & ~(busw
- 1);
1086 aligned_len
= eccfrag_len
;
1087 if (eccpos
[index
] & (busw
- 1))
1089 if (eccpos
[index
+ (num_steps
* chip
->ecc
.bytes
)] & (busw
- 1))
1092 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
,
1093 mtd
->writesize
+ aligned_pos
, -1);
1094 chip
->read_buf(mtd
, &chip
->oob_poi
[aligned_pos
], aligned_len
);
1097 for (i
= 0; i
< eccfrag_len
; i
++)
1098 chip
->buffers
->ecccode
[i
] = chip
->oob_poi
[eccpos
[i
+ index
]];
1100 p
= bufpoi
+ data_col_addr
;
1101 for (i
= 0; i
< eccfrag_len
; i
+= chip
->ecc
.bytes
, p
+= chip
->ecc
.size
) {
1104 stat
= chip
->ecc
.correct(mtd
, p
,
1105 &chip
->buffers
->ecccode
[i
], &chip
->buffers
->ecccalc
[i
]);
1107 mtd
->ecc_stats
.failed
++;
1109 mtd
->ecc_stats
.corrected
+= stat
;
1110 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1113 return max_bitflips
;
1117 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1118 * @mtd: mtd info structure
1119 * @chip: nand chip info structure
1120 * @buf: buffer to store read data
1121 * @oob_required: caller requires OOB data read to chip->oob_poi
1122 * @page: page number to read
1124 * Not for syndrome calculating ECC controllers which need a special oob layout.
1126 static int nand_read_page_hwecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1127 uint8_t *buf
, int oob_required
, int page
)
1129 int i
, eccsize
= chip
->ecc
.size
;
1130 int eccbytes
= chip
->ecc
.bytes
;
1131 int eccsteps
= chip
->ecc
.steps
;
1133 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1134 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
1135 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1136 unsigned int max_bitflips
= 0;
1138 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1139 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1140 chip
->read_buf(mtd
, p
, eccsize
);
1141 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1143 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1145 for (i
= 0; i
< chip
->ecc
.total
; i
++)
1146 ecc_code
[i
] = chip
->oob_poi
[eccpos
[i
]];
1148 eccsteps
= chip
->ecc
.steps
;
1151 for (i
= 0 ; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1154 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], &ecc_calc
[i
]);
1156 mtd
->ecc_stats
.failed
++;
1158 mtd
->ecc_stats
.corrected
+= stat
;
1159 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1162 return max_bitflips
;
1166 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1167 * @mtd: mtd info structure
1168 * @chip: nand chip info structure
1169 * @buf: buffer to store read data
1170 * @oob_required: caller requires OOB data read to chip->oob_poi
1171 * @page: page number to read
1173 * Hardware ECC for large page chips, require OOB to be read first. For this
1174 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1175 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1176 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1177 * the data area, by overwriting the NAND manufacturer bad block markings.
1179 static int nand_read_page_hwecc_oob_first(struct mtd_info
*mtd
,
1180 struct nand_chip
*chip
, uint8_t *buf
, int oob_required
, int page
)
1182 int i
, eccsize
= chip
->ecc
.size
;
1183 int eccbytes
= chip
->ecc
.bytes
;
1184 int eccsteps
= chip
->ecc
.steps
;
1186 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
1187 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1188 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1189 unsigned int max_bitflips
= 0;
1191 /* Read the OOB area first */
1192 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, 0, page
);
1193 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1194 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, 0, page
);
1196 for (i
= 0; i
< chip
->ecc
.total
; i
++)
1197 ecc_code
[i
] = chip
->oob_poi
[eccpos
[i
]];
1199 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1202 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1203 chip
->read_buf(mtd
, p
, eccsize
);
1204 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1206 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], NULL
);
1208 mtd
->ecc_stats
.failed
++;
1210 mtd
->ecc_stats
.corrected
+= stat
;
1211 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1214 return max_bitflips
;
1218 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1219 * @mtd: mtd info structure
1220 * @chip: nand chip info structure
1221 * @buf: buffer to store read data
1222 * @oob_required: caller requires OOB data read to chip->oob_poi
1223 * @page: page number to read
1225 * The hw generator calculates the error syndrome automatically. Therefore we
1226 * need a special oob layout and handling.
1228 static int nand_read_page_syndrome(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1229 uint8_t *buf
, int oob_required
, int page
)
1231 int i
, eccsize
= chip
->ecc
.size
;
1232 int eccbytes
= chip
->ecc
.bytes
;
1233 int eccsteps
= chip
->ecc
.steps
;
1235 uint8_t *oob
= chip
->oob_poi
;
1236 unsigned int max_bitflips
= 0;
1238 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1241 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1242 chip
->read_buf(mtd
, p
, eccsize
);
1244 if (chip
->ecc
.prepad
) {
1245 chip
->read_buf(mtd
, oob
, chip
->ecc
.prepad
);
1246 oob
+= chip
->ecc
.prepad
;
1249 chip
->ecc
.hwctl(mtd
, NAND_ECC_READSYN
);
1250 chip
->read_buf(mtd
, oob
, eccbytes
);
1251 stat
= chip
->ecc
.correct(mtd
, p
, oob
, NULL
);
1254 mtd
->ecc_stats
.failed
++;
1256 mtd
->ecc_stats
.corrected
+= stat
;
1257 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1262 if (chip
->ecc
.postpad
) {
1263 chip
->read_buf(mtd
, oob
, chip
->ecc
.postpad
);
1264 oob
+= chip
->ecc
.postpad
;
1268 /* Calculate remaining oob bytes */
1269 i
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
1271 chip
->read_buf(mtd
, oob
, i
);
1273 return max_bitflips
;
1277 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1278 * @chip: nand chip structure
1279 * @oob: oob destination address
1280 * @ops: oob ops structure
1281 * @len: size of oob to transfer
1283 static uint8_t *nand_transfer_oob(struct nand_chip
*chip
, uint8_t *oob
,
1284 struct mtd_oob_ops
*ops
, size_t len
)
1286 switch (ops
->mode
) {
1288 case MTD_OPS_PLACE_OOB
:
1290 memcpy(oob
, chip
->oob_poi
+ ops
->ooboffs
, len
);
1293 case MTD_OPS_AUTO_OOB
: {
1294 struct nand_oobfree
*free
= chip
->ecc
.layout
->oobfree
;
1295 uint32_t boffs
= 0, roffs
= ops
->ooboffs
;
1298 for (; free
->length
&& len
; free
++, len
-= bytes
) {
1299 /* Read request not from offset 0? */
1300 if (unlikely(roffs
)) {
1301 if (roffs
>= free
->length
) {
1302 roffs
-= free
->length
;
1305 boffs
= free
->offset
+ roffs
;
1306 bytes
= min_t(size_t, len
,
1307 (free
->length
- roffs
));
1310 bytes
= min_t(size_t, len
, free
->length
);
1311 boffs
= free
->offset
;
1313 memcpy(oob
, chip
->oob_poi
+ boffs
, bytes
);
1325 * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
1326 * @mtd: MTD device structure
1327 * @retry_mode: the retry mode to use
1329 * Some vendors supply a special command to shift the Vt threshold, to be used
1330 * when there are too many bitflips in a page (i.e., ECC error). After setting
1331 * a new threshold, the host should retry reading the page.
1333 static int nand_setup_read_retry(struct mtd_info
*mtd
, int retry_mode
)
1335 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1337 pr_debug("setting READ RETRY mode %d\n", retry_mode
);
1339 if (retry_mode
>= chip
->read_retries
)
1342 if (!chip
->setup_read_retry
)
1345 return chip
->setup_read_retry(mtd
, retry_mode
);
1349 * nand_do_read_ops - [INTERN] Read data with ECC
1350 * @mtd: MTD device structure
1351 * @from: offset to read from
1352 * @ops: oob ops structure
1354 * Internal function. Called with chip held.
1356 static int nand_do_read_ops(struct mtd_info
*mtd
, loff_t from
,
1357 struct mtd_oob_ops
*ops
)
1359 int chipnr
, page
, realpage
, col
, bytes
, aligned
, oob_required
;
1360 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1362 uint32_t readlen
= ops
->len
;
1363 uint32_t oobreadlen
= ops
->ooblen
;
1364 uint32_t max_oobsize
= ops
->mode
== MTD_OPS_AUTO_OOB
?
1365 mtd
->oobavail
: mtd
->oobsize
;
1367 uint8_t *bufpoi
, *oob
, *buf
;
1369 unsigned int max_bitflips
= 0;
1371 bool ecc_fail
= false;
1373 chipnr
= (int)(from
>> chip
->chip_shift
);
1374 chip
->select_chip(mtd
, chipnr
);
1376 realpage
= (int)(from
>> chip
->page_shift
);
1377 page
= realpage
& chip
->pagemask
;
1379 col
= (int)(from
& (mtd
->writesize
- 1));
1383 oob_required
= oob
? 1 : 0;
1386 unsigned int ecc_failures
= mtd
->ecc_stats
.failed
;
1389 bytes
= min(mtd
->writesize
- col
, readlen
);
1390 aligned
= (bytes
== mtd
->writesize
);
1397 /* Is the current page in the buffer? */
1398 if (realpage
!= chip
->pagebuf
|| oob
) {
1399 bufpoi
= use_bufpoi
? chip
->buffers
->databuf
: buf
;
1401 if (use_bufpoi
&& aligned
)
1402 pr_debug("%s: using read bounce buffer for buf@%p\n",
1406 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, 0x00, page
);
1409 * Now read the page into the buffer. Absent an error,
1410 * the read methods return max bitflips per ecc step.
1412 if (unlikely(ops
->mode
== MTD_OPS_RAW
))
1413 ret
= chip
->ecc
.read_page_raw(mtd
, chip
, bufpoi
,
1416 else if (!aligned
&& NAND_HAS_SUBPAGE_READ(chip
) &&
1418 ret
= chip
->ecc
.read_subpage(mtd
, chip
,
1422 ret
= chip
->ecc
.read_page(mtd
, chip
, bufpoi
,
1423 oob_required
, page
);
1426 /* Invalidate page cache */
1431 max_bitflips
= max_t(unsigned int, max_bitflips
, ret
);
1433 /* Transfer not aligned data */
1435 if (!NAND_HAS_SUBPAGE_READ(chip
) && !oob
&&
1436 !(mtd
->ecc_stats
.failed
- ecc_failures
) &&
1437 (ops
->mode
!= MTD_OPS_RAW
)) {
1438 chip
->pagebuf
= realpage
;
1439 chip
->pagebuf_bitflips
= ret
;
1441 /* Invalidate page cache */
1444 memcpy(buf
, chip
->buffers
->databuf
+ col
, bytes
);
1447 if (unlikely(oob
)) {
1448 int toread
= min(oobreadlen
, max_oobsize
);
1451 oob
= nand_transfer_oob(chip
,
1453 oobreadlen
-= toread
;
1457 if (chip
->options
& NAND_NEED_READRDY
) {
1458 /* Apply delay or wait for ready/busy pin */
1459 if (!chip
->dev_ready
)
1460 udelay(chip
->chip_delay
);
1462 nand_wait_ready(mtd
);
1465 if (mtd
->ecc_stats
.failed
- ecc_failures
) {
1466 if (retry_mode
+ 1 < chip
->read_retries
) {
1468 ret
= nand_setup_read_retry(mtd
,
1473 /* Reset failures; retry */
1474 mtd
->ecc_stats
.failed
= ecc_failures
;
1477 /* No more retry modes; real failure */
1484 memcpy(buf
, chip
->buffers
->databuf
+ col
, bytes
);
1486 max_bitflips
= max_t(unsigned int, max_bitflips
,
1487 chip
->pagebuf_bitflips
);
1492 /* Reset to retry mode 0 */
1494 ret
= nand_setup_read_retry(mtd
, 0);
1503 /* For subsequent reads align to page boundary */
1505 /* Increment page address */
1508 page
= realpage
& chip
->pagemask
;
1509 /* Check, if we cross a chip boundary */
1512 chip
->select_chip(mtd
, -1);
1513 chip
->select_chip(mtd
, chipnr
);
1516 chip
->select_chip(mtd
, -1);
1518 ops
->retlen
= ops
->len
- (size_t) readlen
;
1520 ops
->oobretlen
= ops
->ooblen
- oobreadlen
;
1528 return max_bitflips
;
1532 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1533 * @mtd: MTD device structure
1534 * @from: offset to read from
1535 * @len: number of bytes to read
1536 * @retlen: pointer to variable to store the number of read bytes
1537 * @buf: the databuffer to put data
1539 * Get hold of the chip and call nand_do_read.
1541 static int nand_read(struct mtd_info
*mtd
, loff_t from
, size_t len
,
1542 size_t *retlen
, uint8_t *buf
)
1544 struct mtd_oob_ops ops
;
1547 nand_get_device(mtd
, FL_READING
);
1548 memset(&ops
, 0, sizeof(ops
));
1551 ops
.mode
= MTD_OPS_PLACE_OOB
;
1552 ret
= nand_do_read_ops(mtd
, from
, &ops
);
1553 *retlen
= ops
.retlen
;
1554 nand_release_device(mtd
);
1559 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
1560 * @mtd: mtd info structure
1561 * @chip: nand chip info structure
1562 * @page: page number to read
1564 static int nand_read_oob_std(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1567 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, 0, page
);
1568 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1573 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
1575 * @mtd: mtd info structure
1576 * @chip: nand chip info structure
1577 * @page: page number to read
1579 static int nand_read_oob_syndrome(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1582 int length
= mtd
->oobsize
;
1583 int chunk
= chip
->ecc
.bytes
+ chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
1584 int eccsize
= chip
->ecc
.size
;
1585 uint8_t *bufpoi
= chip
->oob_poi
;
1586 int i
, toread
, sndrnd
= 0, pos
;
1588 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, chip
->ecc
.size
, page
);
1589 for (i
= 0; i
< chip
->ecc
.steps
; i
++) {
1591 pos
= eccsize
+ i
* (eccsize
+ chunk
);
1592 if (mtd
->writesize
> 512)
1593 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, pos
, -1);
1595 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, pos
, page
);
1598 toread
= min_t(int, length
, chunk
);
1599 chip
->read_buf(mtd
, bufpoi
, toread
);
1604 chip
->read_buf(mtd
, bufpoi
, length
);
1610 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
1611 * @mtd: mtd info structure
1612 * @chip: nand chip info structure
1613 * @page: page number to write
1615 static int nand_write_oob_std(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1619 const uint8_t *buf
= chip
->oob_poi
;
1620 int length
= mtd
->oobsize
;
1622 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, mtd
->writesize
, page
);
1623 chip
->write_buf(mtd
, buf
, length
);
1624 /* Send command to program the OOB data */
1625 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
1627 status
= chip
->waitfunc(mtd
, chip
);
1629 return status
& NAND_STATUS_FAIL
? -EIO
: 0;
1633 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
1634 * with syndrome - only for large page flash
1635 * @mtd: mtd info structure
1636 * @chip: nand chip info structure
1637 * @page: page number to write
1639 static int nand_write_oob_syndrome(struct mtd_info
*mtd
,
1640 struct nand_chip
*chip
, int page
)
1642 int chunk
= chip
->ecc
.bytes
+ chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
1643 int eccsize
= chip
->ecc
.size
, length
= mtd
->oobsize
;
1644 int i
, len
, pos
, status
= 0, sndcmd
= 0, steps
= chip
->ecc
.steps
;
1645 const uint8_t *bufpoi
= chip
->oob_poi
;
1648 * data-ecc-data-ecc ... ecc-oob
1650 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1652 if (!chip
->ecc
.prepad
&& !chip
->ecc
.postpad
) {
1653 pos
= steps
* (eccsize
+ chunk
);
1658 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, pos
, page
);
1659 for (i
= 0; i
< steps
; i
++) {
1661 if (mtd
->writesize
<= 512) {
1662 uint32_t fill
= 0xFFFFFFFF;
1666 int num
= min_t(int, len
, 4);
1667 chip
->write_buf(mtd
, (uint8_t *)&fill
,
1672 pos
= eccsize
+ i
* (eccsize
+ chunk
);
1673 chip
->cmdfunc(mtd
, NAND_CMD_RNDIN
, pos
, -1);
1677 len
= min_t(int, length
, chunk
);
1678 chip
->write_buf(mtd
, bufpoi
, len
);
1683 chip
->write_buf(mtd
, bufpoi
, length
);
1685 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
1686 status
= chip
->waitfunc(mtd
, chip
);
1688 return status
& NAND_STATUS_FAIL
? -EIO
: 0;
1692 * nand_do_read_oob - [INTERN] NAND read out-of-band
1693 * @mtd: MTD device structure
1694 * @from: offset to read from
1695 * @ops: oob operations description structure
1697 * NAND read out-of-band data from the spare area.
1699 static int nand_do_read_oob(struct mtd_info
*mtd
, loff_t from
,
1700 struct mtd_oob_ops
*ops
)
1702 int page
, realpage
, chipnr
;
1703 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1704 struct mtd_ecc_stats stats
;
1705 int readlen
= ops
->ooblen
;
1707 uint8_t *buf
= ops
->oobbuf
;
1710 pr_debug("%s: from = 0x%08Lx, len = %i\n",
1711 __func__
, (unsigned long long)from
, readlen
);
1713 stats
= mtd
->ecc_stats
;
1715 if (ops
->mode
== MTD_OPS_AUTO_OOB
)
1716 len
= chip
->ecc
.layout
->oobavail
;
1720 if (unlikely(ops
->ooboffs
>= len
)) {
1721 pr_debug("%s: attempt to start read outside oob\n",
1726 /* Do not allow reads past end of device */
1727 if (unlikely(from
>= mtd
->size
||
1728 ops
->ooboffs
+ readlen
> ((mtd
->size
>> chip
->page_shift
) -
1729 (from
>> chip
->page_shift
)) * len
)) {
1730 pr_debug("%s: attempt to read beyond end of device\n",
1735 chipnr
= (int)(from
>> chip
->chip_shift
);
1736 chip
->select_chip(mtd
, chipnr
);
1738 /* Shift to get page */
1739 realpage
= (int)(from
>> chip
->page_shift
);
1740 page
= realpage
& chip
->pagemask
;
1745 if (ops
->mode
== MTD_OPS_RAW
)
1746 ret
= chip
->ecc
.read_oob_raw(mtd
, chip
, page
);
1748 ret
= chip
->ecc
.read_oob(mtd
, chip
, page
);
1753 len
= min(len
, readlen
);
1754 buf
= nand_transfer_oob(chip
, buf
, ops
, len
);
1756 if (chip
->options
& NAND_NEED_READRDY
) {
1757 /* Apply delay or wait for ready/busy pin */
1758 if (!chip
->dev_ready
)
1759 udelay(chip
->chip_delay
);
1761 nand_wait_ready(mtd
);
1768 /* Increment page address */
1771 page
= realpage
& chip
->pagemask
;
1772 /* Check, if we cross a chip boundary */
1775 chip
->select_chip(mtd
, -1);
1776 chip
->select_chip(mtd
, chipnr
);
1779 chip
->select_chip(mtd
, -1);
1781 ops
->oobretlen
= ops
->ooblen
- readlen
;
1786 if (mtd
->ecc_stats
.failed
- stats
.failed
)
1789 return mtd
->ecc_stats
.corrected
- stats
.corrected
? -EUCLEAN
: 0;
1793 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1794 * @mtd: MTD device structure
1795 * @from: offset to read from
1796 * @ops: oob operation description structure
1798 * NAND read data and/or out-of-band data.
1800 static int nand_read_oob(struct mtd_info
*mtd
, loff_t from
,
1801 struct mtd_oob_ops
*ops
)
1803 int ret
= -ENOTSUPP
;
1807 /* Do not allow reads past end of device */
1808 if (ops
->datbuf
&& (from
+ ops
->len
) > mtd
->size
) {
1809 pr_debug("%s: attempt to read beyond end of device\n",
1814 nand_get_device(mtd
, FL_READING
);
1816 switch (ops
->mode
) {
1817 case MTD_OPS_PLACE_OOB
:
1818 case MTD_OPS_AUTO_OOB
:
1827 ret
= nand_do_read_oob(mtd
, from
, ops
);
1829 ret
= nand_do_read_ops(mtd
, from
, ops
);
1832 nand_release_device(mtd
);
1838 * nand_write_page_raw - [INTERN] raw page write function
1839 * @mtd: mtd info structure
1840 * @chip: nand chip info structure
1842 * @oob_required: must write chip->oob_poi to OOB
1843 * @page: page number to write
1845 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1847 static int nand_write_page_raw(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1848 const uint8_t *buf
, int oob_required
,
1851 chip
->write_buf(mtd
, buf
, mtd
->writesize
);
1853 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1859 * nand_write_page_raw_syndrome - [INTERN] raw page write function
1860 * @mtd: mtd info structure
1861 * @chip: nand chip info structure
1863 * @oob_required: must write chip->oob_poi to OOB
1865 * We need a special oob layout and handling even when ECC isn't checked.
1867 static int nand_write_page_raw_syndrome(struct mtd_info
*mtd
,
1868 struct nand_chip
*chip
,
1869 const uint8_t *buf
, int oob_required
,
1872 int eccsize
= chip
->ecc
.size
;
1873 int eccbytes
= chip
->ecc
.bytes
;
1874 uint8_t *oob
= chip
->oob_poi
;
1877 for (steps
= chip
->ecc
.steps
; steps
> 0; steps
--) {
1878 chip
->write_buf(mtd
, buf
, eccsize
);
1881 if (chip
->ecc
.prepad
) {
1882 chip
->write_buf(mtd
, oob
, chip
->ecc
.prepad
);
1883 oob
+= chip
->ecc
.prepad
;
1886 chip
->write_buf(mtd
, oob
, eccbytes
);
1889 if (chip
->ecc
.postpad
) {
1890 chip
->write_buf(mtd
, oob
, chip
->ecc
.postpad
);
1891 oob
+= chip
->ecc
.postpad
;
1895 size
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
1897 chip
->write_buf(mtd
, oob
, size
);
1902 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
1903 * @mtd: mtd info structure
1904 * @chip: nand chip info structure
1906 * @oob_required: must write chip->oob_poi to OOB
1907 * @page: page number to write
1909 static int nand_write_page_swecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1910 const uint8_t *buf
, int oob_required
,
1913 int i
, eccsize
= chip
->ecc
.size
;
1914 int eccbytes
= chip
->ecc
.bytes
;
1915 int eccsteps
= chip
->ecc
.steps
;
1916 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1917 const uint8_t *p
= buf
;
1918 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1920 /* Software ECC calculation */
1921 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
)
1922 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1924 for (i
= 0; i
< chip
->ecc
.total
; i
++)
1925 chip
->oob_poi
[eccpos
[i
]] = ecc_calc
[i
];
1927 return chip
->ecc
.write_page_raw(mtd
, chip
, buf
, 1, page
);
1931 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
1932 * @mtd: mtd info structure
1933 * @chip: nand chip info structure
1935 * @oob_required: must write chip->oob_poi to OOB
1936 * @page: page number to write
1938 static int nand_write_page_hwecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1939 const uint8_t *buf
, int oob_required
,
1942 int i
, eccsize
= chip
->ecc
.size
;
1943 int eccbytes
= chip
->ecc
.bytes
;
1944 int eccsteps
= chip
->ecc
.steps
;
1945 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1946 const uint8_t *p
= buf
;
1947 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1949 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1950 chip
->ecc
.hwctl(mtd
, NAND_ECC_WRITE
);
1951 chip
->write_buf(mtd
, p
, eccsize
);
1952 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1955 for (i
= 0; i
< chip
->ecc
.total
; i
++)
1956 chip
->oob_poi
[eccpos
[i
]] = ecc_calc
[i
];
1958 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1965 * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write
1966 * @mtd: mtd info structure
1967 * @chip: nand chip info structure
1968 * @offset: column address of subpage within the page
1969 * @data_len: data length
1971 * @oob_required: must write chip->oob_poi to OOB
1972 * @page: page number to write
1974 static int nand_write_subpage_hwecc(struct mtd_info
*mtd
,
1975 struct nand_chip
*chip
, uint32_t offset
,
1976 uint32_t data_len
, const uint8_t *buf
,
1977 int oob_required
, int page
)
1979 uint8_t *oob_buf
= chip
->oob_poi
;
1980 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1981 int ecc_size
= chip
->ecc
.size
;
1982 int ecc_bytes
= chip
->ecc
.bytes
;
1983 int ecc_steps
= chip
->ecc
.steps
;
1984 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1985 uint32_t start_step
= offset
/ ecc_size
;
1986 uint32_t end_step
= (offset
+ data_len
- 1) / ecc_size
;
1987 int oob_bytes
= mtd
->oobsize
/ ecc_steps
;
1990 for (step
= 0; step
< ecc_steps
; step
++) {
1991 /* configure controller for WRITE access */
1992 chip
->ecc
.hwctl(mtd
, NAND_ECC_WRITE
);
1994 /* write data (untouched subpages already masked by 0xFF) */
1995 chip
->write_buf(mtd
, buf
, ecc_size
);
1997 /* mask ECC of un-touched subpages by padding 0xFF */
1998 if ((step
< start_step
) || (step
> end_step
))
1999 memset(ecc_calc
, 0xff, ecc_bytes
);
2001 chip
->ecc
.calculate(mtd
, buf
, ecc_calc
);
2003 /* mask OOB of un-touched subpages by padding 0xFF */
2004 /* if oob_required, preserve OOB metadata of written subpage */
2005 if (!oob_required
|| (step
< start_step
) || (step
> end_step
))
2006 memset(oob_buf
, 0xff, oob_bytes
);
2009 ecc_calc
+= ecc_bytes
;
2010 oob_buf
+= oob_bytes
;
2013 /* copy calculated ECC for whole page to chip->buffer->oob */
2014 /* this include masked-value(0xFF) for unwritten subpages */
2015 ecc_calc
= chip
->buffers
->ecccalc
;
2016 for (i
= 0; i
< chip
->ecc
.total
; i
++)
2017 chip
->oob_poi
[eccpos
[i
]] = ecc_calc
[i
];
2019 /* write OOB buffer to NAND device */
2020 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
2027 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
2028 * @mtd: mtd info structure
2029 * @chip: nand chip info structure
2031 * @oob_required: must write chip->oob_poi to OOB
2033 * The hw generator calculates the error syndrome automatically. Therefore we
2034 * need a special oob layout and handling.
2036 static int nand_write_page_syndrome(struct mtd_info
*mtd
,
2037 struct nand_chip
*chip
,
2038 const uint8_t *buf
, int oob_required
,
2041 int i
, eccsize
= chip
->ecc
.size
;
2042 int eccbytes
= chip
->ecc
.bytes
;
2043 int eccsteps
= chip
->ecc
.steps
;
2044 const uint8_t *p
= buf
;
2045 uint8_t *oob
= chip
->oob_poi
;
2047 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
2049 chip
->ecc
.hwctl(mtd
, NAND_ECC_WRITE
);
2050 chip
->write_buf(mtd
, p
, eccsize
);
2052 if (chip
->ecc
.prepad
) {
2053 chip
->write_buf(mtd
, oob
, chip
->ecc
.prepad
);
2054 oob
+= chip
->ecc
.prepad
;
2057 chip
->ecc
.calculate(mtd
, p
, oob
);
2058 chip
->write_buf(mtd
, oob
, eccbytes
);
2061 if (chip
->ecc
.postpad
) {
2062 chip
->write_buf(mtd
, oob
, chip
->ecc
.postpad
);
2063 oob
+= chip
->ecc
.postpad
;
2067 /* Calculate remaining oob bytes */
2068 i
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
2070 chip
->write_buf(mtd
, oob
, i
);
2076 * nand_write_page - [REPLACEABLE] write one page
2077 * @mtd: MTD device structure
2078 * @chip: NAND chip descriptor
2079 * @offset: address offset within the page
2080 * @data_len: length of actual data to be written
2081 * @buf: the data to write
2082 * @oob_required: must write chip->oob_poi to OOB
2083 * @page: page number to write
2084 * @cached: cached programming
2085 * @raw: use _raw version of write_page
2087 static int nand_write_page(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2088 uint32_t offset
, int data_len
, const uint8_t *buf
,
2089 int oob_required
, int page
, int cached
, int raw
)
2091 int status
, subpage
;
2093 if (!(chip
->options
& NAND_NO_SUBPAGE_WRITE
) &&
2094 chip
->ecc
.write_subpage
)
2095 subpage
= offset
|| (data_len
< mtd
->writesize
);
2099 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, 0x00, page
);
2102 status
= chip
->ecc
.write_page_raw(mtd
, chip
, buf
,
2103 oob_required
, page
);
2105 status
= chip
->ecc
.write_subpage(mtd
, chip
, offset
, data_len
,
2106 buf
, oob_required
, page
);
2108 status
= chip
->ecc
.write_page(mtd
, chip
, buf
, oob_required
,
2115 * Cached progamming disabled for now. Not sure if it's worth the
2116 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
2120 if (!cached
|| !NAND_HAS_CACHEPROG(chip
)) {
2122 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
2123 status
= chip
->waitfunc(mtd
, chip
);
2125 * See if operation failed and additional status checks are
2128 if ((status
& NAND_STATUS_FAIL
) && (chip
->errstat
))
2129 status
= chip
->errstat(mtd
, chip
, FL_WRITING
, status
,
2132 if (status
& NAND_STATUS_FAIL
)
2135 chip
->cmdfunc(mtd
, NAND_CMD_CACHEDPROG
, -1, -1);
2136 status
= chip
->waitfunc(mtd
, chip
);
2143 * nand_fill_oob - [INTERN] Transfer client buffer to oob
2144 * @mtd: MTD device structure
2145 * @oob: oob data buffer
2146 * @len: oob data write length
2147 * @ops: oob ops structure
2148 * @page: page number to write
2150 static uint8_t *nand_fill_oob(struct mtd_info
*mtd
, uint8_t *oob
, size_t len
,
2151 struct mtd_oob_ops
*ops
)
2153 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2156 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2157 * data from a previous OOB read.
2159 memset(chip
->oob_poi
, 0xff, mtd
->oobsize
);
2161 switch (ops
->mode
) {
2163 case MTD_OPS_PLACE_OOB
:
2165 memcpy(chip
->oob_poi
+ ops
->ooboffs
, oob
, len
);
2168 case MTD_OPS_AUTO_OOB
: {
2169 struct nand_oobfree
*free
= chip
->ecc
.layout
->oobfree
;
2170 uint32_t boffs
= 0, woffs
= ops
->ooboffs
;
2173 for (; free
->length
&& len
; free
++, len
-= bytes
) {
2174 /* Write request not from offset 0? */
2175 if (unlikely(woffs
)) {
2176 if (woffs
>= free
->length
) {
2177 woffs
-= free
->length
;
2180 boffs
= free
->offset
+ woffs
;
2181 bytes
= min_t(size_t, len
,
2182 (free
->length
- woffs
));
2185 bytes
= min_t(size_t, len
, free
->length
);
2186 boffs
= free
->offset
;
2188 memcpy(chip
->oob_poi
+ boffs
, oob
, bytes
);
2199 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
2202 * nand_do_write_ops - [INTERN] NAND write with ECC
2203 * @mtd: MTD device structure
2204 * @to: offset to write to
2205 * @ops: oob operations description structure
2207 * NAND write with ECC.
2209 static int nand_do_write_ops(struct mtd_info
*mtd
, loff_t to
,
2210 struct mtd_oob_ops
*ops
)
2212 int chipnr
, realpage
, page
, blockmask
, column
;
2213 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2214 uint32_t writelen
= ops
->len
;
2216 uint32_t oobwritelen
= ops
->ooblen
;
2217 uint32_t oobmaxlen
= ops
->mode
== MTD_OPS_AUTO_OOB
?
2218 mtd
->oobavail
: mtd
->oobsize
;
2220 uint8_t *oob
= ops
->oobbuf
;
2221 uint8_t *buf
= ops
->datbuf
;
2223 int oob_required
= oob
? 1 : 0;
2229 /* Reject writes, which are not page aligned */
2230 if (NOTALIGNED(to
)) {
2231 pr_notice("%s: attempt to write non page aligned data\n",
2236 column
= to
& (mtd
->writesize
- 1);
2238 chipnr
= (int)(to
>> chip
->chip_shift
);
2239 chip
->select_chip(mtd
, chipnr
);
2241 /* Check, if it is write protected */
2242 if (nand_check_wp(mtd
)) {
2247 realpage
= (int)(to
>> chip
->page_shift
);
2248 page
= realpage
& chip
->pagemask
;
2249 blockmask
= (1 << (chip
->phys_erase_shift
- chip
->page_shift
)) - 1;
2251 /* Invalidate the page cache, when we write to the cached page */
2252 if (to
<= ((loff_t
)chip
->pagebuf
<< chip
->page_shift
) &&
2253 ((loff_t
)chip
->pagebuf
<< chip
->page_shift
) < (to
+ ops
->len
))
2256 /* Don't allow multipage oob writes with offset */
2257 if (oob
&& ops
->ooboffs
&& (ops
->ooboffs
+ ops
->ooblen
> oobmaxlen
)) {
2263 int bytes
= mtd
->writesize
;
2264 int cached
= writelen
> bytes
&& page
!= blockmask
;
2265 uint8_t *wbuf
= buf
;
2267 int part_pagewr
= (column
|| writelen
< (mtd
->writesize
- 1));
2275 /* Partial page write?, or need to use bounce buffer */
2277 pr_debug("%s: using write bounce buffer for buf@%p\n",
2281 bytes
= min_t(int, bytes
- column
, writelen
);
2283 memset(chip
->buffers
->databuf
, 0xff, mtd
->writesize
);
2284 memcpy(&chip
->buffers
->databuf
[column
], buf
, bytes
);
2285 wbuf
= chip
->buffers
->databuf
;
2288 if (unlikely(oob
)) {
2289 size_t len
= min(oobwritelen
, oobmaxlen
);
2290 oob
= nand_fill_oob(mtd
, oob
, len
, ops
);
2293 /* We still need to erase leftover OOB data */
2294 memset(chip
->oob_poi
, 0xff, mtd
->oobsize
);
2296 ret
= chip
->write_page(mtd
, chip
, column
, bytes
, wbuf
,
2297 oob_required
, page
, cached
,
2298 (ops
->mode
== MTD_OPS_RAW
));
2310 page
= realpage
& chip
->pagemask
;
2311 /* Check, if we cross a chip boundary */
2314 chip
->select_chip(mtd
, -1);
2315 chip
->select_chip(mtd
, chipnr
);
2319 ops
->retlen
= ops
->len
- writelen
;
2321 ops
->oobretlen
= ops
->ooblen
;
2324 chip
->select_chip(mtd
, -1);
2329 * panic_nand_write - [MTD Interface] NAND write with ECC
2330 * @mtd: MTD device structure
2331 * @to: offset to write to
2332 * @len: number of bytes to write
2333 * @retlen: pointer to variable to store the number of written bytes
2334 * @buf: the data to write
2336 * NAND write with ECC. Used when performing writes in interrupt context, this
2337 * may for example be called by mtdoops when writing an oops while in panic.
2339 static int panic_nand_write(struct mtd_info
*mtd
, loff_t to
, size_t len
,
2340 size_t *retlen
, const uint8_t *buf
)
2342 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2343 struct mtd_oob_ops ops
;
2346 /* Wait for the device to get ready */
2347 panic_nand_wait(mtd
, chip
, 400);
2349 /* Grab the device */
2350 panic_nand_get_device(chip
, mtd
, FL_WRITING
);
2352 memset(&ops
, 0, sizeof(ops
));
2354 ops
.datbuf
= (uint8_t *)buf
;
2355 ops
.mode
= MTD_OPS_PLACE_OOB
;
2357 ret
= nand_do_write_ops(mtd
, to
, &ops
);
2359 *retlen
= ops
.retlen
;
2364 * nand_write - [MTD Interface] NAND write with ECC
2365 * @mtd: MTD device structure
2366 * @to: offset to write to
2367 * @len: number of bytes to write
2368 * @retlen: pointer to variable to store the number of written bytes
2369 * @buf: the data to write
2371 * NAND write with ECC.
2373 static int nand_write(struct mtd_info
*mtd
, loff_t to
, size_t len
,
2374 size_t *retlen
, const uint8_t *buf
)
2376 struct mtd_oob_ops ops
;
2379 nand_get_device(mtd
, FL_WRITING
);
2380 memset(&ops
, 0, sizeof(ops
));
2382 ops
.datbuf
= (uint8_t *)buf
;
2383 ops
.mode
= MTD_OPS_PLACE_OOB
;
2384 ret
= nand_do_write_ops(mtd
, to
, &ops
);
2385 *retlen
= ops
.retlen
;
2386 nand_release_device(mtd
);
2391 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2392 * @mtd: MTD device structure
2393 * @to: offset to write to
2394 * @ops: oob operation description structure
2396 * NAND write out-of-band.
2398 static int nand_do_write_oob(struct mtd_info
*mtd
, loff_t to
,
2399 struct mtd_oob_ops
*ops
)
2401 int chipnr
, page
, status
, len
;
2402 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2404 pr_debug("%s: to = 0x%08x, len = %i\n",
2405 __func__
, (unsigned int)to
, (int)ops
->ooblen
);
2407 if (ops
->mode
== MTD_OPS_AUTO_OOB
)
2408 len
= chip
->ecc
.layout
->oobavail
;
2412 /* Do not allow write past end of page */
2413 if ((ops
->ooboffs
+ ops
->ooblen
) > len
) {
2414 pr_debug("%s: attempt to write past end of page\n",
2419 if (unlikely(ops
->ooboffs
>= len
)) {
2420 pr_debug("%s: attempt to start write outside oob\n",
2425 /* Do not allow write past end of device */
2426 if (unlikely(to
>= mtd
->size
||
2427 ops
->ooboffs
+ ops
->ooblen
>
2428 ((mtd
->size
>> chip
->page_shift
) -
2429 (to
>> chip
->page_shift
)) * len
)) {
2430 pr_debug("%s: attempt to write beyond end of device\n",
2435 chipnr
= (int)(to
>> chip
->chip_shift
);
2436 chip
->select_chip(mtd
, chipnr
);
2438 /* Shift to get page */
2439 page
= (int)(to
>> chip
->page_shift
);
2442 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2443 * of my DiskOnChip 2000 test units) will clear the whole data page too
2444 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2445 * it in the doc2000 driver in August 1999. dwmw2.
2447 chip
->cmdfunc(mtd
, NAND_CMD_RESET
, -1, -1);
2449 /* Check, if it is write protected */
2450 if (nand_check_wp(mtd
)) {
2451 chip
->select_chip(mtd
, -1);
2455 /* Invalidate the page cache, if we write to the cached page */
2456 if (page
== chip
->pagebuf
)
2459 nand_fill_oob(mtd
, ops
->oobbuf
, ops
->ooblen
, ops
);
2461 if (ops
->mode
== MTD_OPS_RAW
)
2462 status
= chip
->ecc
.write_oob_raw(mtd
, chip
, page
& chip
->pagemask
);
2464 status
= chip
->ecc
.write_oob(mtd
, chip
, page
& chip
->pagemask
);
2466 chip
->select_chip(mtd
, -1);
2471 ops
->oobretlen
= ops
->ooblen
;
2477 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2478 * @mtd: MTD device structure
2479 * @to: offset to write to
2480 * @ops: oob operation description structure
2482 static int nand_write_oob(struct mtd_info
*mtd
, loff_t to
,
2483 struct mtd_oob_ops
*ops
)
2485 int ret
= -ENOTSUPP
;
2489 /* Do not allow writes past end of device */
2490 if (ops
->datbuf
&& (to
+ ops
->len
) > mtd
->size
) {
2491 pr_debug("%s: attempt to write beyond end of device\n",
2496 nand_get_device(mtd
, FL_WRITING
);
2498 switch (ops
->mode
) {
2499 case MTD_OPS_PLACE_OOB
:
2500 case MTD_OPS_AUTO_OOB
:
2509 ret
= nand_do_write_oob(mtd
, to
, ops
);
2511 ret
= nand_do_write_ops(mtd
, to
, ops
);
2514 nand_release_device(mtd
);
2519 * single_erase - [GENERIC] NAND standard block erase command function
2520 * @mtd: MTD device structure
2521 * @page: the page address of the block which will be erased
2523 * Standard erase command for NAND chips. Returns NAND status.
2525 static int single_erase(struct mtd_info
*mtd
, int page
)
2527 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2528 /* Send commands to erase a block */
2529 chip
->cmdfunc(mtd
, NAND_CMD_ERASE1
, -1, page
);
2530 chip
->cmdfunc(mtd
, NAND_CMD_ERASE2
, -1, -1);
2532 return chip
->waitfunc(mtd
, chip
);
2536 * nand_erase - [MTD Interface] erase block(s)
2537 * @mtd: MTD device structure
2538 * @instr: erase instruction
2540 * Erase one ore more blocks.
2542 static int nand_erase(struct mtd_info
*mtd
, struct erase_info
*instr
)
2544 return nand_erase_nand(mtd
, instr
, 0);
2548 * nand_erase_nand - [INTERN] erase block(s)
2549 * @mtd: MTD device structure
2550 * @instr: erase instruction
2551 * @allowbbt: allow erasing the bbt area
2553 * Erase one ore more blocks.
2555 int nand_erase_nand(struct mtd_info
*mtd
, struct erase_info
*instr
,
2558 int page
, status
, pages_per_block
, ret
, chipnr
;
2559 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2562 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2563 __func__
, (unsigned long long)instr
->addr
,
2564 (unsigned long long)instr
->len
);
2566 if (check_offs_len(mtd
, instr
->addr
, instr
->len
))
2569 /* Grab the lock and see if the device is available */
2570 nand_get_device(mtd
, FL_ERASING
);
2572 /* Shift to get first page */
2573 page
= (int)(instr
->addr
>> chip
->page_shift
);
2574 chipnr
= (int)(instr
->addr
>> chip
->chip_shift
);
2576 /* Calculate pages in each block */
2577 pages_per_block
= 1 << (chip
->phys_erase_shift
- chip
->page_shift
);
2579 /* Select the NAND device */
2580 chip
->select_chip(mtd
, chipnr
);
2582 /* Check, if it is write protected */
2583 if (nand_check_wp(mtd
)) {
2584 pr_debug("%s: device is write protected!\n",
2586 instr
->state
= MTD_ERASE_FAILED
;
2590 /* Loop through the pages */
2593 instr
->state
= MTD_ERASING
;
2598 /* Check if we have a bad block, we do not erase bad blocks! */
2599 if (!instr
->scrub
&& nand_block_checkbad(mtd
, ((loff_t
) page
) <<
2600 chip
->page_shift
, 0, allowbbt
)) {
2601 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2603 instr
->state
= MTD_ERASE_FAILED
;
2608 * Invalidate the page cache, if we erase the block which
2609 * contains the current cached page.
2611 if (page
<= chip
->pagebuf
&& chip
->pagebuf
<
2612 (page
+ pages_per_block
))
2615 status
= chip
->erase(mtd
, page
& chip
->pagemask
);
2618 * See if operation failed and additional status checks are
2621 if ((status
& NAND_STATUS_FAIL
) && (chip
->errstat
))
2622 status
= chip
->errstat(mtd
, chip
, FL_ERASING
,
2625 /* See if block erase succeeded */
2626 if (status
& NAND_STATUS_FAIL
) {
2627 pr_debug("%s: failed erase, page 0x%08x\n",
2629 instr
->state
= MTD_ERASE_FAILED
;
2631 ((loff_t
)page
<< chip
->page_shift
);
2635 /* Increment page address and decrement length */
2636 len
-= (1ULL << chip
->phys_erase_shift
);
2637 page
+= pages_per_block
;
2639 /* Check, if we cross a chip boundary */
2640 if (len
&& !(page
& chip
->pagemask
)) {
2642 chip
->select_chip(mtd
, -1);
2643 chip
->select_chip(mtd
, chipnr
);
2646 instr
->state
= MTD_ERASE_DONE
;
2650 ret
= instr
->state
== MTD_ERASE_DONE
? 0 : -EIO
;
2652 /* Deselect and wake up anyone waiting on the device */
2653 chip
->select_chip(mtd
, -1);
2654 nand_release_device(mtd
);
2656 /* Do call back function */
2658 mtd_erase_callback(instr
);
2660 /* Return more or less happy */
2665 * nand_sync - [MTD Interface] sync
2666 * @mtd: MTD device structure
2668 * Sync is actually a wait for chip ready function.
2670 static void nand_sync(struct mtd_info
*mtd
)
2672 pr_debug("%s: called\n", __func__
);
2674 /* Grab the lock and see if the device is available */
2675 nand_get_device(mtd
, FL_SYNCING
);
2676 /* Release it and go back */
2677 nand_release_device(mtd
);
2681 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2682 * @mtd: MTD device structure
2683 * @offs: offset relative to mtd start
2685 static int nand_block_isbad(struct mtd_info
*mtd
, loff_t offs
)
2687 return nand_block_checkbad(mtd
, offs
, 1, 0);
2691 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2692 * @mtd: MTD device structure
2693 * @ofs: offset relative to mtd start
2695 static int nand_block_markbad(struct mtd_info
*mtd
, loff_t ofs
)
2699 ret
= nand_block_isbad(mtd
, ofs
);
2701 /* If it was bad already, return success and do nothing */
2707 return nand_block_markbad_lowlevel(mtd
, ofs
);
2711 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
2712 * @mtd: MTD device structure
2713 * @chip: nand chip info structure
2714 * @addr: feature address.
2715 * @subfeature_param: the subfeature parameters, a four bytes array.
2717 static int nand_onfi_set_features(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2718 int addr
, uint8_t *subfeature_param
)
2723 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
2724 if (!chip
->onfi_version
||
2725 !(le16_to_cpu(chip
->onfi_params
.opt_cmd
)
2726 & ONFI_OPT_CMD_SET_GET_FEATURES
))
2730 chip
->cmdfunc(mtd
, NAND_CMD_SET_FEATURES
, addr
, -1);
2731 for (i
= 0; i
< ONFI_SUBFEATURE_PARAM_LEN
; ++i
)
2732 chip
->write_byte(mtd
, subfeature_param
[i
]);
2734 status
= chip
->waitfunc(mtd
, chip
);
2735 if (status
& NAND_STATUS_FAIL
)
2741 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
2742 * @mtd: MTD device structure
2743 * @chip: nand chip info structure
2744 * @addr: feature address.
2745 * @subfeature_param: the subfeature parameters, a four bytes array.
2747 static int nand_onfi_get_features(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2748 int addr
, uint8_t *subfeature_param
)
2752 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
2753 if (!chip
->onfi_version
||
2754 !(le16_to_cpu(chip
->onfi_params
.opt_cmd
)
2755 & ONFI_OPT_CMD_SET_GET_FEATURES
))
2759 /* clear the sub feature parameters */
2760 memset(subfeature_param
, 0, ONFI_SUBFEATURE_PARAM_LEN
);
2762 chip
->cmdfunc(mtd
, NAND_CMD_GET_FEATURES
, addr
, -1);
2763 for (i
= 0; i
< ONFI_SUBFEATURE_PARAM_LEN
; ++i
)
2764 *subfeature_param
++ = chip
->read_byte(mtd
);
2768 /* Set default functions */
2769 static void nand_set_defaults(struct nand_chip
*chip
, int busw
)
2771 /* check for proper chip_delay setup, set 20us if not */
2772 if (!chip
->chip_delay
)
2773 chip
->chip_delay
= 20;
2775 /* check, if a user supplied command function given */
2776 if (chip
->cmdfunc
== NULL
)
2777 chip
->cmdfunc
= nand_command
;
2779 /* check, if a user supplied wait function given */
2780 if (chip
->waitfunc
== NULL
)
2781 chip
->waitfunc
= nand_wait
;
2783 if (!chip
->select_chip
)
2784 chip
->select_chip
= nand_select_chip
;
2786 /* set for ONFI nand */
2787 if (!chip
->onfi_set_features
)
2788 chip
->onfi_set_features
= nand_onfi_set_features
;
2789 if (!chip
->onfi_get_features
)
2790 chip
->onfi_get_features
= nand_onfi_get_features
;
2792 /* If called twice, pointers that depend on busw may need to be reset */
2793 if (!chip
->read_byte
|| chip
->read_byte
== nand_read_byte
)
2794 chip
->read_byte
= busw
? nand_read_byte16
: nand_read_byte
;
2795 if (!chip
->read_word
)
2796 chip
->read_word
= nand_read_word
;
2797 if (!chip
->block_bad
)
2798 chip
->block_bad
= nand_block_bad
;
2799 if (!chip
->block_markbad
)
2800 chip
->block_markbad
= nand_default_block_markbad
;
2801 if (!chip
->write_buf
|| chip
->write_buf
== nand_write_buf
)
2802 chip
->write_buf
= busw
? nand_write_buf16
: nand_write_buf
;
2803 if (!chip
->write_byte
|| chip
->write_byte
== nand_write_byte
)
2804 chip
->write_byte
= busw
? nand_write_byte16
: nand_write_byte
;
2805 if (!chip
->read_buf
|| chip
->read_buf
== nand_read_buf
)
2806 chip
->read_buf
= busw
? nand_read_buf16
: nand_read_buf
;
2807 if (!chip
->scan_bbt
)
2808 chip
->scan_bbt
= nand_default_bbt
;
2810 if (!chip
->controller
) {
2811 chip
->controller
= &chip
->hwcontrol
;
2812 spin_lock_init(&chip
->controller
->lock
);
2813 init_waitqueue_head(&chip
->controller
->wq
);
2818 /* Sanitize ONFI strings so we can safely print them */
2819 static void sanitize_string(char *s
, size_t len
)
2823 /* Null terminate */
2826 /* Remove non printable chars */
2827 for (i
= 0; i
< len
- 1; i
++) {
2828 if (s
[i
] < ' ' || s
[i
] > 127)
2832 /* Remove trailing spaces */
2836 static u16
onfi_crc16(u16 crc
, u8
const *p
, size_t len
)
2841 for (i
= 0; i
< 8; i
++)
2842 crc
= (crc
<< 1) ^ ((crc
& 0x8000) ? 0x8005 : 0);
2848 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
2849 /* Parse the Extended Parameter Page. */
2850 static int nand_flash_detect_ext_param_page(struct mtd_info
*mtd
,
2851 struct nand_chip
*chip
, struct nand_onfi_params
*p
)
2853 struct onfi_ext_param_page
*ep
;
2854 struct onfi_ext_section
*s
;
2855 struct onfi_ext_ecc_info
*ecc
;
2861 len
= le16_to_cpu(p
->ext_param_page_length
) * 16;
2862 ep
= kmalloc(len
, GFP_KERNEL
);
2866 /* Send our own NAND_CMD_PARAM. */
2867 chip
->cmdfunc(mtd
, NAND_CMD_PARAM
, 0, -1);
2869 /* Use the Change Read Column command to skip the ONFI param pages. */
2870 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
,
2871 sizeof(*p
) * p
->num_of_param_pages
, -1);
2873 /* Read out the Extended Parameter Page. */
2874 chip
->read_buf(mtd
, (uint8_t *)ep
, len
);
2875 if ((onfi_crc16(ONFI_CRC_BASE
, ((uint8_t *)ep
) + 2, len
- 2)
2876 != le16_to_cpu(ep
->crc
))) {
2877 pr_debug("fail in the CRC.\n");
2882 * Check the signature.
2883 * Do not strictly follow the ONFI spec, maybe changed in future.
2885 if (strncmp((char *)ep
->sig
, "EPPS", 4)) {
2886 pr_debug("The signature is invalid.\n");
2890 /* find the ECC section. */
2891 cursor
= (uint8_t *)(ep
+ 1);
2892 for (i
= 0; i
< ONFI_EXT_SECTION_MAX
; i
++) {
2893 s
= ep
->sections
+ i
;
2894 if (s
->type
== ONFI_SECTION_TYPE_2
)
2896 cursor
+= s
->length
* 16;
2898 if (i
== ONFI_EXT_SECTION_MAX
) {
2899 pr_debug("We can not find the ECC section.\n");
2903 /* get the info we want. */
2904 ecc
= (struct onfi_ext_ecc_info
*)cursor
;
2906 if (!ecc
->codeword_size
) {
2907 pr_debug("Invalid codeword size\n");
2911 chip
->ecc_strength_ds
= ecc
->ecc_bits
;
2912 chip
->ecc_step_ds
= 1 << ecc
->codeword_size
;
2920 static int nand_setup_read_retry_micron(struct mtd_info
*mtd
, int retry_mode
)
2922 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2923 uint8_t feature
[ONFI_SUBFEATURE_PARAM_LEN
] = {retry_mode
};
2925 return chip
->onfi_set_features(mtd
, chip
, ONFI_FEATURE_ADDR_READ_RETRY
,
2930 * Configure chip properties from Micron vendor-specific ONFI table
2932 static void nand_onfi_detect_micron(struct nand_chip
*chip
,
2933 struct nand_onfi_params
*p
)
2935 struct nand_onfi_vendor_micron
*micron
= (void *)p
->vendor
;
2937 if (le16_to_cpu(p
->vendor_revision
) < 1)
2940 chip
->read_retries
= micron
->read_retry_options
;
2941 chip
->setup_read_retry
= nand_setup_read_retry_micron
;
2945 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
2947 static int nand_flash_detect_onfi(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2950 struct nand_onfi_params
*p
= &chip
->onfi_params
;
2954 /* Try ONFI for unknown chip or LP */
2955 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x20, -1);
2956 if (chip
->read_byte(mtd
) != 'O' || chip
->read_byte(mtd
) != 'N' ||
2957 chip
->read_byte(mtd
) != 'F' || chip
->read_byte(mtd
) != 'I')
2960 chip
->cmdfunc(mtd
, NAND_CMD_PARAM
, 0, -1);
2961 for (i
= 0; i
< 3; i
++) {
2962 for (j
= 0; j
< sizeof(*p
); j
++)
2963 ((uint8_t *)p
)[j
] = chip
->read_byte(mtd
);
2964 if (onfi_crc16(ONFI_CRC_BASE
, (uint8_t *)p
, 254) ==
2965 le16_to_cpu(p
->crc
)) {
2971 pr_err("Could not find valid ONFI parameter page; aborting\n");
2976 val
= le16_to_cpu(p
->revision
);
2978 chip
->onfi_version
= 23;
2979 else if (val
& (1 << 4))
2980 chip
->onfi_version
= 22;
2981 else if (val
& (1 << 3))
2982 chip
->onfi_version
= 21;
2983 else if (val
& (1 << 2))
2984 chip
->onfi_version
= 20;
2985 else if (val
& (1 << 1))
2986 chip
->onfi_version
= 10;
2988 if (!chip
->onfi_version
) {
2989 pr_info("unsupported ONFI version: %d\n", val
);
2993 sanitize_string(p
->manufacturer
, sizeof(p
->manufacturer
));
2994 sanitize_string(p
->model
, sizeof(p
->model
));
2996 mtd
->name
= p
->model
;
2998 mtd
->writesize
= le32_to_cpu(p
->byte_per_page
);
3001 * pages_per_block and blocks_per_lun may not be a power-of-2 size
3002 * (don't ask me who thought of this...). MTD assumes that these
3003 * dimensions will be power-of-2, so just truncate the remaining area.
3005 mtd
->erasesize
= 1 << (fls(le32_to_cpu(p
->pages_per_block
)) - 1);
3006 mtd
->erasesize
*= mtd
->writesize
;
3008 mtd
->oobsize
= le16_to_cpu(p
->spare_bytes_per_page
);
3010 /* See erasesize comment */
3011 chip
->chipsize
= 1 << (fls(le32_to_cpu(p
->blocks_per_lun
)) - 1);
3012 chip
->chipsize
*= (uint64_t)mtd
->erasesize
* p
->lun_count
;
3013 chip
->bits_per_cell
= p
->bits_per_cell
;
3015 if (onfi_feature(chip
) & ONFI_FEATURE_16_BIT_BUS
)
3016 *busw
= NAND_BUSWIDTH_16
;
3020 if (p
->ecc_bits
!= 0xff) {
3021 chip
->ecc_strength_ds
= p
->ecc_bits
;
3022 chip
->ecc_step_ds
= 512;
3023 } else if (chip
->onfi_version
>= 21 &&
3024 (onfi_feature(chip
) & ONFI_FEATURE_EXT_PARAM_PAGE
)) {
3027 * The nand_flash_detect_ext_param_page() uses the
3028 * Change Read Column command which maybe not supported
3029 * by the chip->cmdfunc. So try to update the chip->cmdfunc
3030 * now. We do not replace user supplied command function.
3032 if (mtd
->writesize
> 512 && chip
->cmdfunc
== nand_command
)
3033 chip
->cmdfunc
= nand_command_lp
;
3035 /* The Extended Parameter Page is supported since ONFI 2.1. */
3036 if (nand_flash_detect_ext_param_page(mtd
, chip
, p
))
3037 pr_warn("Failed to detect ONFI extended param page\n");
3039 pr_warn("Could not retrieve ONFI ECC requirements\n");
3042 if (p
->jedec_id
== NAND_MFR_MICRON
)
3043 nand_onfi_detect_micron(chip
, p
);
3048 static int nand_flash_detect_onfi(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3056 * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise.
3058 static int nand_flash_detect_jedec(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3061 struct nand_jedec_params
*p
= &chip
->jedec_params
;
3062 struct jedec_ecc_info
*ecc
;
3066 /* Try JEDEC for unknown chip or LP */
3067 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x40, -1);
3068 if (chip
->read_byte(mtd
) != 'J' || chip
->read_byte(mtd
) != 'E' ||
3069 chip
->read_byte(mtd
) != 'D' || chip
->read_byte(mtd
) != 'E' ||
3070 chip
->read_byte(mtd
) != 'C')
3073 chip
->cmdfunc(mtd
, NAND_CMD_PARAM
, 0x40, -1);
3074 for (i
= 0; i
< 3; i
++) {
3075 for (j
= 0; j
< sizeof(*p
); j
++)
3076 ((uint8_t *)p
)[j
] = chip
->read_byte(mtd
);
3078 if (onfi_crc16(ONFI_CRC_BASE
, (uint8_t *)p
, 510) ==
3079 le16_to_cpu(p
->crc
))
3084 pr_err("Could not find valid JEDEC parameter page; aborting\n");
3089 val
= le16_to_cpu(p
->revision
);
3091 chip
->jedec_version
= 10;
3092 else if (val
& (1 << 1))
3093 chip
->jedec_version
= 1; /* vendor specific version */
3095 if (!chip
->jedec_version
) {
3096 pr_info("unsupported JEDEC version: %d\n", val
);
3100 sanitize_string(p
->manufacturer
, sizeof(p
->manufacturer
));
3101 sanitize_string(p
->model
, sizeof(p
->model
));
3103 mtd
->name
= p
->model
;
3105 mtd
->writesize
= le32_to_cpu(p
->byte_per_page
);
3107 /* Please reference to the comment for nand_flash_detect_onfi. */
3108 mtd
->erasesize
= 1 << (fls(le32_to_cpu(p
->pages_per_block
)) - 1);
3109 mtd
->erasesize
*= mtd
->writesize
;
3111 mtd
->oobsize
= le16_to_cpu(p
->spare_bytes_per_page
);
3113 /* Please reference to the comment for nand_flash_detect_onfi. */
3114 chip
->chipsize
= 1 << (fls(le32_to_cpu(p
->blocks_per_lun
)) - 1);
3115 chip
->chipsize
*= (uint64_t)mtd
->erasesize
* p
->lun_count
;
3116 chip
->bits_per_cell
= p
->bits_per_cell
;
3118 if (jedec_feature(chip
) & JEDEC_FEATURE_16_BIT_BUS
)
3119 *busw
= NAND_BUSWIDTH_16
;
3124 ecc
= &p
->ecc_info
[0];
3126 if (ecc
->codeword_size
>= 9) {
3127 chip
->ecc_strength_ds
= ecc
->ecc_bits
;
3128 chip
->ecc_step_ds
= 1 << ecc
->codeword_size
;
3130 pr_warn("Invalid codeword size\n");
3137 * nand_id_has_period - Check if an ID string has a given wraparound period
3138 * @id_data: the ID string
3139 * @arrlen: the length of the @id_data array
3140 * @period: the period of repitition
3142 * Check if an ID string is repeated within a given sequence of bytes at
3143 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
3144 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
3145 * if the repetition has a period of @period; otherwise, returns zero.
3147 static int nand_id_has_period(u8
*id_data
, int arrlen
, int period
)
3150 for (i
= 0; i
< period
; i
++)
3151 for (j
= i
+ period
; j
< arrlen
; j
+= period
)
3152 if (id_data
[i
] != id_data
[j
])
3158 * nand_id_len - Get the length of an ID string returned by CMD_READID
3159 * @id_data: the ID string
3160 * @arrlen: the length of the @id_data array
3162 * Returns the length of the ID string, according to known wraparound/trailing
3163 * zero patterns. If no pattern exists, returns the length of the array.
3165 static int nand_id_len(u8
*id_data
, int arrlen
)
3167 int last_nonzero
, period
;
3169 /* Find last non-zero byte */
3170 for (last_nonzero
= arrlen
- 1; last_nonzero
>= 0; last_nonzero
--)
3171 if (id_data
[last_nonzero
])
3175 if (last_nonzero
< 0)
3178 /* Calculate wraparound period */
3179 for (period
= 1; period
< arrlen
; period
++)
3180 if (nand_id_has_period(id_data
, arrlen
, period
))
3183 /* There's a repeated pattern */
3184 if (period
< arrlen
)
3187 /* There are trailing zeros */
3188 if (last_nonzero
< arrlen
- 1)
3189 return last_nonzero
+ 1;
3191 /* No pattern detected */
3195 /* Extract the bits of per cell from the 3rd byte of the extended ID */
3196 static int nand_get_bits_per_cell(u8 cellinfo
)
3200 bits
= cellinfo
& NAND_CI_CELLTYPE_MSK
;
3201 bits
>>= NAND_CI_CELLTYPE_SHIFT
;
3206 * Many new NAND share similar device ID codes, which represent the size of the
3207 * chip. The rest of the parameters must be decoded according to generic or
3208 * manufacturer-specific "extended ID" decoding patterns.
3210 static void nand_decode_ext_id(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3211 u8 id_data
[8], int *busw
)
3214 /* The 3rd id byte holds MLC / multichip data */
3215 chip
->bits_per_cell
= nand_get_bits_per_cell(id_data
[2]);
3216 /* The 4th id byte is the important one */
3219 id_len
= nand_id_len(id_data
, 8);
3222 * Field definitions are in the following datasheets:
3223 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
3224 * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
3225 * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
3227 * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
3228 * ID to decide what to do.
3230 if (id_len
== 6 && id_data
[0] == NAND_MFR_SAMSUNG
&&
3231 !nand_is_slc(chip
) && id_data
[5] != 0x00) {
3233 mtd
->writesize
= 2048 << (extid
& 0x03);
3236 switch (((extid
>> 2) & 0x04) | (extid
& 0x03)) {
3256 default: /* Other cases are "reserved" (unknown) */
3257 mtd
->oobsize
= 1024;
3261 /* Calc blocksize */
3262 mtd
->erasesize
= (128 * 1024) <<
3263 (((extid
>> 1) & 0x04) | (extid
& 0x03));
3265 } else if (id_len
== 6 && id_data
[0] == NAND_MFR_HYNIX
&&
3266 !nand_is_slc(chip
)) {
3270 mtd
->writesize
= 2048 << (extid
& 0x03);
3273 switch (((extid
>> 2) & 0x04) | (extid
& 0x03)) {
3297 /* Calc blocksize */
3298 tmp
= ((extid
>> 1) & 0x04) | (extid
& 0x03);
3300 mtd
->erasesize
= (128 * 1024) << tmp
;
3301 else if (tmp
== 0x03)
3302 mtd
->erasesize
= 768 * 1024;
3304 mtd
->erasesize
= (64 * 1024) << tmp
;
3308 mtd
->writesize
= 1024 << (extid
& 0x03);
3311 mtd
->oobsize
= (8 << (extid
& 0x01)) *
3312 (mtd
->writesize
>> 9);
3314 /* Calc blocksize. Blocksize is multiples of 64KiB */
3315 mtd
->erasesize
= (64 * 1024) << (extid
& 0x03);
3317 /* Get buswidth information */
3318 *busw
= (extid
& 0x01) ? NAND_BUSWIDTH_16
: 0;
3321 * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
3322 * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
3324 * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
3326 * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC
3328 if (id_len
>= 6 && id_data
[0] == NAND_MFR_TOSHIBA
&&
3329 nand_is_slc(chip
) &&
3330 (id_data
[5] & 0x7) == 0x6 /* 24nm */ &&
3331 !(id_data
[4] & 0x80) /* !BENAND */) {
3332 mtd
->oobsize
= 32 * mtd
->writesize
>> 9;
3339 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3340 * decodes a matching ID table entry and assigns the MTD size parameters for
3343 static void nand_decode_id(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3344 struct nand_flash_dev
*type
, u8 id_data
[8],
3347 int maf_id
= id_data
[0];
3349 mtd
->erasesize
= type
->erasesize
;
3350 mtd
->writesize
= type
->pagesize
;
3351 mtd
->oobsize
= mtd
->writesize
/ 32;
3352 *busw
= type
->options
& NAND_BUSWIDTH_16
;
3354 /* All legacy ID NAND are small-page, SLC */
3355 chip
->bits_per_cell
= 1;
3358 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3359 * some Spansion chips have erasesize that conflicts with size
3360 * listed in nand_ids table.
3361 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3363 if (maf_id
== NAND_MFR_AMD
&& id_data
[4] != 0x00 && id_data
[5] == 0x00
3364 && id_data
[6] == 0x00 && id_data
[7] == 0x00
3365 && mtd
->writesize
== 512) {
3366 mtd
->erasesize
= 128 * 1024;
3367 mtd
->erasesize
<<= ((id_data
[3] & 0x03) << 1);
3372 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3373 * heuristic patterns using various detected parameters (e.g., manufacturer,
3374 * page size, cell-type information).
3376 static void nand_decode_bbm_options(struct mtd_info
*mtd
,
3377 struct nand_chip
*chip
, u8 id_data
[8])
3379 int maf_id
= id_data
[0];
3381 /* Set the bad block position */
3382 if (mtd
->writesize
> 512 || (chip
->options
& NAND_BUSWIDTH_16
))
3383 chip
->badblockpos
= NAND_LARGE_BADBLOCK_POS
;
3385 chip
->badblockpos
= NAND_SMALL_BADBLOCK_POS
;
3388 * Bad block marker is stored in the last page of each block on Samsung
3389 * and Hynix MLC devices; stored in first two pages of each block on
3390 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3391 * AMD/Spansion, and Macronix. All others scan only the first page.
3393 if (!nand_is_slc(chip
) &&
3394 (maf_id
== NAND_MFR_SAMSUNG
||
3395 maf_id
== NAND_MFR_HYNIX
))
3396 chip
->bbt_options
|= NAND_BBT_SCANLASTPAGE
;
3397 else if ((nand_is_slc(chip
) &&
3398 (maf_id
== NAND_MFR_SAMSUNG
||
3399 maf_id
== NAND_MFR_HYNIX
||
3400 maf_id
== NAND_MFR_TOSHIBA
||
3401 maf_id
== NAND_MFR_AMD
||
3402 maf_id
== NAND_MFR_MACRONIX
)) ||
3403 (mtd
->writesize
== 2048 &&
3404 maf_id
== NAND_MFR_MICRON
))
3405 chip
->bbt_options
|= NAND_BBT_SCAN2NDPAGE
;
3408 static inline bool is_full_id_nand(struct nand_flash_dev
*type
)
3410 return type
->id_len
;
3413 static bool find_full_id_nand(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3414 struct nand_flash_dev
*type
, u8
*id_data
, int *busw
)
3416 if (!strncmp((char *)type
->id
, (char *)id_data
, type
->id_len
)) {
3417 mtd
->writesize
= type
->pagesize
;
3418 mtd
->erasesize
= type
->erasesize
;
3419 mtd
->oobsize
= type
->oobsize
;
3421 chip
->bits_per_cell
= nand_get_bits_per_cell(id_data
[2]);
3422 chip
->chipsize
= (uint64_t)type
->chipsize
<< 20;
3423 chip
->options
|= type
->options
;
3424 chip
->ecc_strength_ds
= NAND_ECC_STRENGTH(type
);
3425 chip
->ecc_step_ds
= NAND_ECC_STEP(type
);
3426 chip
->onfi_timing_mode_default
=
3427 type
->onfi_timing_mode_default
;
3429 *busw
= type
->options
& NAND_BUSWIDTH_16
;
3432 mtd
->name
= type
->name
;
3440 * Get the flash and manufacturer id and lookup if the type is supported.
3442 static struct nand_flash_dev
*nand_get_flash_type(struct mtd_info
*mtd
,
3443 struct nand_chip
*chip
,
3444 int *maf_id
, int *dev_id
,
3445 struct nand_flash_dev
*type
)
3451 /* Select the device */
3452 chip
->select_chip(mtd
, 0);
3455 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
3458 chip
->cmdfunc(mtd
, NAND_CMD_RESET
, -1, -1);
3460 /* Send the command for reading device ID */
3461 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
3463 /* Read manufacturer and device IDs */
3464 *maf_id
= chip
->read_byte(mtd
);
3465 *dev_id
= chip
->read_byte(mtd
);
3468 * Try again to make sure, as some systems the bus-hold or other
3469 * interface concerns can cause random data which looks like a
3470 * possibly credible NAND flash to appear. If the two results do
3471 * not match, ignore the device completely.
3474 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
3476 /* Read entire ID string */
3477 for (i
= 0; i
< 8; i
++)
3478 id_data
[i
] = chip
->read_byte(mtd
);
3480 if (id_data
[0] != *maf_id
|| id_data
[1] != *dev_id
) {
3481 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
3482 *maf_id
, *dev_id
, id_data
[0], id_data
[1]);
3483 return ERR_PTR(-ENODEV
);
3487 type
= nand_flash_ids
;
3489 for (; type
->name
!= NULL
; type
++) {
3490 if (is_full_id_nand(type
)) {
3491 if (find_full_id_nand(mtd
, chip
, type
, id_data
, &busw
))
3493 } else if (*dev_id
== type
->dev_id
) {
3498 chip
->onfi_version
= 0;
3499 if (!type
->name
|| !type
->pagesize
) {
3500 /* Check if the chip is ONFI compliant */
3501 if (nand_flash_detect_onfi(mtd
, chip
, &busw
))
3504 /* Check if the chip is JEDEC compliant */
3505 if (nand_flash_detect_jedec(mtd
, chip
, &busw
))
3510 return ERR_PTR(-ENODEV
);
3513 mtd
->name
= type
->name
;
3515 chip
->chipsize
= (uint64_t)type
->chipsize
<< 20;
3517 if (!type
->pagesize
&& chip
->init_size
) {
3518 /* Set the pagesize, oobsize, erasesize by the driver */
3519 busw
= chip
->init_size(mtd
, chip
, id_data
);
3520 } else if (!type
->pagesize
) {
3521 /* Decode parameters from extended ID */
3522 nand_decode_ext_id(mtd
, chip
, id_data
, &busw
);
3524 nand_decode_id(mtd
, chip
, type
, id_data
, &busw
);
3526 /* Get chip options */
3527 chip
->options
|= type
->options
;
3530 * Check if chip is not a Samsung device. Do not clear the
3531 * options for chips which do not have an extended id.
3533 if (*maf_id
!= NAND_MFR_SAMSUNG
&& !type
->pagesize
)
3534 chip
->options
&= ~NAND_SAMSUNG_LP_OPTIONS
;
3537 /* Try to identify manufacturer */
3538 for (maf_idx
= 0; nand_manuf_ids
[maf_idx
].id
!= 0x0; maf_idx
++) {
3539 if (nand_manuf_ids
[maf_idx
].id
== *maf_id
)
3543 if (chip
->options
& NAND_BUSWIDTH_AUTO
) {
3544 WARN_ON(chip
->options
& NAND_BUSWIDTH_16
);
3545 chip
->options
|= busw
;
3546 nand_set_defaults(chip
, busw
);
3547 } else if (busw
!= (chip
->options
& NAND_BUSWIDTH_16
)) {
3549 * Check, if buswidth is correct. Hardware drivers should set
3552 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3554 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
, mtd
->name
);
3555 pr_warn("bus width %d instead %d bit\n",
3556 (chip
->options
& NAND_BUSWIDTH_16
) ? 16 : 8,
3558 return ERR_PTR(-EINVAL
);
3561 nand_decode_bbm_options(mtd
, chip
, id_data
);
3563 /* Calculate the address shift from the page size */
3564 chip
->page_shift
= ffs(mtd
->writesize
) - 1;
3565 /* Convert chipsize to number of pages per chip -1 */
3566 chip
->pagemask
= (chip
->chipsize
>> chip
->page_shift
) - 1;
3568 chip
->bbt_erase_shift
= chip
->phys_erase_shift
=
3569 ffs(mtd
->erasesize
) - 1;
3570 if (chip
->chipsize
& 0xffffffff)
3571 chip
->chip_shift
= ffs((unsigned)chip
->chipsize
) - 1;
3573 chip
->chip_shift
= ffs((unsigned)(chip
->chipsize
>> 32));
3574 chip
->chip_shift
+= 32 - 1;
3577 chip
->badblockbits
= 8;
3578 chip
->erase
= single_erase
;
3580 /* Do not replace user supplied command function! */
3581 if (mtd
->writesize
> 512 && chip
->cmdfunc
== nand_command
)
3582 chip
->cmdfunc
= nand_command_lp
;
3584 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3587 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3588 if (chip
->onfi_version
)
3589 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
,
3590 chip
->onfi_params
.model
);
3591 else if (chip
->jedec_version
)
3592 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
,
3593 chip
->jedec_params
.model
);
3595 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
,
3598 if (chip
->jedec_version
)
3599 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
,
3600 chip
->jedec_params
.model
);
3602 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
,
3605 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
,
3609 pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n",
3610 (int)(chip
->chipsize
>> 20), nand_is_slc(chip
) ? "SLC" : "MLC",
3611 mtd
->erasesize
>> 10, mtd
->writesize
, mtd
->oobsize
);
3616 * nand_scan_ident - [NAND Interface] Scan for the NAND device
3617 * @mtd: MTD device structure
3618 * @maxchips: number of chips to scan for
3619 * @table: alternative NAND ID table
3621 * This is the first phase of the normal nand_scan() function. It reads the
3622 * flash ID and sets up MTD fields accordingly.
3624 * The mtd->owner field must be set to the module of the caller.
3626 int nand_scan_ident(struct mtd_info
*mtd
, int maxchips
,
3627 struct nand_flash_dev
*table
)
3629 int i
, nand_maf_id
, nand_dev_id
;
3630 struct nand_chip
*chip
= mtd_to_nand(mtd
);
3631 struct nand_flash_dev
*type
;
3633 /* Set the default functions */
3634 nand_set_defaults(chip
, chip
->options
& NAND_BUSWIDTH_16
);
3636 /* Read the flash type */
3637 type
= nand_get_flash_type(mtd
, chip
, &nand_maf_id
,
3638 &nand_dev_id
, table
);
3641 if (!(chip
->options
& NAND_SCAN_SILENT_NODEV
))
3642 pr_warn("No NAND device found\n");
3643 chip
->select_chip(mtd
, -1);
3644 return PTR_ERR(type
);
3647 chip
->select_chip(mtd
, -1);
3649 /* Check for a chip array */
3650 for (i
= 1; i
< maxchips
; i
++) {
3651 chip
->select_chip(mtd
, i
);
3652 /* See comment in nand_get_flash_type for reset */
3653 chip
->cmdfunc(mtd
, NAND_CMD_RESET
, -1, -1);
3654 /* Send the command for reading device ID */
3655 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
3656 /* Read manufacturer and device IDs */
3657 if (nand_maf_id
!= chip
->read_byte(mtd
) ||
3658 nand_dev_id
!= chip
->read_byte(mtd
)) {
3659 chip
->select_chip(mtd
, -1);
3662 chip
->select_chip(mtd
, -1);
3667 pr_info("%d chips detected\n", i
);
3670 /* Store the number of chips and calc total size for mtd */
3672 mtd
->size
= i
* chip
->chipsize
;
3676 EXPORT_SYMBOL(nand_scan_ident
);
3679 * Check if the chip configuration meet the datasheet requirements.
3681 * If our configuration corrects A bits per B bytes and the minimum
3682 * required correction level is X bits per Y bytes, then we must ensure
3683 * both of the following are true:
3685 * (1) A / B >= X / Y
3688 * Requirement (1) ensures we can correct for the required bitflip density.
3689 * Requirement (2) ensures we can correct even when all bitflips are clumped
3690 * in the same sector.
3692 static bool nand_ecc_strength_good(struct mtd_info
*mtd
)
3694 struct nand_chip
*chip
= mtd_to_nand(mtd
);
3695 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
3698 if (ecc
->size
== 0 || chip
->ecc_step_ds
== 0)
3699 /* Not enough information */
3703 * We get the number of corrected bits per page to compare
3704 * the correction density.
3706 corr
= (mtd
->writesize
* ecc
->strength
) / ecc
->size
;
3707 ds_corr
= (mtd
->writesize
* chip
->ecc_strength_ds
) / chip
->ecc_step_ds
;
3709 return corr
>= ds_corr
&& ecc
->strength
>= chip
->ecc_strength_ds
;
3713 * nand_scan_tail - [NAND Interface] Scan for the NAND device
3714 * @mtd: MTD device structure
3716 * This is the second phase of the normal nand_scan() function. It fills out
3717 * all the uninitialized function pointers with the defaults and scans for a
3718 * bad block table if appropriate.
3720 int nand_scan_tail(struct mtd_info
*mtd
)
3723 struct nand_chip
*chip
= mtd_to_nand(mtd
);
3724 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
3725 struct nand_buffers
*nbuf
;
3727 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
3728 BUG_ON((chip
->bbt_options
& NAND_BBT_NO_OOB_BBM
) &&
3729 !(chip
->bbt_options
& NAND_BBT_USE_FLASH
));
3731 if (!(chip
->options
& NAND_OWN_BUFFERS
)) {
3732 nbuf
= kzalloc(sizeof(struct nand_buffers
), GFP_KERNEL
);
3733 chip
->buffers
= nbuf
;
3739 /* Set the internal oob buffer location, just after the page data */
3740 chip
->oob_poi
= chip
->buffers
->databuf
+ mtd
->writesize
;
3743 * If no default placement scheme is given, select an appropriate one.
3745 if (!ecc
->layout
&& (ecc
->mode
!= NAND_ECC_SOFT_BCH
)) {
3746 switch (mtd
->oobsize
) {
3748 ecc
->layout
= &nand_oob_8
;
3751 ecc
->layout
= &nand_oob_16
;
3754 ecc
->layout
= &nand_oob_64
;
3757 ecc
->layout
= &nand_oob_128
;
3760 pr_warn("No oob scheme defined for oobsize %d\n",
3766 if (!chip
->write_page
)
3767 chip
->write_page
= nand_write_page
;
3770 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
3771 * selected and we have 256 byte pagesize fallback to software ECC
3774 switch (ecc
->mode
) {
3775 case NAND_ECC_HW_OOB_FIRST
:
3776 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3777 if (!ecc
->calculate
|| !ecc
->correct
|| !ecc
->hwctl
) {
3778 pr_warn("No ECC functions supplied; hardware ECC not possible\n");
3781 if (!ecc
->read_page
)
3782 ecc
->read_page
= nand_read_page_hwecc_oob_first
;
3785 /* Use standard hwecc read page function? */
3786 if (!ecc
->read_page
)
3787 ecc
->read_page
= nand_read_page_hwecc
;
3788 if (!ecc
->write_page
)
3789 ecc
->write_page
= nand_write_page_hwecc
;
3790 if (!ecc
->read_page_raw
)
3791 ecc
->read_page_raw
= nand_read_page_raw
;
3792 if (!ecc
->write_page_raw
)
3793 ecc
->write_page_raw
= nand_write_page_raw
;
3795 ecc
->read_oob
= nand_read_oob_std
;
3796 if (!ecc
->write_oob
)
3797 ecc
->write_oob
= nand_write_oob_std
;
3798 if (!ecc
->read_subpage
)
3799 ecc
->read_subpage
= nand_read_subpage
;
3800 if (!ecc
->write_subpage
)
3801 ecc
->write_subpage
= nand_write_subpage_hwecc
;
3803 case NAND_ECC_HW_SYNDROME
:
3804 if ((!ecc
->calculate
|| !ecc
->correct
|| !ecc
->hwctl
) &&
3806 ecc
->read_page
== nand_read_page_hwecc
||
3808 ecc
->write_page
== nand_write_page_hwecc
)) {
3809 pr_warn("No ECC functions supplied; hardware ECC not possible\n");
3812 /* Use standard syndrome read/write page function? */
3813 if (!ecc
->read_page
)
3814 ecc
->read_page
= nand_read_page_syndrome
;
3815 if (!ecc
->write_page
)
3816 ecc
->write_page
= nand_write_page_syndrome
;
3817 if (!ecc
->read_page_raw
)
3818 ecc
->read_page_raw
= nand_read_page_raw_syndrome
;
3819 if (!ecc
->write_page_raw
)
3820 ecc
->write_page_raw
= nand_write_page_raw_syndrome
;
3822 ecc
->read_oob
= nand_read_oob_syndrome
;
3823 if (!ecc
->write_oob
)
3824 ecc
->write_oob
= nand_write_oob_syndrome
;
3826 if (mtd
->writesize
>= ecc
->size
) {
3827 if (!ecc
->strength
) {
3828 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
3833 pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
3834 ecc
->size
, mtd
->writesize
);
3835 ecc
->mode
= NAND_ECC_SOFT
;
3838 ecc
->calculate
= nand_calculate_ecc
;
3839 ecc
->correct
= nand_correct_data
;
3840 ecc
->read_page
= nand_read_page_swecc
;
3841 ecc
->read_subpage
= nand_read_subpage
;
3842 ecc
->write_page
= nand_write_page_swecc
;
3843 ecc
->read_page_raw
= nand_read_page_raw
;
3844 ecc
->write_page_raw
= nand_write_page_raw
;
3845 ecc
->read_oob
= nand_read_oob_std
;
3846 ecc
->write_oob
= nand_write_oob_std
;
3853 case NAND_ECC_SOFT_BCH
:
3854 if (!mtd_nand_has_bch()) {
3855 pr_warn("CONFIG_MTD_NAND_ECC_BCH not enabled\n");
3858 ecc
->calculate
= nand_bch_calculate_ecc
;
3859 ecc
->correct
= nand_bch_correct_data
;
3860 ecc
->read_page
= nand_read_page_swecc
;
3861 ecc
->read_subpage
= nand_read_subpage
;
3862 ecc
->write_page
= nand_write_page_swecc
;
3863 ecc
->read_page_raw
= nand_read_page_raw
;
3864 ecc
->write_page_raw
= nand_write_page_raw
;
3865 ecc
->read_oob
= nand_read_oob_std
;
3866 ecc
->write_oob
= nand_write_oob_std
;
3868 * Board driver should supply ecc.size and ecc.strength values
3869 * to select how many bits are correctable. Otherwise, default
3870 * to 4 bits for large page devices.
3872 if (!ecc
->size
&& (mtd
->oobsize
>= 64)) {
3877 /* See nand_bch_init() for details. */
3878 ecc
->bytes
= DIV_ROUND_UP(
3879 ecc
->strength
* fls(8 * ecc
->size
), 8);
3880 ecc
->priv
= nand_bch_init(mtd
, ecc
->size
, ecc
->bytes
,
3883 pr_warn("BCH ECC initialization failed!\n");
3889 pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n");
3890 ecc
->read_page
= nand_read_page_raw
;
3891 ecc
->write_page
= nand_write_page_raw
;
3892 ecc
->read_oob
= nand_read_oob_std
;
3893 ecc
->read_page_raw
= nand_read_page_raw
;
3894 ecc
->write_page_raw
= nand_write_page_raw
;
3895 ecc
->write_oob
= nand_write_oob_std
;
3896 ecc
->size
= mtd
->writesize
;
3902 pr_warn("Invalid NAND_ECC_MODE %d\n", ecc
->mode
);
3906 /* For many systems, the standard OOB write also works for raw */
3907 if (!ecc
->read_oob_raw
)
3908 ecc
->read_oob_raw
= ecc
->read_oob
;
3909 if (!ecc
->write_oob_raw
)
3910 ecc
->write_oob_raw
= ecc
->write_oob
;
3913 * The number of bytes available for a client to place data into
3914 * the out of band area.
3916 ecc
->layout
->oobavail
= 0;
3917 for (i
= 0; ecc
->layout
->oobfree
[i
].length
3918 && i
< ARRAY_SIZE(ecc
->layout
->oobfree
); i
++)
3919 ecc
->layout
->oobavail
+= ecc
->layout
->oobfree
[i
].length
;
3920 mtd
->oobavail
= ecc
->layout
->oobavail
;
3922 /* ECC sanity check: warn if it's too weak */
3923 if (!nand_ecc_strength_good(mtd
))
3924 pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n",
3928 * Set the number of read / write steps for one page depending on ECC
3931 ecc
->steps
= mtd
->writesize
/ ecc
->size
;
3932 if (ecc
->steps
* ecc
->size
!= mtd
->writesize
) {
3933 pr_warn("Invalid ECC parameters\n");
3936 ecc
->total
= ecc
->steps
* ecc
->bytes
;
3938 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
3939 if (!(chip
->options
& NAND_NO_SUBPAGE_WRITE
) && nand_is_slc(chip
)) {
3940 switch (ecc
->steps
) {
3942 mtd
->subpage_sft
= 1;
3947 mtd
->subpage_sft
= 2;
3951 chip
->subpagesize
= mtd
->writesize
>> mtd
->subpage_sft
;
3953 /* Initialize state */
3954 chip
->state
= FL_READY
;
3956 /* Invalidate the pagebuffer reference */
3959 /* Large page NAND with SOFT_ECC should support subpage reads */
3960 switch (ecc
->mode
) {
3962 case NAND_ECC_SOFT_BCH
:
3963 if (chip
->page_shift
> 9)
3964 chip
->options
|= NAND_SUBPAGE_READ
;
3971 /* Fill in remaining MTD driver data */
3972 mtd
->type
= nand_is_slc(chip
) ? MTD_NANDFLASH
: MTD_MLCNANDFLASH
;
3973 mtd
->flags
= (chip
->options
& NAND_ROM
) ? MTD_CAP_ROM
:
3975 mtd
->_erase
= nand_erase
;
3976 mtd
->_read
= nand_read
;
3977 mtd
->_write
= nand_write
;
3978 mtd
->_panic_write
= panic_nand_write
;
3979 mtd
->_read_oob
= nand_read_oob
;
3980 mtd
->_write_oob
= nand_write_oob
;
3981 mtd
->_sync
= nand_sync
;
3983 mtd
->_unlock
= NULL
;
3984 mtd
->_block_isreserved
= nand_block_isreserved
;
3985 mtd
->_block_isbad
= nand_block_isbad
;
3986 mtd
->_block_markbad
= nand_block_markbad
;
3987 mtd
->writebufsize
= mtd
->writesize
;
3989 /* propagate ecc info to mtd_info */
3990 mtd
->ecclayout
= ecc
->layout
;
3991 mtd
->ecc_strength
= ecc
->strength
;
3992 mtd
->ecc_step_size
= ecc
->size
;
3994 * Initialize bitflip_threshold to its default prior scan_bbt() call.
3995 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
3998 if (!mtd
->bitflip_threshold
)
3999 mtd
->bitflip_threshold
= DIV_ROUND_UP(mtd
->ecc_strength
* 3, 4);
4003 EXPORT_SYMBOL(nand_scan_tail
);
4006 * is_module_text_address() isn't exported, and it's mostly a pointless
4007 * test if this is a module _anyway_ -- they'd have to try _really_ hard
4008 * to call us from in-kernel code if the core NAND support is modular.
4011 #define caller_is_module() (1)
4013 #define caller_is_module() \
4014 is_module_text_address((unsigned long)__builtin_return_address(0))
4018 * nand_scan - [NAND Interface] Scan for the NAND device
4019 * @mtd: MTD device structure
4020 * @maxchips: number of chips to scan for
4022 * This fills out all the uninitialized function pointers with the defaults.
4023 * The flash ID is read and the mtd/chip structures are filled with the
4024 * appropriate values. The mtd->owner field must be set to the module of the
4027 int nand_scan(struct mtd_info
*mtd
, int maxchips
)
4031 /* Many callers got this wrong, so check for it for a while... */
4032 if (!mtd
->owner
&& caller_is_module()) {
4033 pr_crit("%s called with NULL mtd->owner!\n", __func__
);
4037 ret
= nand_scan_ident(mtd
, maxchips
, NULL
);
4039 ret
= nand_scan_tail(mtd
);
4042 EXPORT_SYMBOL(nand_scan
);
4044 module_init(nand_base_init
);
4045 module_exit(nand_base_exit
);
4047 MODULE_LICENSE("GPL");
4048 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
4049 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
4050 MODULE_DESCRIPTION("Generic NAND flash driver code");