3 * This is the generic MTD driver for NAND flash devices. It should be
4 * capable of working with almost all NAND chips currently available.
6 * Additional technical information is available on
7 * http://www.linux-mtd.infradead.org/doc/nand.html
9 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
10 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
13 * David Woodhouse for adding multichip support
15 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
16 * rework for 2K page size chips
19 * Enable cached programming for 2k page size chips
20 * Check, if mtd->ecctype should be set to MTD_ECC_HW
21 * if we have HW ECC support.
22 * BBT table is not serialized, has to be fixed
24 * This program is free software; you can redistribute it and/or modify
25 * it under the terms of the GNU General Public License version 2 as
26 * published by the Free Software Foundation.
30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
32 #if CONFIG_IS_ENABLED(OF_CONTROL)
37 #include <linux/err.h>
38 #include <linux/compat.h>
39 #include <linux/mtd/mtd.h>
40 #include <linux/mtd/nand.h>
41 #include <linux/mtd/nand_ecc.h>
42 #include <linux/mtd/nand_bch.h>
43 #ifdef CONFIG_MTD_PARTITIONS
44 #include <linux/mtd/partitions.h>
47 #include <linux/errno.h>
49 /* Define default oob placement schemes for large and small page devices */
50 static struct nand_ecclayout nand_oob_8
= {
60 static struct nand_ecclayout nand_oob_16
= {
62 .eccpos
= {0, 1, 2, 3, 6, 7},
68 static struct nand_ecclayout nand_oob_64
= {
71 40, 41, 42, 43, 44, 45, 46, 47,
72 48, 49, 50, 51, 52, 53, 54, 55,
73 56, 57, 58, 59, 60, 61, 62, 63},
79 static struct nand_ecclayout nand_oob_128
= {
82 80, 81, 82, 83, 84, 85, 86, 87,
83 88, 89, 90, 91, 92, 93, 94, 95,
84 96, 97, 98, 99, 100, 101, 102, 103,
85 104, 105, 106, 107, 108, 109, 110, 111,
86 112, 113, 114, 115, 116, 117, 118, 119,
87 120, 121, 122, 123, 124, 125, 126, 127},
93 static int nand_get_device(struct mtd_info
*mtd
, int new_state
);
95 static int nand_do_write_oob(struct mtd_info
*mtd
, loff_t to
,
96 struct mtd_oob_ops
*ops
);
99 * For devices which display every fart in the system on a separate LED. Is
100 * compiled away when LED support is disabled.
102 DEFINE_LED_TRIGGER(nand_led_trigger
);
104 static int check_offs_len(struct mtd_info
*mtd
,
105 loff_t ofs
, uint64_t len
)
107 struct nand_chip
*chip
= mtd_to_nand(mtd
);
110 /* Start address must align on block boundary */
111 if (ofs
& ((1ULL << chip
->phys_erase_shift
) - 1)) {
112 pr_debug("%s: unaligned address\n", __func__
);
116 /* Length must align on block boundary */
117 if (len
& ((1ULL << chip
->phys_erase_shift
) - 1)) {
118 pr_debug("%s: length not block aligned\n", __func__
);
126 * nand_release_device - [GENERIC] release chip
127 * @mtd: MTD device structure
129 * Release chip lock and wake up anyone waiting on the device.
131 static void nand_release_device(struct mtd_info
*mtd
)
133 struct nand_chip
*chip
= mtd_to_nand(mtd
);
135 /* De-select the NAND device */
136 chip
->select_chip(mtd
, -1);
140 * nand_read_byte - [DEFAULT] read one byte from the chip
141 * @mtd: MTD device structure
143 * Default read function for 8bit buswidth
145 uint8_t nand_read_byte(struct mtd_info
*mtd
)
147 struct nand_chip
*chip
= mtd_to_nand(mtd
);
148 return readb(chip
->IO_ADDR_R
);
152 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
153 * @mtd: MTD device structure
155 * Default read function for 16bit buswidth with endianness conversion.
158 static uint8_t nand_read_byte16(struct mtd_info
*mtd
)
160 struct nand_chip
*chip
= mtd_to_nand(mtd
);
161 return (uint8_t) cpu_to_le16(readw(chip
->IO_ADDR_R
));
165 * nand_read_word - [DEFAULT] read one word from the chip
166 * @mtd: MTD device structure
168 * Default read function for 16bit buswidth without endianness conversion.
170 static u16
nand_read_word(struct mtd_info
*mtd
)
172 struct nand_chip
*chip
= mtd_to_nand(mtd
);
173 return readw(chip
->IO_ADDR_R
);
177 * nand_select_chip - [DEFAULT] control CE line
178 * @mtd: MTD device structure
179 * @chipnr: chipnumber to select, -1 for deselect
181 * Default select function for 1 chip devices.
183 static void nand_select_chip(struct mtd_info
*mtd
, int chipnr
)
185 struct nand_chip
*chip
= mtd_to_nand(mtd
);
189 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, 0 | NAND_CTRL_CHANGE
);
200 * nand_write_byte - [DEFAULT] write single byte to chip
201 * @mtd: MTD device structure
202 * @byte: value to write
204 * Default function to write a byte to I/O[7:0]
206 static void nand_write_byte(struct mtd_info
*mtd
, uint8_t byte
)
208 struct nand_chip
*chip
= mtd_to_nand(mtd
);
210 chip
->write_buf(mtd
, &byte
, 1);
214 * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
215 * @mtd: MTD device structure
216 * @byte: value to write
218 * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
220 static void nand_write_byte16(struct mtd_info
*mtd
, uint8_t byte
)
222 struct nand_chip
*chip
= mtd_to_nand(mtd
);
223 uint16_t word
= byte
;
226 * It's not entirely clear what should happen to I/O[15:8] when writing
227 * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
229 * When the host supports a 16-bit bus width, only data is
230 * transferred at the 16-bit width. All address and command line
231 * transfers shall use only the lower 8-bits of the data bus. During
232 * command transfers, the host may place any value on the upper
233 * 8-bits of the data bus. During address transfers, the host shall
234 * set the upper 8-bits of the data bus to 00h.
236 * One user of the write_byte callback is nand_onfi_set_features. The
237 * four parameters are specified to be written to I/O[7:0], but this is
238 * neither an address nor a command transfer. Let's assume a 0 on the
239 * upper I/O lines is OK.
241 chip
->write_buf(mtd
, (uint8_t *)&word
, 2);
244 static void iowrite8_rep(void *addr
, const uint8_t *buf
, int len
)
248 for (i
= 0; i
< len
; i
++)
249 writeb(buf
[i
], addr
);
251 static void ioread8_rep(void *addr
, uint8_t *buf
, int len
)
255 for (i
= 0; i
< len
; i
++)
256 buf
[i
] = readb(addr
);
259 static void ioread16_rep(void *addr
, void *buf
, int len
)
262 u16
*p
= (u16
*) buf
;
264 for (i
= 0; i
< len
; i
++)
268 static void iowrite16_rep(void *addr
, void *buf
, int len
)
271 u16
*p
= (u16
*) buf
;
273 for (i
= 0; i
< len
; i
++)
278 * nand_write_buf - [DEFAULT] write buffer to chip
279 * @mtd: MTD device structure
281 * @len: number of bytes to write
283 * Default write function for 8bit buswidth.
285 void nand_write_buf(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
287 struct nand_chip
*chip
= mtd_to_nand(mtd
);
289 iowrite8_rep(chip
->IO_ADDR_W
, buf
, len
);
293 * nand_read_buf - [DEFAULT] read chip data into buffer
294 * @mtd: MTD device structure
295 * @buf: buffer to store date
296 * @len: number of bytes to read
298 * Default read function for 8bit buswidth.
300 void nand_read_buf(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
302 struct nand_chip
*chip
= mtd_to_nand(mtd
);
304 ioread8_rep(chip
->IO_ADDR_R
, buf
, len
);
308 * nand_write_buf16 - [DEFAULT] write buffer to chip
309 * @mtd: MTD device structure
311 * @len: number of bytes to write
313 * Default write function for 16bit buswidth.
315 void nand_write_buf16(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
317 struct nand_chip
*chip
= mtd_to_nand(mtd
);
318 u16
*p
= (u16
*) buf
;
320 iowrite16_rep(chip
->IO_ADDR_W
, p
, len
>> 1);
324 * nand_read_buf16 - [DEFAULT] read chip data into buffer
325 * @mtd: MTD device structure
326 * @buf: buffer to store date
327 * @len: number of bytes to read
329 * Default read function for 16bit buswidth.
331 void nand_read_buf16(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
333 struct nand_chip
*chip
= mtd_to_nand(mtd
);
334 u16
*p
= (u16
*) buf
;
336 ioread16_rep(chip
->IO_ADDR_R
, p
, len
>> 1);
340 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
341 * @mtd: MTD device structure
342 * @ofs: offset from device start
344 * Check, if the block is bad.
346 static int nand_block_bad(struct mtd_info
*mtd
, loff_t ofs
)
348 int page
, res
= 0, i
= 0;
349 struct nand_chip
*chip
= mtd_to_nand(mtd
);
352 if (chip
->bbt_options
& NAND_BBT_SCANLASTPAGE
)
353 ofs
+= mtd
->erasesize
- mtd
->writesize
;
355 page
= (int)(ofs
>> chip
->page_shift
) & chip
->pagemask
;
358 if (chip
->options
& NAND_BUSWIDTH_16
) {
359 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
,
360 chip
->badblockpos
& 0xFE, page
);
361 bad
= cpu_to_le16(chip
->read_word(mtd
));
362 if (chip
->badblockpos
& 0x1)
367 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, chip
->badblockpos
,
369 bad
= chip
->read_byte(mtd
);
372 if (likely(chip
->badblockbits
== 8))
375 res
= hweight8(bad
) < chip
->badblockbits
;
376 ofs
+= mtd
->writesize
;
377 page
= (int)(ofs
>> chip
->page_shift
) & chip
->pagemask
;
379 } while (!res
&& i
< 2 && (chip
->bbt_options
& NAND_BBT_SCAN2NDPAGE
));
385 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
386 * @mtd: MTD device structure
387 * @ofs: offset from device start
389 * This is the default implementation, which can be overridden by a hardware
390 * specific driver. It provides the details for writing a bad block marker to a
393 static int nand_default_block_markbad(struct mtd_info
*mtd
, loff_t ofs
)
395 struct nand_chip
*chip
= mtd_to_nand(mtd
);
396 struct mtd_oob_ops ops
;
397 uint8_t buf
[2] = { 0, 0 };
398 int ret
= 0, res
, i
= 0;
400 memset(&ops
, 0, sizeof(ops
));
402 ops
.ooboffs
= chip
->badblockpos
;
403 if (chip
->options
& NAND_BUSWIDTH_16
) {
404 ops
.ooboffs
&= ~0x01;
405 ops
.len
= ops
.ooblen
= 2;
407 ops
.len
= ops
.ooblen
= 1;
409 ops
.mode
= MTD_OPS_PLACE_OOB
;
411 /* Write to first/last page(s) if necessary */
412 if (chip
->bbt_options
& NAND_BBT_SCANLASTPAGE
)
413 ofs
+= mtd
->erasesize
- mtd
->writesize
;
415 res
= nand_do_write_oob(mtd
, ofs
, &ops
);
420 ofs
+= mtd
->writesize
;
421 } while ((chip
->bbt_options
& NAND_BBT_SCAN2NDPAGE
) && i
< 2);
427 * nand_block_markbad_lowlevel - mark a block bad
428 * @mtd: MTD device structure
429 * @ofs: offset from device start
431 * This function performs the generic NAND bad block marking steps (i.e., bad
432 * block table(s) and/or marker(s)). We only allow the hardware driver to
433 * specify how to write bad block markers to OOB (chip->block_markbad).
435 * We try operations in the following order:
436 * (1) erase the affected block, to allow OOB marker to be written cleanly
437 * (2) write bad block marker to OOB area of affected block (unless flag
438 * NAND_BBT_NO_OOB_BBM is present)
440 * Note that we retain the first error encountered in (2) or (3), finish the
441 * procedures, and dump the error in the end.
443 static int nand_block_markbad_lowlevel(struct mtd_info
*mtd
, loff_t ofs
)
445 struct nand_chip
*chip
= mtd_to_nand(mtd
);
448 if (!(chip
->bbt_options
& NAND_BBT_NO_OOB_BBM
)) {
449 struct erase_info einfo
;
451 /* Attempt erase before marking OOB */
452 memset(&einfo
, 0, sizeof(einfo
));
455 einfo
.len
= 1ULL << chip
->phys_erase_shift
;
456 nand_erase_nand(mtd
, &einfo
, 0);
458 /* Write bad block marker to OOB */
459 nand_get_device(mtd
, FL_WRITING
);
460 ret
= chip
->block_markbad(mtd
, ofs
);
461 nand_release_device(mtd
);
464 /* Mark block bad in BBT */
466 res
= nand_markbad_bbt(mtd
, ofs
);
472 mtd
->ecc_stats
.badblocks
++;
478 * nand_check_wp - [GENERIC] check if the chip is write protected
479 * @mtd: MTD device structure
481 * Check, if the device is write protected. The function expects, that the
482 * device is already selected.
484 static int nand_check_wp(struct mtd_info
*mtd
)
486 struct nand_chip
*chip
= mtd_to_nand(mtd
);
488 /* Broken xD cards report WP despite being writable */
489 if (chip
->options
& NAND_BROKEN_XD
)
492 /* Check the WP bit */
493 chip
->cmdfunc(mtd
, NAND_CMD_STATUS
, -1, -1);
494 return (chip
->read_byte(mtd
) & NAND_STATUS_WP
) ? 0 : 1;
498 * nand_block_isreserved - [GENERIC] Check if a block is marked reserved.
499 * @mtd: MTD device structure
500 * @ofs: offset from device start
502 * Check if the block is marked as reserved.
504 static int nand_block_isreserved(struct mtd_info
*mtd
, loff_t ofs
)
506 struct nand_chip
*chip
= mtd_to_nand(mtd
);
510 /* Return info from the table */
511 return nand_isreserved_bbt(mtd
, ofs
);
515 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
516 * @mtd: MTD device structure
517 * @ofs: offset from device start
518 * @allowbbt: 1, if its allowed to access the bbt area
520 * Check, if the block is bad. Either by reading the bad block table or
521 * calling of the scan function.
523 static int nand_block_checkbad(struct mtd_info
*mtd
, loff_t ofs
, int allowbbt
)
525 struct nand_chip
*chip
= mtd_to_nand(mtd
);
527 if (!(chip
->options
& NAND_SKIP_BBTSCAN
) &&
528 !(chip
->options
& NAND_BBT_SCANNED
)) {
529 chip
->options
|= NAND_BBT_SCANNED
;
534 return chip
->block_bad(mtd
, ofs
);
536 /* Return info from the table */
537 return nand_isbad_bbt(mtd
, ofs
, allowbbt
);
541 * nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
542 * @mtd: MTD device structure
544 * Wait for the ready pin after a command, and warn if a timeout occurs.
546 void nand_wait_ready(struct mtd_info
*mtd
)
548 struct nand_chip
*chip
= mtd_to_nand(mtd
);
549 u32 timeo
= (CONFIG_SYS_HZ
* 400) / 1000;
552 time_start
= get_timer(0);
553 /* Wait until command is processed or timeout occurs */
554 while (get_timer(time_start
) < timeo
) {
556 if (chip
->dev_ready(mtd
))
560 if (!chip
->dev_ready(mtd
))
561 pr_warn("timeout while waiting for chip to become ready\n");
563 EXPORT_SYMBOL_GPL(nand_wait_ready
);
566 * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands.
567 * @mtd: MTD device structure
568 * @timeo: Timeout in ms
570 * Wait for status ready (i.e. command done) or timeout.
572 static void nand_wait_status_ready(struct mtd_info
*mtd
, unsigned long timeo
)
574 register struct nand_chip
*chip
= mtd_to_nand(mtd
);
577 timeo
= (CONFIG_SYS_HZ
* timeo
) / 1000;
578 time_start
= get_timer(0);
579 while (get_timer(time_start
) < timeo
) {
580 if ((chip
->read_byte(mtd
) & NAND_STATUS_READY
))
587 * nand_command - [DEFAULT] Send command to NAND device
588 * @mtd: MTD device structure
589 * @command: the command to be sent
590 * @column: the column address for this command, -1 if none
591 * @page_addr: the page address for this command, -1 if none
593 * Send command to NAND device. This function is used for small page devices
594 * (512 Bytes per page).
596 static void nand_command(struct mtd_info
*mtd
, unsigned int command
,
597 int column
, int page_addr
)
599 register struct nand_chip
*chip
= mtd_to_nand(mtd
);
600 int ctrl
= NAND_CTRL_CLE
| NAND_CTRL_CHANGE
;
602 /* Write out the command to the device */
603 if (command
== NAND_CMD_SEQIN
) {
606 if (column
>= mtd
->writesize
) {
608 column
-= mtd
->writesize
;
609 readcmd
= NAND_CMD_READOOB
;
610 } else if (column
< 256) {
611 /* First 256 bytes --> READ0 */
612 readcmd
= NAND_CMD_READ0
;
615 readcmd
= NAND_CMD_READ1
;
617 chip
->cmd_ctrl(mtd
, readcmd
, ctrl
);
618 ctrl
&= ~NAND_CTRL_CHANGE
;
620 chip
->cmd_ctrl(mtd
, command
, ctrl
);
622 /* Address cycle, when necessary */
623 ctrl
= NAND_CTRL_ALE
| NAND_CTRL_CHANGE
;
624 /* Serially input address */
626 /* Adjust columns for 16 bit buswidth */
627 if (chip
->options
& NAND_BUSWIDTH_16
&&
628 !nand_opcode_8bits(command
))
630 chip
->cmd_ctrl(mtd
, column
, ctrl
);
631 ctrl
&= ~NAND_CTRL_CHANGE
;
633 if (page_addr
!= -1) {
634 chip
->cmd_ctrl(mtd
, page_addr
, ctrl
);
635 ctrl
&= ~NAND_CTRL_CHANGE
;
636 chip
->cmd_ctrl(mtd
, page_addr
>> 8, ctrl
);
637 /* One more address cycle for devices > 32MiB */
638 if (chip
->chipsize
> (32 << 20))
639 chip
->cmd_ctrl(mtd
, page_addr
>> 16, ctrl
);
641 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
644 * Program and erase have their own busy handlers status and sequential
649 case NAND_CMD_PAGEPROG
:
650 case NAND_CMD_ERASE1
:
651 case NAND_CMD_ERASE2
:
653 case NAND_CMD_STATUS
:
654 case NAND_CMD_READID
:
655 case NAND_CMD_SET_FEATURES
:
661 udelay(chip
->chip_delay
);
662 chip
->cmd_ctrl(mtd
, NAND_CMD_STATUS
,
663 NAND_CTRL_CLE
| NAND_CTRL_CHANGE
);
665 NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
666 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
667 nand_wait_status_ready(mtd
, 250);
670 /* This applies to read commands */
673 * If we don't have access to the busy pin, we apply the given
676 if (!chip
->dev_ready
) {
677 udelay(chip
->chip_delay
);
682 * Apply this short delay always to ensure that we do wait tWB in
683 * any case on any machine.
687 nand_wait_ready(mtd
);
691 * nand_command_lp - [DEFAULT] Send command to NAND large page device
692 * @mtd: MTD device structure
693 * @command: the command to be sent
694 * @column: the column address for this command, -1 if none
695 * @page_addr: the page address for this command, -1 if none
697 * Send command to NAND device. This is the version for the new large page
698 * devices. We don't have the separate regions as we have in the small page
699 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
701 static void nand_command_lp(struct mtd_info
*mtd
, unsigned int command
,
702 int column
, int page_addr
)
704 register struct nand_chip
*chip
= mtd_to_nand(mtd
);
706 /* Emulate NAND_CMD_READOOB */
707 if (command
== NAND_CMD_READOOB
) {
708 column
+= mtd
->writesize
;
709 command
= NAND_CMD_READ0
;
712 /* Command latch cycle */
713 chip
->cmd_ctrl(mtd
, command
, NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
715 if (column
!= -1 || page_addr
!= -1) {
716 int ctrl
= NAND_CTRL_CHANGE
| NAND_NCE
| NAND_ALE
;
718 /* Serially input address */
720 /* Adjust columns for 16 bit buswidth */
721 if (chip
->options
& NAND_BUSWIDTH_16
&&
722 !nand_opcode_8bits(command
))
724 chip
->cmd_ctrl(mtd
, column
, ctrl
);
725 ctrl
&= ~NAND_CTRL_CHANGE
;
726 chip
->cmd_ctrl(mtd
, column
>> 8, ctrl
);
728 if (page_addr
!= -1) {
729 chip
->cmd_ctrl(mtd
, page_addr
, ctrl
);
730 chip
->cmd_ctrl(mtd
, page_addr
>> 8,
731 NAND_NCE
| NAND_ALE
);
732 /* One more address cycle for devices > 128MiB */
733 if (chip
->chipsize
> (128 << 20))
734 chip
->cmd_ctrl(mtd
, page_addr
>> 16,
735 NAND_NCE
| NAND_ALE
);
738 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
741 * Program and erase have their own busy handlers status, sequential
742 * in and status need no delay.
746 case NAND_CMD_CACHEDPROG
:
747 case NAND_CMD_PAGEPROG
:
748 case NAND_CMD_ERASE1
:
749 case NAND_CMD_ERASE2
:
752 case NAND_CMD_STATUS
:
753 case NAND_CMD_READID
:
754 case NAND_CMD_SET_FEATURES
:
760 udelay(chip
->chip_delay
);
761 chip
->cmd_ctrl(mtd
, NAND_CMD_STATUS
,
762 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
763 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
,
764 NAND_NCE
| NAND_CTRL_CHANGE
);
765 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
766 nand_wait_status_ready(mtd
, 250);
769 case NAND_CMD_RNDOUT
:
770 /* No ready / busy check necessary */
771 chip
->cmd_ctrl(mtd
, NAND_CMD_RNDOUTSTART
,
772 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
773 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
,
774 NAND_NCE
| NAND_CTRL_CHANGE
);
778 chip
->cmd_ctrl(mtd
, NAND_CMD_READSTART
,
779 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
780 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
,
781 NAND_NCE
| NAND_CTRL_CHANGE
);
783 /* This applies to read commands */
786 * If we don't have access to the busy pin, we apply the given
789 if (!chip
->dev_ready
) {
790 udelay(chip
->chip_delay
);
796 * Apply this short delay always to ensure that we do wait tWB in
797 * any case on any machine.
801 nand_wait_ready(mtd
);
805 * panic_nand_get_device - [GENERIC] Get chip for selected access
806 * @chip: the nand chip descriptor
807 * @mtd: MTD device structure
808 * @new_state: the state which is requested
810 * Used when in panic, no locks are taken.
812 static void panic_nand_get_device(struct nand_chip
*chip
,
813 struct mtd_info
*mtd
, int new_state
)
815 /* Hardware controller shared among independent devices */
816 chip
->controller
->active
= chip
;
817 chip
->state
= new_state
;
821 * nand_get_device - [GENERIC] Get chip for selected access
822 * @mtd: MTD device structure
823 * @new_state: the state which is requested
825 * Get the device and lock it for exclusive access
828 nand_get_device(struct mtd_info
*mtd
, int new_state
)
830 struct nand_chip
*chip
= mtd_to_nand(mtd
);
831 chip
->state
= new_state
;
836 * panic_nand_wait - [GENERIC] wait until the command is done
837 * @mtd: MTD device structure
838 * @chip: NAND chip structure
841 * Wait for command done. This is a helper function for nand_wait used when
842 * we are in interrupt context. May happen when in panic and trying to write
843 * an oops through mtdoops.
845 static void panic_nand_wait(struct mtd_info
*mtd
, struct nand_chip
*chip
,
849 for (i
= 0; i
< timeo
; i
++) {
850 if (chip
->dev_ready
) {
851 if (chip
->dev_ready(mtd
))
854 if (chip
->read_byte(mtd
) & NAND_STATUS_READY
)
862 * nand_wait - [DEFAULT] wait until the command is done
863 * @mtd: MTD device structure
864 * @chip: NAND chip structure
866 * Wait for command done. This applies to erase and program only.
868 static int nand_wait(struct mtd_info
*mtd
, struct nand_chip
*chip
)
871 unsigned long timeo
= 400;
873 led_trigger_event(nand_led_trigger
, LED_FULL
);
876 * Apply this short delay always to ensure that we do wait tWB in any
877 * case on any machine.
881 chip
->cmdfunc(mtd
, NAND_CMD_STATUS
, -1, -1);
883 u32 timer
= (CONFIG_SYS_HZ
* timeo
) / 1000;
886 time_start
= get_timer(0);
887 while (get_timer(time_start
) < timer
) {
888 if (chip
->dev_ready
) {
889 if (chip
->dev_ready(mtd
))
892 if (chip
->read_byte(mtd
) & NAND_STATUS_READY
)
896 led_trigger_event(nand_led_trigger
, LED_OFF
);
898 status
= (int)chip
->read_byte(mtd
);
899 /* This can happen if in case of timeout or buggy dev_ready */
900 WARN_ON(!(status
& NAND_STATUS_READY
));
905 * nand_reset_data_interface - Reset data interface and timings
906 * @chip: The NAND chip
907 * @chipnr: Internal die id
909 * Reset the Data interface and timings to ONFI mode 0.
911 * Returns 0 for success or negative error code otherwise.
913 static int nand_reset_data_interface(struct nand_chip
*chip
, int chipnr
)
915 struct mtd_info
*mtd
= nand_to_mtd(chip
);
916 const struct nand_data_interface
*conf
;
919 if (!chip
->setup_data_interface
)
923 * The ONFI specification says:
925 * To transition from NV-DDR or NV-DDR2 to the SDR data
926 * interface, the host shall use the Reset (FFh) command
927 * using SDR timing mode 0. A device in any timing mode is
928 * required to recognize Reset (FFh) command issued in SDR
932 * Configure the data interface in SDR mode and set the
933 * timings to timing mode 0.
936 conf
= nand_get_default_data_interface();
937 ret
= chip
->setup_data_interface(mtd
, chipnr
, conf
);
939 pr_err("Failed to configure data interface to SDR timing mode 0\n");
945 * nand_setup_data_interface - Setup the best data interface and timings
946 * @chip: The NAND chip
947 * @chipnr: Internal die id
949 * Find and configure the best data interface and NAND timings supported by
950 * the chip and the driver.
951 * First tries to retrieve supported timing modes from ONFI information,
952 * and if the NAND chip does not support ONFI, relies on the
953 * ->onfi_timing_mode_default specified in the nand_ids table.
955 * Returns 0 for success or negative error code otherwise.
957 static int nand_setup_data_interface(struct nand_chip
*chip
, int chipnr
)
959 struct mtd_info
*mtd
= nand_to_mtd(chip
);
962 if (!chip
->setup_data_interface
|| !chip
->data_interface
)
966 * Ensure the timing mode has been changed on the chip side
967 * before changing timings on the controller side.
969 if (chip
->onfi_version
) {
970 u8 tmode_param
[ONFI_SUBFEATURE_PARAM_LEN
] = {
971 chip
->onfi_timing_mode_default
,
974 ret
= chip
->onfi_set_features(mtd
, chip
,
975 ONFI_FEATURE_ADDR_TIMING_MODE
,
981 ret
= chip
->setup_data_interface(mtd
, chipnr
, chip
->data_interface
);
987 * nand_init_data_interface - find the best data interface and timings
988 * @chip: The NAND chip
990 * Find the best data interface and NAND timings supported by the chip
992 * First tries to retrieve supported timing modes from ONFI information,
993 * and if the NAND chip does not support ONFI, relies on the
994 * ->onfi_timing_mode_default specified in the nand_ids table. After this
995 * function nand_chip->data_interface is initialized with the best timing mode
998 * Returns 0 for success or negative error code otherwise.
1000 static int nand_init_data_interface(struct nand_chip
*chip
)
1002 struct mtd_info
*mtd
= nand_to_mtd(chip
);
1003 int modes
, mode
, ret
;
1005 if (!chip
->setup_data_interface
)
1009 * First try to identify the best timings from ONFI parameters and
1010 * if the NAND does not support ONFI, fallback to the default ONFI
1013 modes
= onfi_get_async_timing_mode(chip
);
1014 if (modes
== ONFI_TIMING_MODE_UNKNOWN
) {
1015 if (!chip
->onfi_timing_mode_default
)
1018 modes
= GENMASK(chip
->onfi_timing_mode_default
, 0);
1021 chip
->data_interface
= kzalloc(sizeof(*chip
->data_interface
),
1023 if (!chip
->data_interface
)
1026 for (mode
= fls(modes
) - 1; mode
>= 0; mode
--) {
1027 ret
= onfi_init_data_interface(chip
, chip
->data_interface
,
1028 NAND_SDR_IFACE
, mode
);
1032 /* Pass -1 to only */
1033 ret
= chip
->setup_data_interface(mtd
,
1034 NAND_DATA_IFACE_CHECK_ONLY
,
1035 chip
->data_interface
);
1037 chip
->onfi_timing_mode_default
= mode
;
1045 static void __maybe_unused
nand_release_data_interface(struct nand_chip
*chip
)
1047 kfree(chip
->data_interface
);
1051 * nand_reset - Reset and initialize a NAND device
1052 * @chip: The NAND chip
1053 * @chipnr: Internal die id
1055 * Returns 0 for success or negative error code otherwise
1057 int nand_reset(struct nand_chip
*chip
, int chipnr
)
1059 struct mtd_info
*mtd
= nand_to_mtd(chip
);
1062 ret
= nand_reset_data_interface(chip
, chipnr
);
1067 * The CS line has to be released before we can apply the new NAND
1068 * interface settings, hence this weird ->select_chip() dance.
1070 chip
->select_chip(mtd
, chipnr
);
1071 chip
->cmdfunc(mtd
, NAND_CMD_RESET
, -1, -1);
1072 chip
->select_chip(mtd
, -1);
1074 chip
->select_chip(mtd
, chipnr
);
1075 ret
= nand_setup_data_interface(chip
, chipnr
);
1076 chip
->select_chip(mtd
, -1);
1084 * nand_check_erased_buf - check if a buffer contains (almost) only 0xff data
1085 * @buf: buffer to test
1086 * @len: buffer length
1087 * @bitflips_threshold: maximum number of bitflips
1089 * Check if a buffer contains only 0xff, which means the underlying region
1090 * has been erased and is ready to be programmed.
1091 * The bitflips_threshold specify the maximum number of bitflips before
1092 * considering the region is not erased.
1093 * Note: The logic of this function has been extracted from the memweight
1094 * implementation, except that nand_check_erased_buf function exit before
1095 * testing the whole buffer if the number of bitflips exceed the
1096 * bitflips_threshold value.
1098 * Returns a positive number of bitflips less than or equal to
1099 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
1102 static int nand_check_erased_buf(void *buf
, int len
, int bitflips_threshold
)
1104 const unsigned char *bitmap
= buf
;
1108 for (; len
&& ((uintptr_t)bitmap
) % sizeof(long);
1110 weight
= hweight8(*bitmap
);
1111 bitflips
+= BITS_PER_BYTE
- weight
;
1112 if (unlikely(bitflips
> bitflips_threshold
))
1116 for (; len
>= 4; len
-= 4, bitmap
+= 4) {
1117 weight
= hweight32(*((u32
*)bitmap
));
1118 bitflips
+= 32 - weight
;
1119 if (unlikely(bitflips
> bitflips_threshold
))
1123 for (; len
> 0; len
--, bitmap
++) {
1124 weight
= hweight8(*bitmap
);
1125 bitflips
+= BITS_PER_BYTE
- weight
;
1126 if (unlikely(bitflips
> bitflips_threshold
))
1134 * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only
1136 * @data: data buffer to test
1137 * @datalen: data length
1139 * @ecclen: ECC length
1140 * @extraoob: extra OOB buffer
1141 * @extraooblen: extra OOB length
1142 * @bitflips_threshold: maximum number of bitflips
1144 * Check if a data buffer and its associated ECC and OOB data contains only
1145 * 0xff pattern, which means the underlying region has been erased and is
1146 * ready to be programmed.
1147 * The bitflips_threshold specify the maximum number of bitflips before
1148 * considering the region as not erased.
1151 * 1/ ECC algorithms are working on pre-defined block sizes which are usually
1152 * different from the NAND page size. When fixing bitflips, ECC engines will
1153 * report the number of errors per chunk, and the NAND core infrastructure
1154 * expect you to return the maximum number of bitflips for the whole page.
1155 * This is why you should always use this function on a single chunk and
1156 * not on the whole page. After checking each chunk you should update your
1157 * max_bitflips value accordingly.
1158 * 2/ When checking for bitflips in erased pages you should not only check
1159 * the payload data but also their associated ECC data, because a user might
1160 * have programmed almost all bits to 1 but a few. In this case, we
1161 * shouldn't consider the chunk as erased, and checking ECC bytes prevent
1163 * 3/ The extraoob argument is optional, and should be used if some of your OOB
1164 * data are protected by the ECC engine.
1165 * It could also be used if you support subpages and want to attach some
1166 * extra OOB data to an ECC chunk.
1168 * Returns a positive number of bitflips less than or equal to
1169 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
1170 * threshold. In case of success, the passed buffers are filled with 0xff.
1172 int nand_check_erased_ecc_chunk(void *data
, int datalen
,
1173 void *ecc
, int ecclen
,
1174 void *extraoob
, int extraooblen
,
1175 int bitflips_threshold
)
1177 int data_bitflips
= 0, ecc_bitflips
= 0, extraoob_bitflips
= 0;
1179 data_bitflips
= nand_check_erased_buf(data
, datalen
,
1180 bitflips_threshold
);
1181 if (data_bitflips
< 0)
1182 return data_bitflips
;
1184 bitflips_threshold
-= data_bitflips
;
1186 ecc_bitflips
= nand_check_erased_buf(ecc
, ecclen
, bitflips_threshold
);
1187 if (ecc_bitflips
< 0)
1188 return ecc_bitflips
;
1190 bitflips_threshold
-= ecc_bitflips
;
1192 extraoob_bitflips
= nand_check_erased_buf(extraoob
, extraooblen
,
1193 bitflips_threshold
);
1194 if (extraoob_bitflips
< 0)
1195 return extraoob_bitflips
;
1198 memset(data
, 0xff, datalen
);
1201 memset(ecc
, 0xff, ecclen
);
1203 if (extraoob_bitflips
)
1204 memset(extraoob
, 0xff, extraooblen
);
1206 return data_bitflips
+ ecc_bitflips
+ extraoob_bitflips
;
1208 EXPORT_SYMBOL(nand_check_erased_ecc_chunk
);
1211 * nand_read_page_raw - [INTERN] read raw page data without ecc
1212 * @mtd: mtd info structure
1213 * @chip: nand chip info structure
1214 * @buf: buffer to store read data
1215 * @oob_required: caller requires OOB data read to chip->oob_poi
1216 * @page: page number to read
1218 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1220 static int nand_read_page_raw(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1221 uint8_t *buf
, int oob_required
, int page
)
1223 chip
->read_buf(mtd
, buf
, mtd
->writesize
);
1225 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1230 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1231 * @mtd: mtd info structure
1232 * @chip: nand chip info structure
1233 * @buf: buffer to store read data
1234 * @oob_required: caller requires OOB data read to chip->oob_poi
1235 * @page: page number to read
1237 * We need a special oob layout and handling even when OOB isn't used.
1239 static int nand_read_page_raw_syndrome(struct mtd_info
*mtd
,
1240 struct nand_chip
*chip
, uint8_t *buf
,
1241 int oob_required
, int page
)
1243 int eccsize
= chip
->ecc
.size
;
1244 int eccbytes
= chip
->ecc
.bytes
;
1245 uint8_t *oob
= chip
->oob_poi
;
1248 for (steps
= chip
->ecc
.steps
; steps
> 0; steps
--) {
1249 chip
->read_buf(mtd
, buf
, eccsize
);
1252 if (chip
->ecc
.prepad
) {
1253 chip
->read_buf(mtd
, oob
, chip
->ecc
.prepad
);
1254 oob
+= chip
->ecc
.prepad
;
1257 chip
->read_buf(mtd
, oob
, eccbytes
);
1260 if (chip
->ecc
.postpad
) {
1261 chip
->read_buf(mtd
, oob
, chip
->ecc
.postpad
);
1262 oob
+= chip
->ecc
.postpad
;
1266 size
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
1268 chip
->read_buf(mtd
, oob
, size
);
1274 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1275 * @mtd: mtd info structure
1276 * @chip: nand chip info structure
1277 * @buf: buffer to store read data
1278 * @oob_required: caller requires OOB data read to chip->oob_poi
1279 * @page: page number to read
1281 static int nand_read_page_swecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1282 uint8_t *buf
, int oob_required
, int page
)
1284 int i
, eccsize
= chip
->ecc
.size
;
1285 int eccbytes
= chip
->ecc
.bytes
;
1286 int eccsteps
= chip
->ecc
.steps
;
1288 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1289 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
1290 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1291 unsigned int max_bitflips
= 0;
1293 chip
->ecc
.read_page_raw(mtd
, chip
, buf
, 1, page
);
1295 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
)
1296 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1298 for (i
= 0; i
< chip
->ecc
.total
; i
++)
1299 ecc_code
[i
] = chip
->oob_poi
[eccpos
[i
]];
1301 eccsteps
= chip
->ecc
.steps
;
1304 for (i
= 0 ; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1307 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], &ecc_calc
[i
]);
1309 mtd
->ecc_stats
.failed
++;
1311 mtd
->ecc_stats
.corrected
+= stat
;
1312 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1315 return max_bitflips
;
1319 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
1320 * @mtd: mtd info structure
1321 * @chip: nand chip info structure
1322 * @data_offs: offset of requested data within the page
1323 * @readlen: data length
1324 * @bufpoi: buffer to store read data
1325 * @page: page number to read
1327 static int nand_read_subpage(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1328 uint32_t data_offs
, uint32_t readlen
, uint8_t *bufpoi
,
1331 int start_step
, end_step
, num_steps
;
1332 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1334 int data_col_addr
, i
, gaps
= 0;
1335 int datafrag_len
, eccfrag_len
, aligned_len
, aligned_pos
;
1336 int busw
= (chip
->options
& NAND_BUSWIDTH_16
) ? 2 : 1;
1338 unsigned int max_bitflips
= 0;
1340 /* Column address within the page aligned to ECC size (256bytes) */
1341 start_step
= data_offs
/ chip
->ecc
.size
;
1342 end_step
= (data_offs
+ readlen
- 1) / chip
->ecc
.size
;
1343 num_steps
= end_step
- start_step
+ 1;
1344 index
= start_step
* chip
->ecc
.bytes
;
1346 /* Data size aligned to ECC ecc.size */
1347 datafrag_len
= num_steps
* chip
->ecc
.size
;
1348 eccfrag_len
= num_steps
* chip
->ecc
.bytes
;
1350 data_col_addr
= start_step
* chip
->ecc
.size
;
1351 /* If we read not a page aligned data */
1352 if (data_col_addr
!= 0)
1353 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, data_col_addr
, -1);
1355 p
= bufpoi
+ data_col_addr
;
1356 chip
->read_buf(mtd
, p
, datafrag_len
);
1359 for (i
= 0; i
< eccfrag_len
; i
+= chip
->ecc
.bytes
, p
+= chip
->ecc
.size
)
1360 chip
->ecc
.calculate(mtd
, p
, &chip
->buffers
->ecccalc
[i
]);
1363 * The performance is faster if we position offsets according to
1364 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1366 for (i
= 0; i
< eccfrag_len
- 1; i
++) {
1367 if (eccpos
[i
+ index
] + 1 != eccpos
[i
+ index
+ 1]) {
1373 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, mtd
->writesize
, -1);
1374 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1377 * Send the command to read the particular ECC bytes take care
1378 * about buswidth alignment in read_buf.
1380 aligned_pos
= eccpos
[index
] & ~(busw
- 1);
1381 aligned_len
= eccfrag_len
;
1382 if (eccpos
[index
] & (busw
- 1))
1384 if (eccpos
[index
+ (num_steps
* chip
->ecc
.bytes
)] & (busw
- 1))
1387 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
,
1388 mtd
->writesize
+ aligned_pos
, -1);
1389 chip
->read_buf(mtd
, &chip
->oob_poi
[aligned_pos
], aligned_len
);
1392 for (i
= 0; i
< eccfrag_len
; i
++)
1393 chip
->buffers
->ecccode
[i
] = chip
->oob_poi
[eccpos
[i
+ index
]];
1395 p
= bufpoi
+ data_col_addr
;
1396 for (i
= 0; i
< eccfrag_len
; i
+= chip
->ecc
.bytes
, p
+= chip
->ecc
.size
) {
1399 stat
= chip
->ecc
.correct(mtd
, p
,
1400 &chip
->buffers
->ecccode
[i
], &chip
->buffers
->ecccalc
[i
]);
1401 if (stat
== -EBADMSG
&&
1402 (chip
->ecc
.options
& NAND_ECC_GENERIC_ERASED_CHECK
)) {
1403 /* check for empty pages with bitflips */
1404 stat
= nand_check_erased_ecc_chunk(p
, chip
->ecc
.size
,
1405 &chip
->buffers
->ecccode
[i
],
1408 chip
->ecc
.strength
);
1412 mtd
->ecc_stats
.failed
++;
1414 mtd
->ecc_stats
.corrected
+= stat
;
1415 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1418 return max_bitflips
;
1422 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1423 * @mtd: mtd info structure
1424 * @chip: nand chip info structure
1425 * @buf: buffer to store read data
1426 * @oob_required: caller requires OOB data read to chip->oob_poi
1427 * @page: page number to read
1429 * Not for syndrome calculating ECC controllers which need a special oob layout.
1431 static int nand_read_page_hwecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1432 uint8_t *buf
, int oob_required
, int page
)
1434 int i
, eccsize
= chip
->ecc
.size
;
1435 int eccbytes
= chip
->ecc
.bytes
;
1436 int eccsteps
= chip
->ecc
.steps
;
1438 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1439 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
1440 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1441 unsigned int max_bitflips
= 0;
1443 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1444 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1445 chip
->read_buf(mtd
, p
, eccsize
);
1446 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1448 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1450 for (i
= 0; i
< chip
->ecc
.total
; i
++)
1451 ecc_code
[i
] = chip
->oob_poi
[eccpos
[i
]];
1453 eccsteps
= chip
->ecc
.steps
;
1456 for (i
= 0 ; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1459 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], &ecc_calc
[i
]);
1460 if (stat
== -EBADMSG
&&
1461 (chip
->ecc
.options
& NAND_ECC_GENERIC_ERASED_CHECK
)) {
1462 /* check for empty pages with bitflips */
1463 stat
= nand_check_erased_ecc_chunk(p
, eccsize
,
1464 &ecc_code
[i
], eccbytes
,
1466 chip
->ecc
.strength
);
1470 mtd
->ecc_stats
.failed
++;
1472 mtd
->ecc_stats
.corrected
+= stat
;
1473 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1476 return max_bitflips
;
1480 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1481 * @mtd: mtd info structure
1482 * @chip: nand chip info structure
1483 * @buf: buffer to store read data
1484 * @oob_required: caller requires OOB data read to chip->oob_poi
1485 * @page: page number to read
1487 * Hardware ECC for large page chips, require OOB to be read first. For this
1488 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1489 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1490 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1491 * the data area, by overwriting the NAND manufacturer bad block markings.
1493 static int nand_read_page_hwecc_oob_first(struct mtd_info
*mtd
,
1494 struct nand_chip
*chip
, uint8_t *buf
, int oob_required
, int page
)
1496 int i
, eccsize
= chip
->ecc
.size
;
1497 int eccbytes
= chip
->ecc
.bytes
;
1498 int eccsteps
= chip
->ecc
.steps
;
1500 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
1501 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1502 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1503 unsigned int max_bitflips
= 0;
1505 /* Read the OOB area first */
1506 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, 0, page
);
1507 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1508 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, 0, page
);
1510 for (i
= 0; i
< chip
->ecc
.total
; i
++)
1511 ecc_code
[i
] = chip
->oob_poi
[eccpos
[i
]];
1513 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1516 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1517 chip
->read_buf(mtd
, p
, eccsize
);
1518 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1520 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], NULL
);
1521 if (stat
== -EBADMSG
&&
1522 (chip
->ecc
.options
& NAND_ECC_GENERIC_ERASED_CHECK
)) {
1523 /* check for empty pages with bitflips */
1524 stat
= nand_check_erased_ecc_chunk(p
, eccsize
,
1525 &ecc_code
[i
], eccbytes
,
1527 chip
->ecc
.strength
);
1531 mtd
->ecc_stats
.failed
++;
1533 mtd
->ecc_stats
.corrected
+= stat
;
1534 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1537 return max_bitflips
;
1541 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1542 * @mtd: mtd info structure
1543 * @chip: nand chip info structure
1544 * @buf: buffer to store read data
1545 * @oob_required: caller requires OOB data read to chip->oob_poi
1546 * @page: page number to read
1548 * The hw generator calculates the error syndrome automatically. Therefore we
1549 * need a special oob layout and handling.
1551 static int nand_read_page_syndrome(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1552 uint8_t *buf
, int oob_required
, int page
)
1554 int i
, eccsize
= chip
->ecc
.size
;
1555 int eccbytes
= chip
->ecc
.bytes
;
1556 int eccsteps
= chip
->ecc
.steps
;
1557 int eccpadbytes
= eccbytes
+ chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
1559 uint8_t *oob
= chip
->oob_poi
;
1560 unsigned int max_bitflips
= 0;
1562 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1565 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1566 chip
->read_buf(mtd
, p
, eccsize
);
1568 if (chip
->ecc
.prepad
) {
1569 chip
->read_buf(mtd
, oob
, chip
->ecc
.prepad
);
1570 oob
+= chip
->ecc
.prepad
;
1573 chip
->ecc
.hwctl(mtd
, NAND_ECC_READSYN
);
1574 chip
->read_buf(mtd
, oob
, eccbytes
);
1575 stat
= chip
->ecc
.correct(mtd
, p
, oob
, NULL
);
1579 if (chip
->ecc
.postpad
) {
1580 chip
->read_buf(mtd
, oob
, chip
->ecc
.postpad
);
1581 oob
+= chip
->ecc
.postpad
;
1584 if (stat
== -EBADMSG
&&
1585 (chip
->ecc
.options
& NAND_ECC_GENERIC_ERASED_CHECK
)) {
1586 /* check for empty pages with bitflips */
1587 stat
= nand_check_erased_ecc_chunk(p
, chip
->ecc
.size
,
1591 chip
->ecc
.strength
);
1595 mtd
->ecc_stats
.failed
++;
1597 mtd
->ecc_stats
.corrected
+= stat
;
1598 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1602 /* Calculate remaining oob bytes */
1603 i
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
1605 chip
->read_buf(mtd
, oob
, i
);
1607 return max_bitflips
;
1611 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1612 * @chip: nand chip structure
1613 * @oob: oob destination address
1614 * @ops: oob ops structure
1615 * @len: size of oob to transfer
1617 static uint8_t *nand_transfer_oob(struct nand_chip
*chip
, uint8_t *oob
,
1618 struct mtd_oob_ops
*ops
, size_t len
)
1620 switch (ops
->mode
) {
1622 case MTD_OPS_PLACE_OOB
:
1624 memcpy(oob
, chip
->oob_poi
+ ops
->ooboffs
, len
);
1627 case MTD_OPS_AUTO_OOB
: {
1628 struct nand_oobfree
*free
= chip
->ecc
.layout
->oobfree
;
1629 uint32_t boffs
= 0, roffs
= ops
->ooboffs
;
1632 for (; free
->length
&& len
; free
++, len
-= bytes
) {
1633 /* Read request not from offset 0? */
1634 if (unlikely(roffs
)) {
1635 if (roffs
>= free
->length
) {
1636 roffs
-= free
->length
;
1639 boffs
= free
->offset
+ roffs
;
1640 bytes
= min_t(size_t, len
,
1641 (free
->length
- roffs
));
1644 bytes
= min_t(size_t, len
, free
->length
);
1645 boffs
= free
->offset
;
1647 memcpy(oob
, chip
->oob_poi
+ boffs
, bytes
);
1659 * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
1660 * @mtd: MTD device structure
1661 * @retry_mode: the retry mode to use
1663 * Some vendors supply a special command to shift the Vt threshold, to be used
1664 * when there are too many bitflips in a page (i.e., ECC error). After setting
1665 * a new threshold, the host should retry reading the page.
1667 static int nand_setup_read_retry(struct mtd_info
*mtd
, int retry_mode
)
1669 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1671 pr_debug("setting READ RETRY mode %d\n", retry_mode
);
1673 if (retry_mode
>= chip
->read_retries
)
1676 if (!chip
->setup_read_retry
)
1679 return chip
->setup_read_retry(mtd
, retry_mode
);
1683 * nand_do_read_ops - [INTERN] Read data with ECC
1684 * @mtd: MTD device structure
1685 * @from: offset to read from
1686 * @ops: oob ops structure
1688 * Internal function. Called with chip held.
1690 static int nand_do_read_ops(struct mtd_info
*mtd
, loff_t from
,
1691 struct mtd_oob_ops
*ops
)
1693 int chipnr
, page
, realpage
, col
, bytes
, aligned
, oob_required
;
1694 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1696 uint32_t readlen
= ops
->len
;
1697 uint32_t oobreadlen
= ops
->ooblen
;
1698 uint32_t max_oobsize
= mtd_oobavail(mtd
, ops
);
1700 uint8_t *bufpoi
, *oob
, *buf
;
1702 unsigned int max_bitflips
= 0;
1704 bool ecc_fail
= false;
1706 chipnr
= (int)(from
>> chip
->chip_shift
);
1707 chip
->select_chip(mtd
, chipnr
);
1709 realpage
= (int)(from
>> chip
->page_shift
);
1710 page
= realpage
& chip
->pagemask
;
1712 col
= (int)(from
& (mtd
->writesize
- 1));
1716 oob_required
= oob
? 1 : 0;
1719 unsigned int ecc_failures
= mtd
->ecc_stats
.failed
;
1722 bytes
= min(mtd
->writesize
- col
, readlen
);
1723 aligned
= (bytes
== mtd
->writesize
);
1727 else if (chip
->options
& NAND_USE_BOUNCE_BUFFER
)
1728 use_bufpoi
= !IS_ALIGNED((unsigned long)buf
,
1733 /* Is the current page in the buffer? */
1734 if (realpage
!= chip
->pagebuf
|| oob
) {
1735 bufpoi
= use_bufpoi
? chip
->buffers
->databuf
: buf
;
1737 if (use_bufpoi
&& aligned
)
1738 pr_debug("%s: using read bounce buffer for buf@%p\n",
1742 if (nand_standard_page_accessors(&chip
->ecc
))
1743 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, 0x00, page
);
1746 * Now read the page into the buffer. Absent an error,
1747 * the read methods return max bitflips per ecc step.
1749 if (unlikely(ops
->mode
== MTD_OPS_RAW
))
1750 ret
= chip
->ecc
.read_page_raw(mtd
, chip
, bufpoi
,
1753 else if (!aligned
&& NAND_HAS_SUBPAGE_READ(chip
) &&
1755 ret
= chip
->ecc
.read_subpage(mtd
, chip
,
1759 ret
= chip
->ecc
.read_page(mtd
, chip
, bufpoi
,
1760 oob_required
, page
);
1763 /* Invalidate page cache */
1768 max_bitflips
= max_t(unsigned int, max_bitflips
, ret
);
1770 /* Transfer not aligned data */
1772 if (!NAND_HAS_SUBPAGE_READ(chip
) && !oob
&&
1773 !(mtd
->ecc_stats
.failed
- ecc_failures
) &&
1774 (ops
->mode
!= MTD_OPS_RAW
)) {
1775 chip
->pagebuf
= realpage
;
1776 chip
->pagebuf_bitflips
= ret
;
1778 /* Invalidate page cache */
1781 memcpy(buf
, chip
->buffers
->databuf
+ col
, bytes
);
1784 if (unlikely(oob
)) {
1785 int toread
= min(oobreadlen
, max_oobsize
);
1788 oob
= nand_transfer_oob(chip
,
1790 oobreadlen
-= toread
;
1794 if (chip
->options
& NAND_NEED_READRDY
) {
1795 /* Apply delay or wait for ready/busy pin */
1796 if (!chip
->dev_ready
)
1797 udelay(chip
->chip_delay
);
1799 nand_wait_ready(mtd
);
1802 if (mtd
->ecc_stats
.failed
- ecc_failures
) {
1803 if (retry_mode
+ 1 < chip
->read_retries
) {
1805 ret
= nand_setup_read_retry(mtd
,
1810 /* Reset failures; retry */
1811 mtd
->ecc_stats
.failed
= ecc_failures
;
1814 /* No more retry modes; real failure */
1821 memcpy(buf
, chip
->buffers
->databuf
+ col
, bytes
);
1823 max_bitflips
= max_t(unsigned int, max_bitflips
,
1824 chip
->pagebuf_bitflips
);
1829 /* Reset to retry mode 0 */
1831 ret
= nand_setup_read_retry(mtd
, 0);
1840 /* For subsequent reads align to page boundary */
1842 /* Increment page address */
1845 page
= realpage
& chip
->pagemask
;
1846 /* Check, if we cross a chip boundary */
1849 chip
->select_chip(mtd
, -1);
1850 chip
->select_chip(mtd
, chipnr
);
1853 chip
->select_chip(mtd
, -1);
1855 ops
->retlen
= ops
->len
- (size_t) readlen
;
1857 ops
->oobretlen
= ops
->ooblen
- oobreadlen
;
1865 return max_bitflips
;
1869 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1870 * @mtd: MTD device structure
1871 * @from: offset to read from
1872 * @len: number of bytes to read
1873 * @retlen: pointer to variable to store the number of read bytes
1874 * @buf: the databuffer to put data
1876 * Get hold of the chip and call nand_do_read.
1878 static int nand_read(struct mtd_info
*mtd
, loff_t from
, size_t len
,
1879 size_t *retlen
, uint8_t *buf
)
1881 struct mtd_oob_ops ops
;
1884 nand_get_device(mtd
, FL_READING
);
1885 memset(&ops
, 0, sizeof(ops
));
1888 ops
.mode
= MTD_OPS_PLACE_OOB
;
1889 ret
= nand_do_read_ops(mtd
, from
, &ops
);
1890 *retlen
= ops
.retlen
;
1891 nand_release_device(mtd
);
1896 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
1897 * @mtd: mtd info structure
1898 * @chip: nand chip info structure
1899 * @page: page number to read
1901 static int nand_read_oob_std(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1904 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, 0, page
);
1905 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1910 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
1912 * @mtd: mtd info structure
1913 * @chip: nand chip info structure
1914 * @page: page number to read
1916 static int nand_read_oob_syndrome(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1919 int length
= mtd
->oobsize
;
1920 int chunk
= chip
->ecc
.bytes
+ chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
1921 int eccsize
= chip
->ecc
.size
;
1922 uint8_t *bufpoi
= chip
->oob_poi
;
1923 int i
, toread
, sndrnd
= 0, pos
;
1925 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, chip
->ecc
.size
, page
);
1926 for (i
= 0; i
< chip
->ecc
.steps
; i
++) {
1928 pos
= eccsize
+ i
* (eccsize
+ chunk
);
1929 if (mtd
->writesize
> 512)
1930 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, pos
, -1);
1932 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, pos
, page
);
1935 toread
= min_t(int, length
, chunk
);
1936 chip
->read_buf(mtd
, bufpoi
, toread
);
1941 chip
->read_buf(mtd
, bufpoi
, length
);
1947 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
1948 * @mtd: mtd info structure
1949 * @chip: nand chip info structure
1950 * @page: page number to write
1952 static int nand_write_oob_std(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1956 const uint8_t *buf
= chip
->oob_poi
;
1957 int length
= mtd
->oobsize
;
1959 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, mtd
->writesize
, page
);
1960 chip
->write_buf(mtd
, buf
, length
);
1961 /* Send command to program the OOB data */
1962 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
1964 status
= chip
->waitfunc(mtd
, chip
);
1966 return status
& NAND_STATUS_FAIL
? -EIO
: 0;
1970 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
1971 * with syndrome - only for large page flash
1972 * @mtd: mtd info structure
1973 * @chip: nand chip info structure
1974 * @page: page number to write
1976 static int nand_write_oob_syndrome(struct mtd_info
*mtd
,
1977 struct nand_chip
*chip
, int page
)
1979 int chunk
= chip
->ecc
.bytes
+ chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
1980 int eccsize
= chip
->ecc
.size
, length
= mtd
->oobsize
;
1981 int i
, len
, pos
, status
= 0, sndcmd
= 0, steps
= chip
->ecc
.steps
;
1982 const uint8_t *bufpoi
= chip
->oob_poi
;
1985 * data-ecc-data-ecc ... ecc-oob
1987 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1989 if (!chip
->ecc
.prepad
&& !chip
->ecc
.postpad
) {
1990 pos
= steps
* (eccsize
+ chunk
);
1995 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, pos
, page
);
1996 for (i
= 0; i
< steps
; i
++) {
1998 if (mtd
->writesize
<= 512) {
1999 uint32_t fill
= 0xFFFFFFFF;
2003 int num
= min_t(int, len
, 4);
2004 chip
->write_buf(mtd
, (uint8_t *)&fill
,
2009 pos
= eccsize
+ i
* (eccsize
+ chunk
);
2010 chip
->cmdfunc(mtd
, NAND_CMD_RNDIN
, pos
, -1);
2014 len
= min_t(int, length
, chunk
);
2015 chip
->write_buf(mtd
, bufpoi
, len
);
2020 chip
->write_buf(mtd
, bufpoi
, length
);
2022 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
2023 status
= chip
->waitfunc(mtd
, chip
);
2025 return status
& NAND_STATUS_FAIL
? -EIO
: 0;
2029 * nand_do_read_oob - [INTERN] NAND read out-of-band
2030 * @mtd: MTD device structure
2031 * @from: offset to read from
2032 * @ops: oob operations description structure
2034 * NAND read out-of-band data from the spare area.
2036 static int nand_do_read_oob(struct mtd_info
*mtd
, loff_t from
,
2037 struct mtd_oob_ops
*ops
)
2039 int page
, realpage
, chipnr
;
2040 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2041 struct mtd_ecc_stats stats
;
2042 int readlen
= ops
->ooblen
;
2044 uint8_t *buf
= ops
->oobbuf
;
2047 pr_debug("%s: from = 0x%08Lx, len = %i\n",
2048 __func__
, (unsigned long long)from
, readlen
);
2050 stats
= mtd
->ecc_stats
;
2052 len
= mtd_oobavail(mtd
, ops
);
2054 if (unlikely(ops
->ooboffs
>= len
)) {
2055 pr_debug("%s: attempt to start read outside oob\n",
2060 /* Do not allow reads past end of device */
2061 if (unlikely(from
>= mtd
->size
||
2062 ops
->ooboffs
+ readlen
> ((mtd
->size
>> chip
->page_shift
) -
2063 (from
>> chip
->page_shift
)) * len
)) {
2064 pr_debug("%s: attempt to read beyond end of device\n",
2069 chipnr
= (int)(from
>> chip
->chip_shift
);
2070 chip
->select_chip(mtd
, chipnr
);
2072 /* Shift to get page */
2073 realpage
= (int)(from
>> chip
->page_shift
);
2074 page
= realpage
& chip
->pagemask
;
2079 if (ops
->mode
== MTD_OPS_RAW
)
2080 ret
= chip
->ecc
.read_oob_raw(mtd
, chip
, page
);
2082 ret
= chip
->ecc
.read_oob(mtd
, chip
, page
);
2087 len
= min(len
, readlen
);
2088 buf
= nand_transfer_oob(chip
, buf
, ops
, len
);
2090 if (chip
->options
& NAND_NEED_READRDY
) {
2091 /* Apply delay or wait for ready/busy pin */
2092 if (!chip
->dev_ready
)
2093 udelay(chip
->chip_delay
);
2095 nand_wait_ready(mtd
);
2102 /* Increment page address */
2105 page
= realpage
& chip
->pagemask
;
2106 /* Check, if we cross a chip boundary */
2109 chip
->select_chip(mtd
, -1);
2110 chip
->select_chip(mtd
, chipnr
);
2113 chip
->select_chip(mtd
, -1);
2115 ops
->oobretlen
= ops
->ooblen
- readlen
;
2120 if (mtd
->ecc_stats
.failed
- stats
.failed
)
2123 return mtd
->ecc_stats
.corrected
- stats
.corrected
? -EUCLEAN
: 0;
2127 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
2128 * @mtd: MTD device structure
2129 * @from: offset to read from
2130 * @ops: oob operation description structure
2132 * NAND read data and/or out-of-band data.
2134 static int nand_read_oob(struct mtd_info
*mtd
, loff_t from
,
2135 struct mtd_oob_ops
*ops
)
2137 int ret
= -ENOTSUPP
;
2141 /* Do not allow reads past end of device */
2142 if (ops
->datbuf
&& (from
+ ops
->len
) > mtd
->size
) {
2143 pr_debug("%s: attempt to read beyond end of device\n",
2148 nand_get_device(mtd
, FL_READING
);
2150 switch (ops
->mode
) {
2151 case MTD_OPS_PLACE_OOB
:
2152 case MTD_OPS_AUTO_OOB
:
2161 ret
= nand_do_read_oob(mtd
, from
, ops
);
2163 ret
= nand_do_read_ops(mtd
, from
, ops
);
2166 nand_release_device(mtd
);
2172 * nand_write_page_raw - [INTERN] raw page write function
2173 * @mtd: mtd info structure
2174 * @chip: nand chip info structure
2176 * @oob_required: must write chip->oob_poi to OOB
2177 * @page: page number to write
2179 * Not for syndrome calculating ECC controllers, which use a special oob layout.
2181 static int nand_write_page_raw(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2182 const uint8_t *buf
, int oob_required
, int page
)
2184 chip
->write_buf(mtd
, buf
, mtd
->writesize
);
2186 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
2192 * nand_write_page_raw_syndrome - [INTERN] raw page write function
2193 * @mtd: mtd info structure
2194 * @chip: nand chip info structure
2196 * @oob_required: must write chip->oob_poi to OOB
2197 * @page: page number to write
2199 * We need a special oob layout and handling even when ECC isn't checked.
2201 static int nand_write_page_raw_syndrome(struct mtd_info
*mtd
,
2202 struct nand_chip
*chip
,
2203 const uint8_t *buf
, int oob_required
,
2206 int eccsize
= chip
->ecc
.size
;
2207 int eccbytes
= chip
->ecc
.bytes
;
2208 uint8_t *oob
= chip
->oob_poi
;
2211 for (steps
= chip
->ecc
.steps
; steps
> 0; steps
--) {
2212 chip
->write_buf(mtd
, buf
, eccsize
);
2215 if (chip
->ecc
.prepad
) {
2216 chip
->write_buf(mtd
, oob
, chip
->ecc
.prepad
);
2217 oob
+= chip
->ecc
.prepad
;
2220 chip
->write_buf(mtd
, oob
, eccbytes
);
2223 if (chip
->ecc
.postpad
) {
2224 chip
->write_buf(mtd
, oob
, chip
->ecc
.postpad
);
2225 oob
+= chip
->ecc
.postpad
;
2229 size
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
2231 chip
->write_buf(mtd
, oob
, size
);
2236 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
2237 * @mtd: mtd info structure
2238 * @chip: nand chip info structure
2240 * @oob_required: must write chip->oob_poi to OOB
2241 * @page: page number to write
2243 static int nand_write_page_swecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2244 const uint8_t *buf
, int oob_required
,
2247 int i
, eccsize
= chip
->ecc
.size
;
2248 int eccbytes
= chip
->ecc
.bytes
;
2249 int eccsteps
= chip
->ecc
.steps
;
2250 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
2251 const uint8_t *p
= buf
;
2252 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
2254 /* Software ECC calculation */
2255 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
)
2256 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
2258 for (i
= 0; i
< chip
->ecc
.total
; i
++)
2259 chip
->oob_poi
[eccpos
[i
]] = ecc_calc
[i
];
2261 return chip
->ecc
.write_page_raw(mtd
, chip
, buf
, 1, page
);
2265 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
2266 * @mtd: mtd info structure
2267 * @chip: nand chip info structure
2269 * @oob_required: must write chip->oob_poi to OOB
2270 * @page: page number to write
2272 static int nand_write_page_hwecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2273 const uint8_t *buf
, int oob_required
,
2276 int i
, eccsize
= chip
->ecc
.size
;
2277 int eccbytes
= chip
->ecc
.bytes
;
2278 int eccsteps
= chip
->ecc
.steps
;
2279 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
2280 const uint8_t *p
= buf
;
2281 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
2283 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
2284 chip
->ecc
.hwctl(mtd
, NAND_ECC_WRITE
);
2285 chip
->write_buf(mtd
, p
, eccsize
);
2286 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
2289 for (i
= 0; i
< chip
->ecc
.total
; i
++)
2290 chip
->oob_poi
[eccpos
[i
]] = ecc_calc
[i
];
2292 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
2299 * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write
2300 * @mtd: mtd info structure
2301 * @chip: nand chip info structure
2302 * @offset: column address of subpage within the page
2303 * @data_len: data length
2305 * @oob_required: must write chip->oob_poi to OOB
2306 * @page: page number to write
2308 static int nand_write_subpage_hwecc(struct mtd_info
*mtd
,
2309 struct nand_chip
*chip
, uint32_t offset
,
2310 uint32_t data_len
, const uint8_t *buf
,
2311 int oob_required
, int page
)
2313 uint8_t *oob_buf
= chip
->oob_poi
;
2314 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
2315 int ecc_size
= chip
->ecc
.size
;
2316 int ecc_bytes
= chip
->ecc
.bytes
;
2317 int ecc_steps
= chip
->ecc
.steps
;
2318 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
2319 uint32_t start_step
= offset
/ ecc_size
;
2320 uint32_t end_step
= (offset
+ data_len
- 1) / ecc_size
;
2321 int oob_bytes
= mtd
->oobsize
/ ecc_steps
;
2324 for (step
= 0; step
< ecc_steps
; step
++) {
2325 /* configure controller for WRITE access */
2326 chip
->ecc
.hwctl(mtd
, NAND_ECC_WRITE
);
2328 /* write data (untouched subpages already masked by 0xFF) */
2329 chip
->write_buf(mtd
, buf
, ecc_size
);
2331 /* mask ECC of un-touched subpages by padding 0xFF */
2332 if ((step
< start_step
) || (step
> end_step
))
2333 memset(ecc_calc
, 0xff, ecc_bytes
);
2335 chip
->ecc
.calculate(mtd
, buf
, ecc_calc
);
2337 /* mask OOB of un-touched subpages by padding 0xFF */
2338 /* if oob_required, preserve OOB metadata of written subpage */
2339 if (!oob_required
|| (step
< start_step
) || (step
> end_step
))
2340 memset(oob_buf
, 0xff, oob_bytes
);
2343 ecc_calc
+= ecc_bytes
;
2344 oob_buf
+= oob_bytes
;
2347 /* copy calculated ECC for whole page to chip->buffer->oob */
2348 /* this include masked-value(0xFF) for unwritten subpages */
2349 ecc_calc
= chip
->buffers
->ecccalc
;
2350 for (i
= 0; i
< chip
->ecc
.total
; i
++)
2351 chip
->oob_poi
[eccpos
[i
]] = ecc_calc
[i
];
2353 /* write OOB buffer to NAND device */
2354 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
2361 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
2362 * @mtd: mtd info structure
2363 * @chip: nand chip info structure
2365 * @oob_required: must write chip->oob_poi to OOB
2366 * @page: page number to write
2368 * The hw generator calculates the error syndrome automatically. Therefore we
2369 * need a special oob layout and handling.
2371 static int nand_write_page_syndrome(struct mtd_info
*mtd
,
2372 struct nand_chip
*chip
,
2373 const uint8_t *buf
, int oob_required
,
2376 int i
, eccsize
= chip
->ecc
.size
;
2377 int eccbytes
= chip
->ecc
.bytes
;
2378 int eccsteps
= chip
->ecc
.steps
;
2379 const uint8_t *p
= buf
;
2380 uint8_t *oob
= chip
->oob_poi
;
2382 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
2384 chip
->ecc
.hwctl(mtd
, NAND_ECC_WRITE
);
2385 chip
->write_buf(mtd
, p
, eccsize
);
2387 if (chip
->ecc
.prepad
) {
2388 chip
->write_buf(mtd
, oob
, chip
->ecc
.prepad
);
2389 oob
+= chip
->ecc
.prepad
;
2392 chip
->ecc
.calculate(mtd
, p
, oob
);
2393 chip
->write_buf(mtd
, oob
, eccbytes
);
2396 if (chip
->ecc
.postpad
) {
2397 chip
->write_buf(mtd
, oob
, chip
->ecc
.postpad
);
2398 oob
+= chip
->ecc
.postpad
;
2402 /* Calculate remaining oob bytes */
2403 i
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
2405 chip
->write_buf(mtd
, oob
, i
);
2411 * nand_write_page - [REPLACEABLE] write one page
2412 * @mtd: MTD device structure
2413 * @chip: NAND chip descriptor
2414 * @offset: address offset within the page
2415 * @data_len: length of actual data to be written
2416 * @buf: the data to write
2417 * @oob_required: must write chip->oob_poi to OOB
2418 * @page: page number to write
2419 * @raw: use _raw version of write_page
2421 static int nand_write_page(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2422 uint32_t offset
, int data_len
, const uint8_t *buf
,
2423 int oob_required
, int page
, int raw
)
2425 int status
, subpage
;
2427 if (!(chip
->options
& NAND_NO_SUBPAGE_WRITE
) &&
2428 chip
->ecc
.write_subpage
)
2429 subpage
= offset
|| (data_len
< mtd
->writesize
);
2433 if (nand_standard_page_accessors(&chip
->ecc
))
2434 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, 0x00, page
);
2437 status
= chip
->ecc
.write_page_raw(mtd
, chip
, buf
,
2438 oob_required
, page
);
2440 status
= chip
->ecc
.write_subpage(mtd
, chip
, offset
, data_len
,
2441 buf
, oob_required
, page
);
2443 status
= chip
->ecc
.write_page(mtd
, chip
, buf
, oob_required
,
2449 if (nand_standard_page_accessors(&chip
->ecc
)) {
2450 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
2452 status
= chip
->waitfunc(mtd
, chip
);
2453 if (status
& NAND_STATUS_FAIL
)
2461 * nand_fill_oob - [INTERN] Transfer client buffer to oob
2462 * @mtd: MTD device structure
2463 * @oob: oob data buffer
2464 * @len: oob data write length
2465 * @ops: oob ops structure
2467 static uint8_t *nand_fill_oob(struct mtd_info
*mtd
, uint8_t *oob
, size_t len
,
2468 struct mtd_oob_ops
*ops
)
2470 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2473 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2474 * data from a previous OOB read.
2476 memset(chip
->oob_poi
, 0xff, mtd
->oobsize
);
2478 switch (ops
->mode
) {
2480 case MTD_OPS_PLACE_OOB
:
2482 memcpy(chip
->oob_poi
+ ops
->ooboffs
, oob
, len
);
2485 case MTD_OPS_AUTO_OOB
: {
2486 struct nand_oobfree
*free
= chip
->ecc
.layout
->oobfree
;
2487 uint32_t boffs
= 0, woffs
= ops
->ooboffs
;
2490 for (; free
->length
&& len
; free
++, len
-= bytes
) {
2491 /* Write request not from offset 0? */
2492 if (unlikely(woffs
)) {
2493 if (woffs
>= free
->length
) {
2494 woffs
-= free
->length
;
2497 boffs
= free
->offset
+ woffs
;
2498 bytes
= min_t(size_t, len
,
2499 (free
->length
- woffs
));
2502 bytes
= min_t(size_t, len
, free
->length
);
2503 boffs
= free
->offset
;
2505 memcpy(chip
->oob_poi
+ boffs
, oob
, bytes
);
2516 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
2519 * nand_do_write_ops - [INTERN] NAND write with ECC
2520 * @mtd: MTD device structure
2521 * @to: offset to write to
2522 * @ops: oob operations description structure
2524 * NAND write with ECC.
2526 static int nand_do_write_ops(struct mtd_info
*mtd
, loff_t to
,
2527 struct mtd_oob_ops
*ops
)
2529 int chipnr
, realpage
, page
, column
;
2530 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2531 uint32_t writelen
= ops
->len
;
2533 uint32_t oobwritelen
= ops
->ooblen
;
2534 uint32_t oobmaxlen
= mtd_oobavail(mtd
, ops
);
2536 uint8_t *oob
= ops
->oobbuf
;
2537 uint8_t *buf
= ops
->datbuf
;
2539 int oob_required
= oob
? 1 : 0;
2545 /* Reject writes, which are not page aligned */
2546 if (NOTALIGNED(to
)) {
2547 pr_notice("%s: attempt to write non page aligned data\n",
2552 column
= to
& (mtd
->writesize
- 1);
2554 chipnr
= (int)(to
>> chip
->chip_shift
);
2555 chip
->select_chip(mtd
, chipnr
);
2557 /* Check, if it is write protected */
2558 if (nand_check_wp(mtd
)) {
2563 realpage
= (int)(to
>> chip
->page_shift
);
2564 page
= realpage
& chip
->pagemask
;
2566 /* Invalidate the page cache, when we write to the cached page */
2567 if (to
<= ((loff_t
)chip
->pagebuf
<< chip
->page_shift
) &&
2568 ((loff_t
)chip
->pagebuf
<< chip
->page_shift
) < (to
+ ops
->len
))
2571 /* Don't allow multipage oob writes with offset */
2572 if (oob
&& ops
->ooboffs
&& (ops
->ooboffs
+ ops
->ooblen
> oobmaxlen
)) {
2578 int bytes
= mtd
->writesize
;
2579 uint8_t *wbuf
= buf
;
2581 int part_pagewr
= (column
|| writelen
< mtd
->writesize
);
2585 else if (chip
->options
& NAND_USE_BOUNCE_BUFFER
)
2586 use_bufpoi
= !IS_ALIGNED((unsigned long)buf
,
2592 /* Partial page write?, or need to use bounce buffer */
2594 pr_debug("%s: using write bounce buffer for buf@%p\n",
2597 bytes
= min_t(int, bytes
- column
, writelen
);
2599 memset(chip
->buffers
->databuf
, 0xff, mtd
->writesize
);
2600 memcpy(&chip
->buffers
->databuf
[column
], buf
, bytes
);
2601 wbuf
= chip
->buffers
->databuf
;
2604 if (unlikely(oob
)) {
2605 size_t len
= min(oobwritelen
, oobmaxlen
);
2606 oob
= nand_fill_oob(mtd
, oob
, len
, ops
);
2609 /* We still need to erase leftover OOB data */
2610 memset(chip
->oob_poi
, 0xff, mtd
->oobsize
);
2612 ret
= chip
->write_page(mtd
, chip
, column
, bytes
, wbuf
,
2614 (ops
->mode
== MTD_OPS_RAW
));
2626 page
= realpage
& chip
->pagemask
;
2627 /* Check, if we cross a chip boundary */
2630 chip
->select_chip(mtd
, -1);
2631 chip
->select_chip(mtd
, chipnr
);
2635 ops
->retlen
= ops
->len
- writelen
;
2637 ops
->oobretlen
= ops
->ooblen
;
2640 chip
->select_chip(mtd
, -1);
2645 * panic_nand_write - [MTD Interface] NAND write with ECC
2646 * @mtd: MTD device structure
2647 * @to: offset to write to
2648 * @len: number of bytes to write
2649 * @retlen: pointer to variable to store the number of written bytes
2650 * @buf: the data to write
2652 * NAND write with ECC. Used when performing writes in interrupt context, this
2653 * may for example be called by mtdoops when writing an oops while in panic.
2655 static int panic_nand_write(struct mtd_info
*mtd
, loff_t to
, size_t len
,
2656 size_t *retlen
, const uint8_t *buf
)
2658 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2659 struct mtd_oob_ops ops
;
2662 /* Wait for the device to get ready */
2663 panic_nand_wait(mtd
, chip
, 400);
2665 /* Grab the device */
2666 panic_nand_get_device(chip
, mtd
, FL_WRITING
);
2668 memset(&ops
, 0, sizeof(ops
));
2670 ops
.datbuf
= (uint8_t *)buf
;
2671 ops
.mode
= MTD_OPS_PLACE_OOB
;
2673 ret
= nand_do_write_ops(mtd
, to
, &ops
);
2675 *retlen
= ops
.retlen
;
2680 * nand_write - [MTD Interface] NAND write with ECC
2681 * @mtd: MTD device structure
2682 * @to: offset to write to
2683 * @len: number of bytes to write
2684 * @retlen: pointer to variable to store the number of written bytes
2685 * @buf: the data to write
2687 * NAND write with ECC.
2689 static int nand_write(struct mtd_info
*mtd
, loff_t to
, size_t len
,
2690 size_t *retlen
, const uint8_t *buf
)
2692 struct mtd_oob_ops ops
;
2695 nand_get_device(mtd
, FL_WRITING
);
2696 memset(&ops
, 0, sizeof(ops
));
2698 ops
.datbuf
= (uint8_t *)buf
;
2699 ops
.mode
= MTD_OPS_PLACE_OOB
;
2700 ret
= nand_do_write_ops(mtd
, to
, &ops
);
2701 *retlen
= ops
.retlen
;
2702 nand_release_device(mtd
);
2707 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2708 * @mtd: MTD device structure
2709 * @to: offset to write to
2710 * @ops: oob operation description structure
2712 * NAND write out-of-band.
2714 static int nand_do_write_oob(struct mtd_info
*mtd
, loff_t to
,
2715 struct mtd_oob_ops
*ops
)
2717 int chipnr
, page
, status
, len
;
2718 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2720 pr_debug("%s: to = 0x%08x, len = %i\n",
2721 __func__
, (unsigned int)to
, (int)ops
->ooblen
);
2723 len
= mtd_oobavail(mtd
, ops
);
2725 /* Do not allow write past end of page */
2726 if ((ops
->ooboffs
+ ops
->ooblen
) > len
) {
2727 pr_debug("%s: attempt to write past end of page\n",
2732 if (unlikely(ops
->ooboffs
>= len
)) {
2733 pr_debug("%s: attempt to start write outside oob\n",
2738 /* Do not allow write past end of device */
2739 if (unlikely(to
>= mtd
->size
||
2740 ops
->ooboffs
+ ops
->ooblen
>
2741 ((mtd
->size
>> chip
->page_shift
) -
2742 (to
>> chip
->page_shift
)) * len
)) {
2743 pr_debug("%s: attempt to write beyond end of device\n",
2748 chipnr
= (int)(to
>> chip
->chip_shift
);
2751 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2752 * of my DiskOnChip 2000 test units) will clear the whole data page too
2753 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2754 * it in the doc2000 driver in August 1999. dwmw2.
2756 nand_reset(chip
, chipnr
);
2758 chip
->select_chip(mtd
, chipnr
);
2760 /* Shift to get page */
2761 page
= (int)(to
>> chip
->page_shift
);
2763 /* Check, if it is write protected */
2764 if (nand_check_wp(mtd
)) {
2765 chip
->select_chip(mtd
, -1);
2769 /* Invalidate the page cache, if we write to the cached page */
2770 if (page
== chip
->pagebuf
)
2773 nand_fill_oob(mtd
, ops
->oobbuf
, ops
->ooblen
, ops
);
2775 if (ops
->mode
== MTD_OPS_RAW
)
2776 status
= chip
->ecc
.write_oob_raw(mtd
, chip
, page
& chip
->pagemask
);
2778 status
= chip
->ecc
.write_oob(mtd
, chip
, page
& chip
->pagemask
);
2780 chip
->select_chip(mtd
, -1);
2785 ops
->oobretlen
= ops
->ooblen
;
2791 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2792 * @mtd: MTD device structure
2793 * @to: offset to write to
2794 * @ops: oob operation description structure
2796 static int nand_write_oob(struct mtd_info
*mtd
, loff_t to
,
2797 struct mtd_oob_ops
*ops
)
2799 int ret
= -ENOTSUPP
;
2803 /* Do not allow writes past end of device */
2804 if (ops
->datbuf
&& (to
+ ops
->len
) > mtd
->size
) {
2805 pr_debug("%s: attempt to write beyond end of device\n",
2810 nand_get_device(mtd
, FL_WRITING
);
2812 switch (ops
->mode
) {
2813 case MTD_OPS_PLACE_OOB
:
2814 case MTD_OPS_AUTO_OOB
:
2823 ret
= nand_do_write_oob(mtd
, to
, ops
);
2825 ret
= nand_do_write_ops(mtd
, to
, ops
);
2828 nand_release_device(mtd
);
2833 * single_erase - [GENERIC] NAND standard block erase command function
2834 * @mtd: MTD device structure
2835 * @page: the page address of the block which will be erased
2837 * Standard erase command for NAND chips. Returns NAND status.
2839 static int single_erase(struct mtd_info
*mtd
, int page
)
2841 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2842 /* Send commands to erase a block */
2843 chip
->cmdfunc(mtd
, NAND_CMD_ERASE1
, -1, page
);
2844 chip
->cmdfunc(mtd
, NAND_CMD_ERASE2
, -1, -1);
2846 return chip
->waitfunc(mtd
, chip
);
2850 * nand_erase - [MTD Interface] erase block(s)
2851 * @mtd: MTD device structure
2852 * @instr: erase instruction
2854 * Erase one ore more blocks.
2856 static int nand_erase(struct mtd_info
*mtd
, struct erase_info
*instr
)
2858 return nand_erase_nand(mtd
, instr
, 0);
2862 * nand_erase_nand - [INTERN] erase block(s)
2863 * @mtd: MTD device structure
2864 * @instr: erase instruction
2865 * @allowbbt: allow erasing the bbt area
2867 * Erase one ore more blocks.
2869 int nand_erase_nand(struct mtd_info
*mtd
, struct erase_info
*instr
,
2872 int page
, status
, pages_per_block
, ret
, chipnr
;
2873 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2876 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2877 __func__
, (unsigned long long)instr
->addr
,
2878 (unsigned long long)instr
->len
);
2880 if (check_offs_len(mtd
, instr
->addr
, instr
->len
))
2883 /* Grab the lock and see if the device is available */
2884 nand_get_device(mtd
, FL_ERASING
);
2886 /* Shift to get first page */
2887 page
= (int)(instr
->addr
>> chip
->page_shift
);
2888 chipnr
= (int)(instr
->addr
>> chip
->chip_shift
);
2890 /* Calculate pages in each block */
2891 pages_per_block
= 1 << (chip
->phys_erase_shift
- chip
->page_shift
);
2893 /* Select the NAND device */
2894 chip
->select_chip(mtd
, chipnr
);
2896 /* Check, if it is write protected */
2897 if (nand_check_wp(mtd
)) {
2898 pr_debug("%s: device is write protected!\n",
2900 instr
->state
= MTD_ERASE_FAILED
;
2904 /* Loop through the pages */
2907 instr
->state
= MTD_ERASING
;
2912 /* Check if we have a bad block, we do not erase bad blocks! */
2913 if (!instr
->scrub
&& nand_block_checkbad(mtd
, ((loff_t
) page
) <<
2914 chip
->page_shift
, allowbbt
)) {
2915 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2917 instr
->state
= MTD_ERASE_FAILED
;
2922 * Invalidate the page cache, if we erase the block which
2923 * contains the current cached page.
2925 if (page
<= chip
->pagebuf
&& chip
->pagebuf
<
2926 (page
+ pages_per_block
))
2929 status
= chip
->erase(mtd
, page
& chip
->pagemask
);
2931 /* See if block erase succeeded */
2932 if (status
& NAND_STATUS_FAIL
) {
2933 pr_debug("%s: failed erase, page 0x%08x\n",
2935 instr
->state
= MTD_ERASE_FAILED
;
2937 ((loff_t
)page
<< chip
->page_shift
);
2941 /* Increment page address and decrement length */
2942 len
-= (1ULL << chip
->phys_erase_shift
);
2943 page
+= pages_per_block
;
2945 /* Check, if we cross a chip boundary */
2946 if (len
&& !(page
& chip
->pagemask
)) {
2948 chip
->select_chip(mtd
, -1);
2949 chip
->select_chip(mtd
, chipnr
);
2952 instr
->state
= MTD_ERASE_DONE
;
2956 ret
= instr
->state
== MTD_ERASE_DONE
? 0 : -EIO
;
2958 /* Deselect and wake up anyone waiting on the device */
2959 chip
->select_chip(mtd
, -1);
2960 nand_release_device(mtd
);
2962 /* Do call back function */
2964 mtd_erase_callback(instr
);
2966 /* Return more or less happy */
2971 * nand_sync - [MTD Interface] sync
2972 * @mtd: MTD device structure
2974 * Sync is actually a wait for chip ready function.
2976 static void nand_sync(struct mtd_info
*mtd
)
2978 pr_debug("%s: called\n", __func__
);
2980 /* Grab the lock and see if the device is available */
2981 nand_get_device(mtd
, FL_SYNCING
);
2982 /* Release it and go back */
2983 nand_release_device(mtd
);
2987 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2988 * @mtd: MTD device structure
2989 * @offs: offset relative to mtd start
2991 static int nand_block_isbad(struct mtd_info
*mtd
, loff_t offs
)
2993 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2994 int chipnr
= (int)(offs
>> chip
->chip_shift
);
2997 /* Select the NAND device */
2998 nand_get_device(mtd
, FL_READING
);
2999 chip
->select_chip(mtd
, chipnr
);
3001 ret
= nand_block_checkbad(mtd
, offs
, 0);
3003 chip
->select_chip(mtd
, -1);
3004 nand_release_device(mtd
);
3010 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
3011 * @mtd: MTD device structure
3012 * @ofs: offset relative to mtd start
3014 static int nand_block_markbad(struct mtd_info
*mtd
, loff_t ofs
)
3018 ret
= nand_block_isbad(mtd
, ofs
);
3020 /* If it was bad already, return success and do nothing */
3026 return nand_block_markbad_lowlevel(mtd
, ofs
);
3030 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
3031 * @mtd: MTD device structure
3032 * @chip: nand chip info structure
3033 * @addr: feature address.
3034 * @subfeature_param: the subfeature parameters, a four bytes array.
3036 static int nand_onfi_set_features(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3037 int addr
, uint8_t *subfeature_param
)
3042 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3043 if (!chip
->onfi_version
||
3044 !(le16_to_cpu(chip
->onfi_params
.opt_cmd
)
3045 & ONFI_OPT_CMD_SET_GET_FEATURES
))
3049 chip
->cmdfunc(mtd
, NAND_CMD_SET_FEATURES
, addr
, -1);
3050 for (i
= 0; i
< ONFI_SUBFEATURE_PARAM_LEN
; ++i
)
3051 chip
->write_byte(mtd
, subfeature_param
[i
]);
3053 status
= chip
->waitfunc(mtd
, chip
);
3054 if (status
& NAND_STATUS_FAIL
)
3060 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
3061 * @mtd: MTD device structure
3062 * @chip: nand chip info structure
3063 * @addr: feature address.
3064 * @subfeature_param: the subfeature parameters, a four bytes array.
3066 static int nand_onfi_get_features(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3067 int addr
, uint8_t *subfeature_param
)
3071 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3072 if (!chip
->onfi_version
||
3073 !(le16_to_cpu(chip
->onfi_params
.opt_cmd
)
3074 & ONFI_OPT_CMD_SET_GET_FEATURES
))
3078 chip
->cmdfunc(mtd
, NAND_CMD_GET_FEATURES
, addr
, -1);
3079 for (i
= 0; i
< ONFI_SUBFEATURE_PARAM_LEN
; ++i
)
3080 *subfeature_param
++ = chip
->read_byte(mtd
);
3084 /* Set default functions */
3085 static void nand_set_defaults(struct nand_chip
*chip
, int busw
)
3087 /* check for proper chip_delay setup, set 20us if not */
3088 if (!chip
->chip_delay
)
3089 chip
->chip_delay
= 20;
3091 /* check, if a user supplied command function given */
3092 if (chip
->cmdfunc
== NULL
)
3093 chip
->cmdfunc
= nand_command
;
3095 /* check, if a user supplied wait function given */
3096 if (chip
->waitfunc
== NULL
)
3097 chip
->waitfunc
= nand_wait
;
3099 if (!chip
->select_chip
)
3100 chip
->select_chip
= nand_select_chip
;
3102 /* set for ONFI nand */
3103 if (!chip
->onfi_set_features
)
3104 chip
->onfi_set_features
= nand_onfi_set_features
;
3105 if (!chip
->onfi_get_features
)
3106 chip
->onfi_get_features
= nand_onfi_get_features
;
3108 /* If called twice, pointers that depend on busw may need to be reset */
3109 if (!chip
->read_byte
|| chip
->read_byte
== nand_read_byte
)
3110 chip
->read_byte
= busw
? nand_read_byte16
: nand_read_byte
;
3111 if (!chip
->read_word
)
3112 chip
->read_word
= nand_read_word
;
3113 if (!chip
->block_bad
)
3114 chip
->block_bad
= nand_block_bad
;
3115 if (!chip
->block_markbad
)
3116 chip
->block_markbad
= nand_default_block_markbad
;
3117 if (!chip
->write_buf
|| chip
->write_buf
== nand_write_buf
)
3118 chip
->write_buf
= busw
? nand_write_buf16
: nand_write_buf
;
3119 if (!chip
->write_byte
|| chip
->write_byte
== nand_write_byte
)
3120 chip
->write_byte
= busw
? nand_write_byte16
: nand_write_byte
;
3121 if (!chip
->read_buf
|| chip
->read_buf
== nand_read_buf
)
3122 chip
->read_buf
= busw
? nand_read_buf16
: nand_read_buf
;
3123 if (!chip
->scan_bbt
)
3124 chip
->scan_bbt
= nand_default_bbt
;
3126 if (!chip
->controller
) {
3127 chip
->controller
= &chip
->hwcontrol
;
3128 spin_lock_init(&chip
->controller
->lock
);
3129 init_waitqueue_head(&chip
->controller
->wq
);
3132 if (!chip
->buf_align
)
3133 chip
->buf_align
= 1;
3136 /* Sanitize ONFI strings so we can safely print them */
3137 static void sanitize_string(char *s
, size_t len
)
3141 /* Null terminate */
3144 /* Remove non printable chars */
3145 for (i
= 0; i
< len
- 1; i
++) {
3146 if (s
[i
] < ' ' || s
[i
] > 127)
3150 /* Remove trailing spaces */
3154 static u16
onfi_crc16(u16 crc
, u8
const *p
, size_t len
)
3159 for (i
= 0; i
< 8; i
++)
3160 crc
= (crc
<< 1) ^ ((crc
& 0x8000) ? 0x8005 : 0);
3166 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3167 /* Parse the Extended Parameter Page. */
3168 static int nand_flash_detect_ext_param_page(struct mtd_info
*mtd
,
3169 struct nand_chip
*chip
, struct nand_onfi_params
*p
)
3171 struct onfi_ext_param_page
*ep
;
3172 struct onfi_ext_section
*s
;
3173 struct onfi_ext_ecc_info
*ecc
;
3179 len
= le16_to_cpu(p
->ext_param_page_length
) * 16;
3180 ep
= kmalloc(len
, GFP_KERNEL
);
3184 /* Send our own NAND_CMD_PARAM. */
3185 chip
->cmdfunc(mtd
, NAND_CMD_PARAM
, 0, -1);
3187 /* Use the Change Read Column command to skip the ONFI param pages. */
3188 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
,
3189 sizeof(*p
) * p
->num_of_param_pages
, -1);
3191 /* Read out the Extended Parameter Page. */
3192 chip
->read_buf(mtd
, (uint8_t *)ep
, len
);
3193 if ((onfi_crc16(ONFI_CRC_BASE
, ((uint8_t *)ep
) + 2, len
- 2)
3194 != le16_to_cpu(ep
->crc
))) {
3195 pr_debug("fail in the CRC.\n");
3200 * Check the signature.
3201 * Do not strictly follow the ONFI spec, maybe changed in future.
3203 if (strncmp((char *)ep
->sig
, "EPPS", 4)) {
3204 pr_debug("The signature is invalid.\n");
3208 /* find the ECC section. */
3209 cursor
= (uint8_t *)(ep
+ 1);
3210 for (i
= 0; i
< ONFI_EXT_SECTION_MAX
; i
++) {
3211 s
= ep
->sections
+ i
;
3212 if (s
->type
== ONFI_SECTION_TYPE_2
)
3214 cursor
+= s
->length
* 16;
3216 if (i
== ONFI_EXT_SECTION_MAX
) {
3217 pr_debug("We can not find the ECC section.\n");
3221 /* get the info we want. */
3222 ecc
= (struct onfi_ext_ecc_info
*)cursor
;
3224 if (!ecc
->codeword_size
) {
3225 pr_debug("Invalid codeword size\n");
3229 chip
->ecc_strength_ds
= ecc
->ecc_bits
;
3230 chip
->ecc_step_ds
= 1 << ecc
->codeword_size
;
3238 static int nand_setup_read_retry_micron(struct mtd_info
*mtd
, int retry_mode
)
3240 struct nand_chip
*chip
= mtd_to_nand(mtd
);
3241 uint8_t feature
[ONFI_SUBFEATURE_PARAM_LEN
] = {retry_mode
};
3243 return chip
->onfi_set_features(mtd
, chip
, ONFI_FEATURE_ADDR_READ_RETRY
,
3248 * Configure chip properties from Micron vendor-specific ONFI table
3250 static void nand_onfi_detect_micron(struct nand_chip
*chip
,
3251 struct nand_onfi_params
*p
)
3253 struct nand_onfi_vendor_micron
*micron
= (void *)p
->vendor
;
3255 if (le16_to_cpu(p
->vendor_revision
) < 1)
3258 chip
->read_retries
= micron
->read_retry_options
;
3259 chip
->setup_read_retry
= nand_setup_read_retry_micron
;
3263 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
3265 static int nand_flash_detect_onfi(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3268 struct nand_onfi_params
*p
= &chip
->onfi_params
;
3272 /* Try ONFI for unknown chip or LP */
3273 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x20, -1);
3274 if (chip
->read_byte(mtd
) != 'O' || chip
->read_byte(mtd
) != 'N' ||
3275 chip
->read_byte(mtd
) != 'F' || chip
->read_byte(mtd
) != 'I')
3278 chip
->cmdfunc(mtd
, NAND_CMD_PARAM
, 0, -1);
3279 for (i
= 0; i
< 3; i
++) {
3280 for (j
= 0; j
< sizeof(*p
); j
++)
3281 ((uint8_t *)p
)[j
] = chip
->read_byte(mtd
);
3282 if (onfi_crc16(ONFI_CRC_BASE
, (uint8_t *)p
, 254) ==
3283 le16_to_cpu(p
->crc
)) {
3289 pr_err("Could not find valid ONFI parameter page; aborting\n");
3294 val
= le16_to_cpu(p
->revision
);
3296 chip
->onfi_version
= 23;
3297 else if (val
& (1 << 4))
3298 chip
->onfi_version
= 22;
3299 else if (val
& (1 << 3))
3300 chip
->onfi_version
= 21;
3301 else if (val
& (1 << 2))
3302 chip
->onfi_version
= 20;
3303 else if (val
& (1 << 1))
3304 chip
->onfi_version
= 10;
3306 if (!chip
->onfi_version
) {
3307 pr_info("unsupported ONFI version: %d\n", val
);
3311 sanitize_string(p
->manufacturer
, sizeof(p
->manufacturer
));
3312 sanitize_string(p
->model
, sizeof(p
->model
));
3314 mtd
->name
= p
->model
;
3316 mtd
->writesize
= le32_to_cpu(p
->byte_per_page
);
3319 * pages_per_block and blocks_per_lun may not be a power-of-2 size
3320 * (don't ask me who thought of this...). MTD assumes that these
3321 * dimensions will be power-of-2, so just truncate the remaining area.
3323 mtd
->erasesize
= 1 << (fls(le32_to_cpu(p
->pages_per_block
)) - 1);
3324 mtd
->erasesize
*= mtd
->writesize
;
3326 mtd
->oobsize
= le16_to_cpu(p
->spare_bytes_per_page
);
3328 /* See erasesize comment */
3329 chip
->chipsize
= 1 << (fls(le32_to_cpu(p
->blocks_per_lun
)) - 1);
3330 chip
->chipsize
*= (uint64_t)mtd
->erasesize
* p
->lun_count
;
3331 chip
->bits_per_cell
= p
->bits_per_cell
;
3333 if (onfi_feature(chip
) & ONFI_FEATURE_16_BIT_BUS
)
3334 *busw
= NAND_BUSWIDTH_16
;
3338 if (p
->ecc_bits
!= 0xff) {
3339 chip
->ecc_strength_ds
= p
->ecc_bits
;
3340 chip
->ecc_step_ds
= 512;
3341 } else if (chip
->onfi_version
>= 21 &&
3342 (onfi_feature(chip
) & ONFI_FEATURE_EXT_PARAM_PAGE
)) {
3345 * The nand_flash_detect_ext_param_page() uses the
3346 * Change Read Column command which maybe not supported
3347 * by the chip->cmdfunc. So try to update the chip->cmdfunc
3348 * now. We do not replace user supplied command function.
3350 if (mtd
->writesize
> 512 && chip
->cmdfunc
== nand_command
)
3351 chip
->cmdfunc
= nand_command_lp
;
3353 /* The Extended Parameter Page is supported since ONFI 2.1. */
3354 if (nand_flash_detect_ext_param_page(mtd
, chip
, p
))
3355 pr_warn("Failed to detect ONFI extended param page\n");
3357 pr_warn("Could not retrieve ONFI ECC requirements\n");
3360 if (p
->jedec_id
== NAND_MFR_MICRON
)
3361 nand_onfi_detect_micron(chip
, p
);
3366 static int nand_flash_detect_onfi(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3374 * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise.
3376 static int nand_flash_detect_jedec(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3379 struct nand_jedec_params
*p
= &chip
->jedec_params
;
3380 struct jedec_ecc_info
*ecc
;
3384 /* Try JEDEC for unknown chip or LP */
3385 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x40, -1);
3386 if (chip
->read_byte(mtd
) != 'J' || chip
->read_byte(mtd
) != 'E' ||
3387 chip
->read_byte(mtd
) != 'D' || chip
->read_byte(mtd
) != 'E' ||
3388 chip
->read_byte(mtd
) != 'C')
3391 chip
->cmdfunc(mtd
, NAND_CMD_PARAM
, 0x40, -1);
3392 for (i
= 0; i
< 3; i
++) {
3393 for (j
= 0; j
< sizeof(*p
); j
++)
3394 ((uint8_t *)p
)[j
] = chip
->read_byte(mtd
);
3396 if (onfi_crc16(ONFI_CRC_BASE
, (uint8_t *)p
, 510) ==
3397 le16_to_cpu(p
->crc
))
3402 pr_err("Could not find valid JEDEC parameter page; aborting\n");
3407 val
= le16_to_cpu(p
->revision
);
3409 chip
->jedec_version
= 10;
3410 else if (val
& (1 << 1))
3411 chip
->jedec_version
= 1; /* vendor specific version */
3413 if (!chip
->jedec_version
) {
3414 pr_info("unsupported JEDEC version: %d\n", val
);
3418 sanitize_string(p
->manufacturer
, sizeof(p
->manufacturer
));
3419 sanitize_string(p
->model
, sizeof(p
->model
));
3421 mtd
->name
= p
->model
;
3423 mtd
->writesize
= le32_to_cpu(p
->byte_per_page
);
3425 /* Please reference to the comment for nand_flash_detect_onfi. */
3426 mtd
->erasesize
= 1 << (fls(le32_to_cpu(p
->pages_per_block
)) - 1);
3427 mtd
->erasesize
*= mtd
->writesize
;
3429 mtd
->oobsize
= le16_to_cpu(p
->spare_bytes_per_page
);
3431 /* Please reference to the comment for nand_flash_detect_onfi. */
3432 chip
->chipsize
= 1 << (fls(le32_to_cpu(p
->blocks_per_lun
)) - 1);
3433 chip
->chipsize
*= (uint64_t)mtd
->erasesize
* p
->lun_count
;
3434 chip
->bits_per_cell
= p
->bits_per_cell
;
3436 if (jedec_feature(chip
) & JEDEC_FEATURE_16_BIT_BUS
)
3437 *busw
= NAND_BUSWIDTH_16
;
3442 ecc
= &p
->ecc_info
[0];
3444 if (ecc
->codeword_size
>= 9) {
3445 chip
->ecc_strength_ds
= ecc
->ecc_bits
;
3446 chip
->ecc_step_ds
= 1 << ecc
->codeword_size
;
3448 pr_warn("Invalid codeword size\n");
3455 * nand_id_has_period - Check if an ID string has a given wraparound period
3456 * @id_data: the ID string
3457 * @arrlen: the length of the @id_data array
3458 * @period: the period of repitition
3460 * Check if an ID string is repeated within a given sequence of bytes at
3461 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
3462 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
3463 * if the repetition has a period of @period; otherwise, returns zero.
3465 static int nand_id_has_period(u8
*id_data
, int arrlen
, int period
)
3468 for (i
= 0; i
< period
; i
++)
3469 for (j
= i
+ period
; j
< arrlen
; j
+= period
)
3470 if (id_data
[i
] != id_data
[j
])
3476 * nand_id_len - Get the length of an ID string returned by CMD_READID
3477 * @id_data: the ID string
3478 * @arrlen: the length of the @id_data array
3480 * Returns the length of the ID string, according to known wraparound/trailing
3481 * zero patterns. If no pattern exists, returns the length of the array.
3483 static int nand_id_len(u8
*id_data
, int arrlen
)
3485 int last_nonzero
, period
;
3487 /* Find last non-zero byte */
3488 for (last_nonzero
= arrlen
- 1; last_nonzero
>= 0; last_nonzero
--)
3489 if (id_data
[last_nonzero
])
3493 if (last_nonzero
< 0)
3496 /* Calculate wraparound period */
3497 for (period
= 1; period
< arrlen
; period
++)
3498 if (nand_id_has_period(id_data
, arrlen
, period
))
3501 /* There's a repeated pattern */
3502 if (period
< arrlen
)
3505 /* There are trailing zeros */
3506 if (last_nonzero
< arrlen
- 1)
3507 return last_nonzero
+ 1;
3509 /* No pattern detected */
3513 /* Extract the bits of per cell from the 3rd byte of the extended ID */
3514 static int nand_get_bits_per_cell(u8 cellinfo
)
3518 bits
= cellinfo
& NAND_CI_CELLTYPE_MSK
;
3519 bits
>>= NAND_CI_CELLTYPE_SHIFT
;
3524 * Many new NAND share similar device ID codes, which represent the size of the
3525 * chip. The rest of the parameters must be decoded according to generic or
3526 * manufacturer-specific "extended ID" decoding patterns.
3528 static void nand_decode_ext_id(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3529 u8 id_data
[8], int *busw
)
3532 /* The 3rd id byte holds MLC / multichip data */
3533 chip
->bits_per_cell
= nand_get_bits_per_cell(id_data
[2]);
3534 /* The 4th id byte is the important one */
3537 id_len
= nand_id_len(id_data
, 8);
3540 * Field definitions are in the following datasheets:
3541 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
3542 * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
3543 * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
3545 * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
3546 * ID to decide what to do.
3548 if (id_len
== 6 && id_data
[0] == NAND_MFR_SAMSUNG
&&
3549 !nand_is_slc(chip
) && id_data
[5] != 0x00) {
3551 mtd
->writesize
= 2048 << (extid
& 0x03);
3554 switch (((extid
>> 2) & 0x04) | (extid
& 0x03)) {
3574 default: /* Other cases are "reserved" (unknown) */
3575 mtd
->oobsize
= 1024;
3579 /* Calc blocksize */
3580 mtd
->erasesize
= (128 * 1024) <<
3581 (((extid
>> 1) & 0x04) | (extid
& 0x03));
3583 } else if (id_len
== 6 && id_data
[0] == NAND_MFR_HYNIX
&&
3584 !nand_is_slc(chip
)) {
3588 mtd
->writesize
= 2048 << (extid
& 0x03);
3591 switch (((extid
>> 2) & 0x04) | (extid
& 0x03)) {
3615 /* Calc blocksize */
3616 tmp
= ((extid
>> 1) & 0x04) | (extid
& 0x03);
3618 mtd
->erasesize
= (128 * 1024) << tmp
;
3619 else if (tmp
== 0x03)
3620 mtd
->erasesize
= 768 * 1024;
3622 mtd
->erasesize
= (64 * 1024) << tmp
;
3626 mtd
->writesize
= 1024 << (extid
& 0x03);
3629 mtd
->oobsize
= (8 << (extid
& 0x01)) *
3630 (mtd
->writesize
>> 9);
3632 /* Calc blocksize. Blocksize is multiples of 64KiB */
3633 mtd
->erasesize
= (64 * 1024) << (extid
& 0x03);
3635 /* Get buswidth information */
3636 *busw
= (extid
& 0x01) ? NAND_BUSWIDTH_16
: 0;
3639 * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
3640 * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
3642 * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
3644 * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC
3646 if (id_len
>= 6 && id_data
[0] == NAND_MFR_TOSHIBA
&&
3647 nand_is_slc(chip
) &&
3648 (id_data
[5] & 0x7) == 0x6 /* 24nm */ &&
3649 !(id_data
[4] & 0x80) /* !BENAND */) {
3650 mtd
->oobsize
= 32 * mtd
->writesize
>> 9;
3657 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3658 * decodes a matching ID table entry and assigns the MTD size parameters for
3661 static void nand_decode_id(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3662 struct nand_flash_dev
*type
, u8 id_data
[8],
3665 int maf_id
= id_data
[0];
3667 mtd
->erasesize
= type
->erasesize
;
3668 mtd
->writesize
= type
->pagesize
;
3669 mtd
->oobsize
= mtd
->writesize
/ 32;
3670 *busw
= type
->options
& NAND_BUSWIDTH_16
;
3672 /* All legacy ID NAND are small-page, SLC */
3673 chip
->bits_per_cell
= 1;
3676 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3677 * some Spansion chips have erasesize that conflicts with size
3678 * listed in nand_ids table.
3679 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3681 if (maf_id
== NAND_MFR_AMD
&& id_data
[4] != 0x00 && id_data
[5] == 0x00
3682 && id_data
[6] == 0x00 && id_data
[7] == 0x00
3683 && mtd
->writesize
== 512) {
3684 mtd
->erasesize
= 128 * 1024;
3685 mtd
->erasesize
<<= ((id_data
[3] & 0x03) << 1);
3690 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3691 * heuristic patterns using various detected parameters (e.g., manufacturer,
3692 * page size, cell-type information).
3694 static void nand_decode_bbm_options(struct mtd_info
*mtd
,
3695 struct nand_chip
*chip
, u8 id_data
[8])
3697 int maf_id
= id_data
[0];
3699 /* Set the bad block position */
3700 if (mtd
->writesize
> 512 || (chip
->options
& NAND_BUSWIDTH_16
))
3701 chip
->badblockpos
= NAND_LARGE_BADBLOCK_POS
;
3703 chip
->badblockpos
= NAND_SMALL_BADBLOCK_POS
;
3706 * Bad block marker is stored in the last page of each block on Samsung
3707 * and Hynix MLC devices; stored in first two pages of each block on
3708 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3709 * AMD/Spansion, and Macronix. All others scan only the first page.
3711 if (!nand_is_slc(chip
) &&
3712 (maf_id
== NAND_MFR_SAMSUNG
||
3713 maf_id
== NAND_MFR_HYNIX
))
3714 chip
->bbt_options
|= NAND_BBT_SCANLASTPAGE
;
3715 else if ((nand_is_slc(chip
) &&
3716 (maf_id
== NAND_MFR_SAMSUNG
||
3717 maf_id
== NAND_MFR_HYNIX
||
3718 maf_id
== NAND_MFR_TOSHIBA
||
3719 maf_id
== NAND_MFR_AMD
||
3720 maf_id
== NAND_MFR_MACRONIX
)) ||
3721 (mtd
->writesize
== 2048 &&
3722 maf_id
== NAND_MFR_MICRON
))
3723 chip
->bbt_options
|= NAND_BBT_SCAN2NDPAGE
;
3726 static inline bool is_full_id_nand(struct nand_flash_dev
*type
)
3728 return type
->id_len
;
3731 static bool find_full_id_nand(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3732 struct nand_flash_dev
*type
, u8
*id_data
, int *busw
)
3734 if (!strncmp((char *)type
->id
, (char *)id_data
, type
->id_len
)) {
3735 mtd
->writesize
= type
->pagesize
;
3736 mtd
->erasesize
= type
->erasesize
;
3737 mtd
->oobsize
= type
->oobsize
;
3739 chip
->bits_per_cell
= nand_get_bits_per_cell(id_data
[2]);
3740 chip
->chipsize
= (uint64_t)type
->chipsize
<< 20;
3741 chip
->options
|= type
->options
;
3742 chip
->ecc_strength_ds
= NAND_ECC_STRENGTH(type
);
3743 chip
->ecc_step_ds
= NAND_ECC_STEP(type
);
3744 chip
->onfi_timing_mode_default
=
3745 type
->onfi_timing_mode_default
;
3747 *busw
= type
->options
& NAND_BUSWIDTH_16
;
3750 mtd
->name
= type
->name
;
3758 * Get the flash and manufacturer id and lookup if the type is supported.
3760 static struct nand_flash_dev
*nand_get_flash_type(struct mtd_info
*mtd
,
3761 struct nand_chip
*chip
,
3762 int *maf_id
, int *dev_id
,
3763 struct nand_flash_dev
*type
)
3770 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
3773 nand_reset(chip
, 0);
3775 /* Select the device */
3776 chip
->select_chip(mtd
, 0);
3778 /* Send the command for reading device ID */
3779 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
3781 /* Read manufacturer and device IDs */
3782 *maf_id
= chip
->read_byte(mtd
);
3783 *dev_id
= chip
->read_byte(mtd
);
3786 * Try again to make sure, as some systems the bus-hold or other
3787 * interface concerns can cause random data which looks like a
3788 * possibly credible NAND flash to appear. If the two results do
3789 * not match, ignore the device completely.
3792 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
3794 /* Read entire ID string */
3795 for (i
= 0; i
< 8; i
++)
3796 id_data
[i
] = chip
->read_byte(mtd
);
3798 if (id_data
[0] != *maf_id
|| id_data
[1] != *dev_id
) {
3799 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
3800 *maf_id
, *dev_id
, id_data
[0], id_data
[1]);
3801 return ERR_PTR(-ENODEV
);
3805 type
= nand_flash_ids
;
3807 for (; type
->name
!= NULL
; type
++) {
3808 if (is_full_id_nand(type
)) {
3809 if (find_full_id_nand(mtd
, chip
, type
, id_data
, &busw
))
3811 } else if (*dev_id
== type
->dev_id
) {
3816 chip
->onfi_version
= 0;
3817 if (!type
->name
|| !type
->pagesize
) {
3818 /* Check if the chip is ONFI compliant */
3819 if (nand_flash_detect_onfi(mtd
, chip
, &busw
))
3822 /* Check if the chip is JEDEC compliant */
3823 if (nand_flash_detect_jedec(mtd
, chip
, &busw
))
3828 return ERR_PTR(-ENODEV
);
3831 mtd
->name
= type
->name
;
3833 chip
->chipsize
= (uint64_t)type
->chipsize
<< 20;
3835 if (!type
->pagesize
) {
3836 /* Decode parameters from extended ID */
3837 nand_decode_ext_id(mtd
, chip
, id_data
, &busw
);
3839 nand_decode_id(mtd
, chip
, type
, id_data
, &busw
);
3841 /* Get chip options */
3842 chip
->options
|= type
->options
;
3845 * Check if chip is not a Samsung device. Do not clear the
3846 * options for chips which do not have an extended id.
3848 if (*maf_id
!= NAND_MFR_SAMSUNG
&& !type
->pagesize
)
3849 chip
->options
&= ~NAND_SAMSUNG_LP_OPTIONS
;
3852 /* Try to identify manufacturer */
3853 for (maf_idx
= 0; nand_manuf_ids
[maf_idx
].id
!= 0x0; maf_idx
++) {
3854 if (nand_manuf_ids
[maf_idx
].id
== *maf_id
)
3858 if (chip
->options
& NAND_BUSWIDTH_AUTO
) {
3859 WARN_ON(chip
->options
& NAND_BUSWIDTH_16
);
3860 chip
->options
|= busw
;
3861 nand_set_defaults(chip
, busw
);
3862 } else if (busw
!= (chip
->options
& NAND_BUSWIDTH_16
)) {
3864 * Check, if buswidth is correct. Hardware drivers should set
3867 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3869 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
, mtd
->name
);
3870 pr_warn("bus width %d instead %d bit\n",
3871 (chip
->options
& NAND_BUSWIDTH_16
) ? 16 : 8,
3873 return ERR_PTR(-EINVAL
);
3876 nand_decode_bbm_options(mtd
, chip
, id_data
);
3878 /* Calculate the address shift from the page size */
3879 chip
->page_shift
= ffs(mtd
->writesize
) - 1;
3880 /* Convert chipsize to number of pages per chip -1 */
3881 chip
->pagemask
= (chip
->chipsize
>> chip
->page_shift
) - 1;
3883 chip
->bbt_erase_shift
= chip
->phys_erase_shift
=
3884 ffs(mtd
->erasesize
) - 1;
3885 if (chip
->chipsize
& 0xffffffff)
3886 chip
->chip_shift
= ffs((unsigned)chip
->chipsize
) - 1;
3888 chip
->chip_shift
= ffs((unsigned)(chip
->chipsize
>> 32));
3889 chip
->chip_shift
+= 32 - 1;
3892 chip
->badblockbits
= 8;
3893 chip
->erase
= single_erase
;
3895 /* Do not replace user supplied command function! */
3896 if (mtd
->writesize
> 512 && chip
->cmdfunc
== nand_command
)
3897 chip
->cmdfunc
= nand_command_lp
;
3899 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3902 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3903 if (chip
->onfi_version
)
3904 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
,
3905 chip
->onfi_params
.model
);
3906 else if (chip
->jedec_version
)
3907 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
,
3908 chip
->jedec_params
.model
);
3910 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
,
3913 if (chip
->jedec_version
)
3914 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
,
3915 chip
->jedec_params
.model
);
3917 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
,
3920 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
,
3924 pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n",
3925 (int)(chip
->chipsize
>> 20), nand_is_slc(chip
) ? "SLC" : "MLC",
3926 mtd
->erasesize
>> 10, mtd
->writesize
, mtd
->oobsize
);
3930 #if CONFIG_IS_ENABLED(OF_CONTROL)
3931 DECLARE_GLOBAL_DATA_PTR
;
3933 static int nand_dt_init(struct mtd_info
*mtd
, struct nand_chip
*chip
, int node
)
3935 int ret
, ecc_mode
= -1, ecc_strength
, ecc_step
;
3936 const void *blob
= gd
->fdt_blob
;
3939 ret
= fdtdec_get_int(blob
, node
, "nand-bus-width", -1);
3941 chip
->options
|= NAND_BUSWIDTH_16
;
3943 if (fdtdec_get_bool(blob
, node
, "nand-on-flash-bbt"))
3944 chip
->bbt_options
|= NAND_BBT_USE_FLASH
;
3946 str
= fdt_getprop(blob
, node
, "nand-ecc-mode", NULL
);
3948 if (!strcmp(str
, "none"))
3949 ecc_mode
= NAND_ECC_NONE
;
3950 else if (!strcmp(str
, "soft"))
3951 ecc_mode
= NAND_ECC_SOFT
;
3952 else if (!strcmp(str
, "hw"))
3953 ecc_mode
= NAND_ECC_HW
;
3954 else if (!strcmp(str
, "hw_syndrome"))
3955 ecc_mode
= NAND_ECC_HW_SYNDROME
;
3956 else if (!strcmp(str
, "hw_oob_first"))
3957 ecc_mode
= NAND_ECC_HW_OOB_FIRST
;
3958 else if (!strcmp(str
, "soft_bch"))
3959 ecc_mode
= NAND_ECC_SOFT_BCH
;
3963 ecc_strength
= fdtdec_get_int(blob
, node
, "nand-ecc-strength", -1);
3964 ecc_step
= fdtdec_get_int(blob
, node
, "nand-ecc-step-size", -1);
3966 if ((ecc_step
>= 0 && !(ecc_strength
>= 0)) ||
3967 (!(ecc_step
>= 0) && ecc_strength
>= 0)) {
3968 pr_err("must set both strength and step size in DT\n");
3973 chip
->ecc
.mode
= ecc_mode
;
3975 if (ecc_strength
>= 0)
3976 chip
->ecc
.strength
= ecc_strength
;
3979 chip
->ecc
.size
= ecc_step
;
3981 if (fdt_getprop(blob
, node
, "nand-ecc-maximize", NULL
))
3982 chip
->ecc
.options
|= NAND_ECC_MAXIMIZE
;
3987 static int nand_dt_init(struct mtd_info
*mtd
, struct nand_chip
*chip
, int node
)
3991 #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
3994 * nand_scan_ident - [NAND Interface] Scan for the NAND device
3995 * @mtd: MTD device structure
3996 * @maxchips: number of chips to scan for
3997 * @table: alternative NAND ID table
3999 * This is the first phase of the normal nand_scan() function. It reads the
4000 * flash ID and sets up MTD fields accordingly.
4003 int nand_scan_ident(struct mtd_info
*mtd
, int maxchips
,
4004 struct nand_flash_dev
*table
)
4006 int i
, nand_maf_id
, nand_dev_id
;
4007 struct nand_chip
*chip
= mtd_to_nand(mtd
);
4008 struct nand_flash_dev
*type
;
4011 if (chip
->flash_node
) {
4012 ret
= nand_dt_init(mtd
, chip
, chip
->flash_node
);
4017 /* Set the default functions */
4018 nand_set_defaults(chip
, chip
->options
& NAND_BUSWIDTH_16
);
4020 /* Read the flash type */
4021 type
= nand_get_flash_type(mtd
, chip
, &nand_maf_id
,
4022 &nand_dev_id
, table
);
4025 if (!(chip
->options
& NAND_SCAN_SILENT_NODEV
))
4026 pr_warn("No NAND device found\n");
4027 chip
->select_chip(mtd
, -1);
4028 return PTR_ERR(type
);
4031 /* Initialize the ->data_interface field. */
4032 ret
= nand_init_data_interface(chip
);
4037 * Setup the data interface correctly on the chip and controller side.
4038 * This explicit call to nand_setup_data_interface() is only required
4039 * for the first die, because nand_reset() has been called before
4040 * ->data_interface and ->default_onfi_timing_mode were set.
4041 * For the other dies, nand_reset() will automatically switch to the
4044 ret
= nand_setup_data_interface(chip
, 0);
4048 chip
->select_chip(mtd
, -1);
4050 /* Check for a chip array */
4051 for (i
= 1; i
< maxchips
; i
++) {
4052 /* See comment in nand_get_flash_type for reset */
4053 nand_reset(chip
, i
);
4055 chip
->select_chip(mtd
, i
);
4056 /* Send the command for reading device ID */
4057 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
4058 /* Read manufacturer and device IDs */
4059 if (nand_maf_id
!= chip
->read_byte(mtd
) ||
4060 nand_dev_id
!= chip
->read_byte(mtd
)) {
4061 chip
->select_chip(mtd
, -1);
4064 chip
->select_chip(mtd
, -1);
4069 pr_info("%d chips detected\n", i
);
4072 /* Store the number of chips and calc total size for mtd */
4074 mtd
->size
= i
* chip
->chipsize
;
4078 EXPORT_SYMBOL(nand_scan_ident
);
4081 * nand_check_ecc_caps - check the sanity of preset ECC settings
4082 * @chip: nand chip info structure
4083 * @caps: ECC caps info structure
4084 * @oobavail: OOB size that the ECC engine can use
4086 * When ECC step size and strength are already set, check if they are supported
4087 * by the controller and the calculated ECC bytes fit within the chip's OOB.
4088 * On success, the calculated ECC bytes is set.
4090 int nand_check_ecc_caps(struct nand_chip
*chip
,
4091 const struct nand_ecc_caps
*caps
, int oobavail
)
4093 struct mtd_info
*mtd
= nand_to_mtd(chip
);
4094 const struct nand_ecc_step_info
*stepinfo
;
4095 int preset_step
= chip
->ecc
.size
;
4096 int preset_strength
= chip
->ecc
.strength
;
4097 int nsteps
, ecc_bytes
;
4100 if (WARN_ON(oobavail
< 0))
4103 if (!preset_step
|| !preset_strength
)
4106 nsteps
= mtd
->writesize
/ preset_step
;
4108 for (i
= 0; i
< caps
->nstepinfos
; i
++) {
4109 stepinfo
= &caps
->stepinfos
[i
];
4111 if (stepinfo
->stepsize
!= preset_step
)
4114 for (j
= 0; j
< stepinfo
->nstrengths
; j
++) {
4115 if (stepinfo
->strengths
[j
] != preset_strength
)
4118 ecc_bytes
= caps
->calc_ecc_bytes(preset_step
,
4120 if (WARN_ON_ONCE(ecc_bytes
< 0))
4123 if (ecc_bytes
* nsteps
> oobavail
) {
4124 pr_err("ECC (step, strength) = (%d, %d) does not fit in OOB",
4125 preset_step
, preset_strength
);
4129 chip
->ecc
.bytes
= ecc_bytes
;
4135 pr_err("ECC (step, strength) = (%d, %d) not supported on this controller",
4136 preset_step
, preset_strength
);
4140 EXPORT_SYMBOL_GPL(nand_check_ecc_caps
);
4143 * nand_match_ecc_req - meet the chip's requirement with least ECC bytes
4144 * @chip: nand chip info structure
4145 * @caps: ECC engine caps info structure
4146 * @oobavail: OOB size that the ECC engine can use
4148 * If a chip's ECC requirement is provided, try to meet it with the least
4149 * number of ECC bytes (i.e. with the largest number of OOB-free bytes).
4150 * On success, the chosen ECC settings are set.
4152 int nand_match_ecc_req(struct nand_chip
*chip
,
4153 const struct nand_ecc_caps
*caps
, int oobavail
)
4155 struct mtd_info
*mtd
= nand_to_mtd(chip
);
4156 const struct nand_ecc_step_info
*stepinfo
;
4157 int req_step
= chip
->ecc_step_ds
;
4158 int req_strength
= chip
->ecc_strength_ds
;
4159 int req_corr
, step_size
, strength
, nsteps
, ecc_bytes
, ecc_bytes_total
;
4160 int best_step
, best_strength
, best_ecc_bytes
;
4161 int best_ecc_bytes_total
= INT_MAX
;
4164 if (WARN_ON(oobavail
< 0))
4167 /* No information provided by the NAND chip */
4168 if (!req_step
|| !req_strength
)
4171 /* number of correctable bits the chip requires in a page */
4172 req_corr
= mtd
->writesize
/ req_step
* req_strength
;
4174 for (i
= 0; i
< caps
->nstepinfos
; i
++) {
4175 stepinfo
= &caps
->stepinfos
[i
];
4176 step_size
= stepinfo
->stepsize
;
4178 for (j
= 0; j
< stepinfo
->nstrengths
; j
++) {
4179 strength
= stepinfo
->strengths
[j
];
4182 * If both step size and strength are smaller than the
4183 * chip's requirement, it is not easy to compare the
4184 * resulted reliability.
4186 if (step_size
< req_step
&& strength
< req_strength
)
4189 if (mtd
->writesize
% step_size
)
4192 nsteps
= mtd
->writesize
/ step_size
;
4194 ecc_bytes
= caps
->calc_ecc_bytes(step_size
, strength
);
4195 if (WARN_ON_ONCE(ecc_bytes
< 0))
4197 ecc_bytes_total
= ecc_bytes
* nsteps
;
4199 if (ecc_bytes_total
> oobavail
||
4200 strength
* nsteps
< req_corr
)
4204 * We assume the best is to meet the chip's requrement
4205 * with the least number of ECC bytes.
4207 if (ecc_bytes_total
< best_ecc_bytes_total
) {
4208 best_ecc_bytes_total
= ecc_bytes_total
;
4209 best_step
= step_size
;
4210 best_strength
= strength
;
4211 best_ecc_bytes
= ecc_bytes
;
4216 if (best_ecc_bytes_total
== INT_MAX
)
4219 chip
->ecc
.size
= best_step
;
4220 chip
->ecc
.strength
= best_strength
;
4221 chip
->ecc
.bytes
= best_ecc_bytes
;
4225 EXPORT_SYMBOL_GPL(nand_match_ecc_req
);
4228 * nand_maximize_ecc - choose the max ECC strength available
4229 * @chip: nand chip info structure
4230 * @caps: ECC engine caps info structure
4231 * @oobavail: OOB size that the ECC engine can use
4233 * Choose the max ECC strength that is supported on the controller, and can fit
4234 * within the chip's OOB. On success, the chosen ECC settings are set.
4236 int nand_maximize_ecc(struct nand_chip
*chip
,
4237 const struct nand_ecc_caps
*caps
, int oobavail
)
4239 struct mtd_info
*mtd
= nand_to_mtd(chip
);
4240 const struct nand_ecc_step_info
*stepinfo
;
4241 int step_size
, strength
, nsteps
, ecc_bytes
, corr
;
4244 int best_strength
, best_ecc_bytes
;
4247 if (WARN_ON(oobavail
< 0))
4250 for (i
= 0; i
< caps
->nstepinfos
; i
++) {
4251 stepinfo
= &caps
->stepinfos
[i
];
4252 step_size
= stepinfo
->stepsize
;
4254 /* If chip->ecc.size is already set, respect it */
4255 if (chip
->ecc
.size
&& step_size
!= chip
->ecc
.size
)
4258 for (j
= 0; j
< stepinfo
->nstrengths
; j
++) {
4259 strength
= stepinfo
->strengths
[j
];
4261 if (mtd
->writesize
% step_size
)
4264 nsteps
= mtd
->writesize
/ step_size
;
4266 ecc_bytes
= caps
->calc_ecc_bytes(step_size
, strength
);
4267 if (WARN_ON_ONCE(ecc_bytes
< 0))
4270 if (ecc_bytes
* nsteps
> oobavail
)
4273 corr
= strength
* nsteps
;
4276 * If the number of correctable bits is the same,
4277 * bigger step_size has more reliability.
4279 if (corr
> best_corr
||
4280 (corr
== best_corr
&& step_size
> best_step
)) {
4282 best_step
= step_size
;
4283 best_strength
= strength
;
4284 best_ecc_bytes
= ecc_bytes
;
4292 chip
->ecc
.size
= best_step
;
4293 chip
->ecc
.strength
= best_strength
;
4294 chip
->ecc
.bytes
= best_ecc_bytes
;
4298 EXPORT_SYMBOL_GPL(nand_maximize_ecc
);
4301 * Check if the chip configuration meet the datasheet requirements.
4303 * If our configuration corrects A bits per B bytes and the minimum
4304 * required correction level is X bits per Y bytes, then we must ensure
4305 * both of the following are true:
4307 * (1) A / B >= X / Y
4310 * Requirement (1) ensures we can correct for the required bitflip density.
4311 * Requirement (2) ensures we can correct even when all bitflips are clumped
4312 * in the same sector.
4314 static bool nand_ecc_strength_good(struct mtd_info
*mtd
)
4316 struct nand_chip
*chip
= mtd_to_nand(mtd
);
4317 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
4320 if (ecc
->size
== 0 || chip
->ecc_step_ds
== 0)
4321 /* Not enough information */
4325 * We get the number of corrected bits per page to compare
4326 * the correction density.
4328 corr
= (mtd
->writesize
* ecc
->strength
) / ecc
->size
;
4329 ds_corr
= (mtd
->writesize
* chip
->ecc_strength_ds
) / chip
->ecc_step_ds
;
4331 return corr
>= ds_corr
&& ecc
->strength
>= chip
->ecc_strength_ds
;
4334 static bool invalid_ecc_page_accessors(struct nand_chip
*chip
)
4336 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
4338 if (nand_standard_page_accessors(ecc
))
4342 * NAND_ECC_CUSTOM_PAGE_ACCESS flag is set, make sure the NAND
4343 * controller driver implements all the page accessors because
4344 * default helpers are not suitable when the core does not
4345 * send the READ0/PAGEPROG commands.
4347 return (!ecc
->read_page
|| !ecc
->write_page
||
4348 !ecc
->read_page_raw
|| !ecc
->write_page_raw
||
4349 (NAND_HAS_SUBPAGE_READ(chip
) && !ecc
->read_subpage
) ||
4350 (NAND_HAS_SUBPAGE_WRITE(chip
) && !ecc
->write_subpage
&&
4351 ecc
->hwctl
&& ecc
->calculate
));
4355 * nand_scan_tail - [NAND Interface] Scan for the NAND device
4356 * @mtd: MTD device structure
4358 * This is the second phase of the normal nand_scan() function. It fills out
4359 * all the uninitialized function pointers with the defaults and scans for a
4360 * bad block table if appropriate.
4362 int nand_scan_tail(struct mtd_info
*mtd
)
4365 struct nand_chip
*chip
= mtd_to_nand(mtd
);
4366 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
4367 struct nand_buffers
*nbuf
;
4369 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
4370 BUG_ON((chip
->bbt_options
& NAND_BBT_NO_OOB_BBM
) &&
4371 !(chip
->bbt_options
& NAND_BBT_USE_FLASH
));
4373 if (invalid_ecc_page_accessors(chip
)) {
4374 pr_err("Invalid ECC page accessors setup\n");
4378 if (!(chip
->options
& NAND_OWN_BUFFERS
)) {
4379 nbuf
= kzalloc(sizeof(struct nand_buffers
), GFP_KERNEL
);
4380 chip
->buffers
= nbuf
;
4386 /* Set the internal oob buffer location, just after the page data */
4387 chip
->oob_poi
= chip
->buffers
->databuf
+ mtd
->writesize
;
4390 * If no default placement scheme is given, select an appropriate one.
4392 if (!ecc
->layout
&& (ecc
->mode
!= NAND_ECC_SOFT_BCH
)) {
4393 switch (mtd
->oobsize
) {
4395 ecc
->layout
= &nand_oob_8
;
4398 ecc
->layout
= &nand_oob_16
;
4401 ecc
->layout
= &nand_oob_64
;
4404 ecc
->layout
= &nand_oob_128
;
4407 pr_warn("No oob scheme defined for oobsize %d\n",
4413 if (!chip
->write_page
)
4414 chip
->write_page
= nand_write_page
;
4417 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
4418 * selected and we have 256 byte pagesize fallback to software ECC
4421 switch (ecc
->mode
) {
4422 case NAND_ECC_HW_OOB_FIRST
:
4423 /* Similar to NAND_ECC_HW, but a separate read_page handle */
4424 if (!ecc
->calculate
|| !ecc
->correct
|| !ecc
->hwctl
) {
4425 pr_warn("No ECC functions supplied; hardware ECC not possible\n");
4428 if (!ecc
->read_page
)
4429 ecc
->read_page
= nand_read_page_hwecc_oob_first
;
4432 /* Use standard hwecc read page function? */
4433 if (!ecc
->read_page
)
4434 ecc
->read_page
= nand_read_page_hwecc
;
4435 if (!ecc
->write_page
)
4436 ecc
->write_page
= nand_write_page_hwecc
;
4437 if (!ecc
->read_page_raw
)
4438 ecc
->read_page_raw
= nand_read_page_raw
;
4439 if (!ecc
->write_page_raw
)
4440 ecc
->write_page_raw
= nand_write_page_raw
;
4442 ecc
->read_oob
= nand_read_oob_std
;
4443 if (!ecc
->write_oob
)
4444 ecc
->write_oob
= nand_write_oob_std
;
4445 if (!ecc
->read_subpage
)
4446 ecc
->read_subpage
= nand_read_subpage
;
4447 if (!ecc
->write_subpage
&& ecc
->hwctl
&& ecc
->calculate
)
4448 ecc
->write_subpage
= nand_write_subpage_hwecc
;
4450 case NAND_ECC_HW_SYNDROME
:
4451 if ((!ecc
->calculate
|| !ecc
->correct
|| !ecc
->hwctl
) &&
4453 ecc
->read_page
== nand_read_page_hwecc
||
4455 ecc
->write_page
== nand_write_page_hwecc
)) {
4456 pr_warn("No ECC functions supplied; hardware ECC not possible\n");
4459 /* Use standard syndrome read/write page function? */
4460 if (!ecc
->read_page
)
4461 ecc
->read_page
= nand_read_page_syndrome
;
4462 if (!ecc
->write_page
)
4463 ecc
->write_page
= nand_write_page_syndrome
;
4464 if (!ecc
->read_page_raw
)
4465 ecc
->read_page_raw
= nand_read_page_raw_syndrome
;
4466 if (!ecc
->write_page_raw
)
4467 ecc
->write_page_raw
= nand_write_page_raw_syndrome
;
4469 ecc
->read_oob
= nand_read_oob_syndrome
;
4470 if (!ecc
->write_oob
)
4471 ecc
->write_oob
= nand_write_oob_syndrome
;
4473 if (mtd
->writesize
>= ecc
->size
) {
4474 if (!ecc
->strength
) {
4475 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
4480 pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
4481 ecc
->size
, mtd
->writesize
);
4482 ecc
->mode
= NAND_ECC_SOFT
;
4485 ecc
->calculate
= nand_calculate_ecc
;
4486 ecc
->correct
= nand_correct_data
;
4487 ecc
->read_page
= nand_read_page_swecc
;
4488 ecc
->read_subpage
= nand_read_subpage
;
4489 ecc
->write_page
= nand_write_page_swecc
;
4490 ecc
->read_page_raw
= nand_read_page_raw
;
4491 ecc
->write_page_raw
= nand_write_page_raw
;
4492 ecc
->read_oob
= nand_read_oob_std
;
4493 ecc
->write_oob
= nand_write_oob_std
;
4500 case NAND_ECC_SOFT_BCH
:
4501 if (!mtd_nand_has_bch()) {
4502 pr_warn("CONFIG_MTD_NAND_ECC_BCH not enabled\n");
4505 ecc
->calculate
= nand_bch_calculate_ecc
;
4506 ecc
->correct
= nand_bch_correct_data
;
4507 ecc
->read_page
= nand_read_page_swecc
;
4508 ecc
->read_subpage
= nand_read_subpage
;
4509 ecc
->write_page
= nand_write_page_swecc
;
4510 ecc
->read_page_raw
= nand_read_page_raw
;
4511 ecc
->write_page_raw
= nand_write_page_raw
;
4512 ecc
->read_oob
= nand_read_oob_std
;
4513 ecc
->write_oob
= nand_write_oob_std
;
4515 * Board driver should supply ecc.size and ecc.strength values
4516 * to select how many bits are correctable. Otherwise, default
4517 * to 4 bits for large page devices.
4519 if (!ecc
->size
&& (mtd
->oobsize
>= 64)) {
4524 /* See nand_bch_init() for details. */
4526 ecc
->priv
= nand_bch_init(mtd
);
4528 pr_warn("BCH ECC initialization failed!\n");
4534 pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n");
4535 ecc
->read_page
= nand_read_page_raw
;
4536 ecc
->write_page
= nand_write_page_raw
;
4537 ecc
->read_oob
= nand_read_oob_std
;
4538 ecc
->read_page_raw
= nand_read_page_raw
;
4539 ecc
->write_page_raw
= nand_write_page_raw
;
4540 ecc
->write_oob
= nand_write_oob_std
;
4541 ecc
->size
= mtd
->writesize
;
4547 pr_warn("Invalid NAND_ECC_MODE %d\n", ecc
->mode
);
4551 /* For many systems, the standard OOB write also works for raw */
4552 if (!ecc
->read_oob_raw
)
4553 ecc
->read_oob_raw
= ecc
->read_oob
;
4554 if (!ecc
->write_oob_raw
)
4555 ecc
->write_oob_raw
= ecc
->write_oob
;
4558 * The number of bytes available for a client to place data into
4559 * the out of band area.
4563 for (i
= 0; ecc
->layout
->oobfree
[i
].length
; i
++)
4564 mtd
->oobavail
+= ecc
->layout
->oobfree
[i
].length
;
4567 /* ECC sanity check: warn if it's too weak */
4568 if (!nand_ecc_strength_good(mtd
))
4569 pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n",
4573 * Set the number of read / write steps for one page depending on ECC
4576 ecc
->steps
= mtd
->writesize
/ ecc
->size
;
4577 if (ecc
->steps
* ecc
->size
!= mtd
->writesize
) {
4578 pr_warn("Invalid ECC parameters\n");
4581 ecc
->total
= ecc
->steps
* ecc
->bytes
;
4583 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
4584 if (!(chip
->options
& NAND_NO_SUBPAGE_WRITE
) && nand_is_slc(chip
)) {
4585 switch (ecc
->steps
) {
4587 mtd
->subpage_sft
= 1;
4592 mtd
->subpage_sft
= 2;
4596 chip
->subpagesize
= mtd
->writesize
>> mtd
->subpage_sft
;
4598 /* Initialize state */
4599 chip
->state
= FL_READY
;
4601 /* Invalidate the pagebuffer reference */
4604 /* Large page NAND with SOFT_ECC should support subpage reads */
4605 switch (ecc
->mode
) {
4607 case NAND_ECC_SOFT_BCH
:
4608 if (chip
->page_shift
> 9)
4609 chip
->options
|= NAND_SUBPAGE_READ
;
4616 /* Fill in remaining MTD driver data */
4617 mtd
->type
= nand_is_slc(chip
) ? MTD_NANDFLASH
: MTD_MLCNANDFLASH
;
4618 mtd
->flags
= (chip
->options
& NAND_ROM
) ? MTD_CAP_ROM
:
4620 mtd
->_erase
= nand_erase
;
4621 mtd
->_read
= nand_read
;
4622 mtd
->_write
= nand_write
;
4623 mtd
->_panic_write
= panic_nand_write
;
4624 mtd
->_read_oob
= nand_read_oob
;
4625 mtd
->_write_oob
= nand_write_oob
;
4626 mtd
->_sync
= nand_sync
;
4628 mtd
->_unlock
= NULL
;
4629 mtd
->_block_isreserved
= nand_block_isreserved
;
4630 mtd
->_block_isbad
= nand_block_isbad
;
4631 mtd
->_block_markbad
= nand_block_markbad
;
4632 mtd
->writebufsize
= mtd
->writesize
;
4634 /* propagate ecc info to mtd_info */
4635 mtd
->ecclayout
= ecc
->layout
;
4636 mtd
->ecc_strength
= ecc
->strength
;
4637 mtd
->ecc_step_size
= ecc
->size
;
4639 * Initialize bitflip_threshold to its default prior scan_bbt() call.
4640 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
4643 if (!mtd
->bitflip_threshold
)
4644 mtd
->bitflip_threshold
= DIV_ROUND_UP(mtd
->ecc_strength
* 3, 4);
4648 EXPORT_SYMBOL(nand_scan_tail
);
4651 * nand_scan - [NAND Interface] Scan for the NAND device
4652 * @mtd: MTD device structure
4653 * @maxchips: number of chips to scan for
4655 * This fills out all the uninitialized function pointers with the defaults.
4656 * The flash ID is read and the mtd/chip structures are filled with the
4657 * appropriate values.
4659 int nand_scan(struct mtd_info
*mtd
, int maxchips
)
4663 ret
= nand_scan_ident(mtd
, maxchips
, NULL
);
4665 ret
= nand_scan_tail(mtd
);
4668 EXPORT_SYMBOL(nand_scan
);
4670 MODULE_LICENSE("GPL");
4671 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
4672 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
4673 MODULE_DESCRIPTION("Generic NAND flash driver code");