]> git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/mtd/nand/nand_base.c
projects / people / ms / u-boot.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
mtd: nand: Include linux/mtd/partitions.h in nand_base.h
[people/ms/u-boot.git] / drivers / mtd / nand / nand_base.c
1 /*
2 * drivers/mtd/nand.c
3 *
4 * Overview:
5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
8 *
9 * Additional technical information is available on
10 * http://www.linux-mtd.infradead.org/doc/nand.html
11 *
12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
14 *
15 * Credits:
16 * David Woodhouse for adding multichip support
17 *
18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
20 *
21 * TODO:
22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
24 * if we have HW ecc support.
25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
27 * BBT table is not serialized, has to be fixed
28 *
29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License version 2 as
31 * published by the Free Software Foundation.
32 *
33 */
34
35 /* XXX U-BOOT XXX */
36 #if 0
37 #include <linux/module.h>
38 #include <linux/delay.h>
39 #include <linux/errno.h>
40 #include <linux/err.h>
41 #include <linux/sched.h>
42 #include <linux/slab.h>
43 #include <linux/types.h>
44 #include <linux/mtd/mtd.h>
45 #include <linux/mtd/nand.h>
46 #include <linux/mtd/nand_ecc.h>
47 #include <linux/mtd/compatmac.h>
48 #include <linux/interrupt.h>
49 #include <linux/bitops.h>
50 #include <linux/leds.h>
51 #include <asm/io.h>
52
53 #ifdef CONFIG_MTD_PARTITIONS
54 #include <linux/mtd/partitions.h>
55 #endif
56
57 #endif
58
59 #include <common.h>
60
61 #define ENOTSUPP 524 /* Operation is not supported */
62
63 #include <malloc.h>
64 #include <watchdog.h>
65 #include <linux/err.h>
66 #include <linux/mtd/compat.h>
67 #include <linux/mtd/mtd.h>
68 #include <linux/mtd/nand.h>
69 #include <linux/mtd/nand_ecc.h>
70
71 #ifdef CONFIG_MTD_PARTITIONS
72 #include <linux/mtd/partitions.h>
73 #endif
74
75 #include <asm/io.h>
76 #include <asm/errno.h>
77
78 #ifdef CONFIG_JFFS2_NAND
79 #include <jffs2/jffs2.h>
80 #endif
81
82 /*
83 * CONFIG_SYS_NAND_RESET_CNT is used as a timeout mechanism when resetting
84 * a flash. NAND flash is initialized prior to interrupts so standard timers
85 * can't be used. CONFIG_SYS_NAND_RESET_CNT should be set to a value
86 * which is greater than (max NAND reset time / NAND status read time).
87 * A conservative default of 200000 (500 us / 25 ns) is used as a default.
88 */
89 #ifndef CONFIG_SYS_NAND_RESET_CNT
90 #define CONFIG_SYS_NAND_RESET_CNT 200000
91 #endif
92
93 /* Define default oob placement schemes for large and small page devices */
94 static struct nand_ecclayout nand_oob_8 = {
95 .eccbytes = 3,
96 .eccpos = {0, 1, 2},
97 .oobfree = {
98 {.offset = 3,
99 .length = 2},
100 {.offset = 6,
101 .length = 2}}
102 };
103
104 static struct nand_ecclayout nand_oob_16 = {
105 .eccbytes = 6,
106 .eccpos = {0, 1, 2, 3, 6, 7},
107 .oobfree = {
108 {.offset = 8,
109 . length = 8}}
110 };
111
112 static struct nand_ecclayout nand_oob_64 = {
113 .eccbytes = 24,
114 .eccpos = {
115 40, 41, 42, 43, 44, 45, 46, 47,
116 48, 49, 50, 51, 52, 53, 54, 55,
117 56, 57, 58, 59, 60, 61, 62, 63},
118 .oobfree = {
119 {.offset = 2,
120 .length = 38}}
121 };
122
123 static struct nand_ecclayout nand_oob_128 = {
124 .eccbytes = 48,
125 .eccpos = {
126 80, 81, 82, 83, 84, 85, 86, 87,
127 88, 89, 90, 91, 92, 93, 94, 95,
128 96, 97, 98, 99, 100, 101, 102, 103,
129 104, 105, 106, 107, 108, 109, 110, 111,
130 112, 113, 114, 115, 116, 117, 118, 119,
131 120, 121, 122, 123, 124, 125, 126, 127},
132 .oobfree = {
133 {.offset = 2,
134 .length = 78}}
135 };
136
137
138 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
139 int new_state);
140
141 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
142 struct mtd_oob_ops *ops);
143
144 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this);
145
146 /*
147 * For devices which display every fart in the system on a separate LED. Is
148 * compiled away when LED support is disabled.
149 */
150 /* XXX U-BOOT XXX */
151 #if 0
152 DEFINE_LED_TRIGGER(nand_led_trigger);
153 #endif
154
155 /**
156 * nand_release_device - [GENERIC] release chip
157 * @mtd: MTD device structure
158 *
159 * Deselect, release chip lock and wake up anyone waiting on the device
160 */
161 /* XXX U-BOOT XXX */
162 #if 0
163 static void nand_release_device(struct mtd_info *mtd)
164 {
165 struct nand_chip *chip = mtd->priv;
166
167 /* De-select the NAND device */
168 chip->select_chip(mtd, -1);
169
170 /* Release the controller and the chip */
171 spin_lock(&chip->controller->lock);
172 chip->controller->active = NULL;
173 chip->state = FL_READY;
174 wake_up(&chip->controller->wq);
175 spin_unlock(&chip->controller->lock);
176 }
177 #else
178 static void nand_release_device (struct mtd_info *mtd)
179 {
180 struct nand_chip *this = mtd->priv;
181 this->select_chip(mtd, -1); /* De-select the NAND device */
182 }
183 #endif
184
185 /**
186 * nand_read_byte - [DEFAULT] read one byte from the chip
187 * @mtd: MTD device structure
188 *
189 * Default read function for 8bit buswith
190 */
191 static uint8_t nand_read_byte(struct mtd_info *mtd)
192 {
193 struct nand_chip *chip = mtd->priv;
194 return readb(chip->IO_ADDR_R);
195 }
196
197 /**
198 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
199 * @mtd: MTD device structure
200 *
201 * Default read function for 16bit buswith with
202 * endianess conversion
203 */
204 static uint8_t nand_read_byte16(struct mtd_info *mtd)
205 {
206 struct nand_chip *chip = mtd->priv;
207 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
208 }
209
210 /**
211 * nand_read_word - [DEFAULT] read one word from the chip
212 * @mtd: MTD device structure
213 *
214 * Default read function for 16bit buswith without
215 * endianess conversion
216 */
217 static u16 nand_read_word(struct mtd_info *mtd)
218 {
219 struct nand_chip *chip = mtd->priv;
220 return readw(chip->IO_ADDR_R);
221 }
222
223 /**
224 * nand_select_chip - [DEFAULT] control CE line
225 * @mtd: MTD device structure
226 * @chipnr: chipnumber to select, -1 for deselect
227 *
228 * Default select function for 1 chip devices.
229 */
230 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
231 {
232 struct nand_chip *chip = mtd->priv;
233
234 switch (chipnr) {
235 case -1:
236 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
237 break;
238 case 0:
239 break;
240
241 default:
242 BUG();
243 }
244 }
245
246 /**
247 * nand_write_buf - [DEFAULT] write buffer to chip
248 * @mtd: MTD device structure
249 * @buf: data buffer
250 * @len: number of bytes to write
251 *
252 * Default write function for 8bit buswith
253 */
254 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
255 {
256 int i;
257 struct nand_chip *chip = mtd->priv;
258
259 for (i = 0; i < len; i++)
260 writeb(buf[i], chip->IO_ADDR_W);
261 }
262
263 /**
264 * nand_read_buf - [DEFAULT] read chip data into buffer
265 * @mtd: MTD device structure
266 * @buf: buffer to store date
267 * @len: number of bytes to read
268 *
269 * Default read function for 8bit buswith
270 */
271 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
272 {
273 int i;
274 struct nand_chip *chip = mtd->priv;
275
276 for (i = 0; i < len; i++)
277 buf[i] = readb(chip->IO_ADDR_R);
278 }
279
280 /**
281 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
282 * @mtd: MTD device structure
283 * @buf: buffer containing the data to compare
284 * @len: number of bytes to compare
285 *
286 * Default verify function for 8bit buswith
287 */
288 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
289 {
290 int i;
291 struct nand_chip *chip = mtd->priv;
292
293 for (i = 0; i < len; i++)
294 if (buf[i] != readb(chip->IO_ADDR_R))
295 return -EFAULT;
296 return 0;
297 }
298
299 /**
300 * nand_write_buf16 - [DEFAULT] write buffer to chip
301 * @mtd: MTD device structure
302 * @buf: data buffer
303 * @len: number of bytes to write
304 *
305 * Default write function for 16bit buswith
306 */
307 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
308 {
309 int i;
310 struct nand_chip *chip = mtd->priv;
311 u16 *p = (u16 *) buf;
312 len >>= 1;
313
314 for (i = 0; i < len; i++)
315 writew(p[i], chip->IO_ADDR_W);
316
317 }
318
319 /**
320 * nand_read_buf16 - [DEFAULT] read chip data into buffer
321 * @mtd: MTD device structure
322 * @buf: buffer to store date
323 * @len: number of bytes to read
324 *
325 * Default read function for 16bit buswith
326 */
327 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
328 {
329 int i;
330 struct nand_chip *chip = mtd->priv;
331 u16 *p = (u16 *) buf;
332 len >>= 1;
333
334 for (i = 0; i < len; i++)
335 p[i] = readw(chip->IO_ADDR_R);
336 }
337
338 /**
339 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
340 * @mtd: MTD device structure
341 * @buf: buffer containing the data to compare
342 * @len: number of bytes to compare
343 *
344 * Default verify function for 16bit buswith
345 */
346 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
347 {
348 int i;
349 struct nand_chip *chip = mtd->priv;
350 u16 *p = (u16 *) buf;
351 len >>= 1;
352
353 for (i = 0; i < len; i++)
354 if (p[i] != readw(chip->IO_ADDR_R))
355 return -EFAULT;
356
357 return 0;
358 }
359
360 /**
361 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
362 * @mtd: MTD device structure
363 * @ofs: offset from device start
364 * @getchip: 0, if the chip is already selected
365 *
366 * Check, if the block is bad.
367 */
368 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
369 {
370 int page, chipnr, res = 0;
371 struct nand_chip *chip = mtd->priv;
372 u16 bad;
373
374 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
375
376 if (getchip) {
377 chipnr = (int)(ofs >> chip->chip_shift);
378
379 nand_get_device(chip, mtd, FL_READING);
380
381 /* Select the NAND device */
382 chip->select_chip(mtd, chipnr);
383 }
384
385 if (chip->options & NAND_BUSWIDTH_16) {
386 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
387 page);
388 bad = cpu_to_le16(chip->read_word(mtd));
389 if (chip->badblockpos & 0x1)
390 bad >>= 8;
391 if ((bad & 0xFF) != 0xff)
392 res = 1;
393 } else {
394 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
395 if (chip->read_byte(mtd) != 0xff)
396 res = 1;
397 }
398
399 if (getchip)
400 nand_release_device(mtd);
401
402 return res;
403 }
404
405 /**
406 * nand_default_block_markbad - [DEFAULT] mark a block bad
407 * @mtd: MTD device structure
408 * @ofs: offset from device start
409 *
410 * This is the default implementation, which can be overridden by
411 * a hardware specific driver.
412 */
413 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
414 {
415 struct nand_chip *chip = mtd->priv;
416 uint8_t buf[2] = { 0, 0 };
417 int block, ret;
418
419 /* Get block number */
420 block = (int)(ofs >> chip->bbt_erase_shift);
421 if (chip->bbt)
422 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
423
424 /* Do we have a flash based bad block table ? */
425 if (chip->options & NAND_USE_FLASH_BBT)
426 ret = nand_update_bbt(mtd, ofs);
427 else {
428 /* We write two bytes, so we dont have to mess with 16 bit
429 * access
430 */
431 nand_get_device(chip, mtd, FL_WRITING);
432 ofs += mtd->oobsize;
433 chip->ops.len = chip->ops.ooblen = 2;
434 chip->ops.datbuf = NULL;
435 chip->ops.oobbuf = buf;
436 chip->ops.ooboffs = chip->badblockpos & ~0x01;
437
438 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
439 nand_release_device(mtd);
440 }
441 if (!ret)
442 mtd->ecc_stats.badblocks++;
443
444 return ret;
445 }
446
447 /**
448 * nand_check_wp - [GENERIC] check if the chip is write protected
449 * @mtd: MTD device structure
450 * Check, if the device is write protected
451 *
452 * The function expects, that the device is already selected
453 */
454 static int nand_check_wp(struct mtd_info *mtd)
455 {
456 struct nand_chip *chip = mtd->priv;
457 /* Check the WP bit */
458 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
459 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
460 }
461
462 /**
463 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
464 * @mtd: MTD device structure
465 * @ofs: offset from device start
466 * @getchip: 0, if the chip is already selected
467 * @allowbbt: 1, if its allowed to access the bbt area
468 *
469 * Check, if the block is bad. Either by reading the bad block table or
470 * calling of the scan function.
471 */
472 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
473 int allowbbt)
474 {
475 struct nand_chip *chip = mtd->priv;
476
477 if (!(chip->options & NAND_BBT_SCANNED)) {
478 chip->options |= NAND_BBT_SCANNED;
479 chip->scan_bbt(mtd);
480 }
481
482 if (!chip->bbt)
483 return chip->block_bad(mtd, ofs, getchip);
484
485 /* Return info from the table */
486 return nand_isbad_bbt(mtd, ofs, allowbbt);
487 }
488
489 /*
490 * Wait for the ready pin, after a command
491 * The timeout is catched later.
492 */
493 /* XXX U-BOOT XXX */
494 #if 0
495 void nand_wait_ready(struct mtd_info *mtd)
496 {
497 struct nand_chip *chip = mtd->priv;
498 unsigned long timeo = jiffies + 2;
499
500 led_trigger_event(nand_led_trigger, LED_FULL);
501 /* wait until command is processed or timeout occures */
502 do {
503 if (chip->dev_ready(mtd))
504 break;
505 touch_softlockup_watchdog();
506 } while (time_before(jiffies, timeo));
507 led_trigger_event(nand_led_trigger, LED_OFF);
508 }
509 EXPORT_SYMBOL_GPL(nand_wait_ready);
510 #else
511 void nand_wait_ready(struct mtd_info *mtd)
512 {
513 struct nand_chip *chip = mtd->priv;
514 u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
515
516 reset_timer();
517
518 /* wait until command is processed or timeout occures */
519 while (get_timer(0) < timeo) {
520 if (chip->dev_ready)
521 if (chip->dev_ready(mtd))
522 break;
523 }
524 }
525 #endif
526
527 /**
528 * nand_command - [DEFAULT] Send command to NAND device
529 * @mtd: MTD device structure
530 * @command: the command to be sent
531 * @column: the column address for this command, -1 if none
532 * @page_addr: the page address for this command, -1 if none
533 *
534 * Send command to NAND device. This function is used for small page
535 * devices (256/512 Bytes per page)
536 */
537 static void nand_command(struct mtd_info *mtd, unsigned int command,
538 int column, int page_addr)
539 {
540 register struct nand_chip *chip = mtd->priv;
541 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
542 uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
543
544 /*
545 * Write out the command to the device.
546 */
547 if (command == NAND_CMD_SEQIN) {
548 int readcmd;
549
550 if (column >= mtd->writesize) {
551 /* OOB area */
552 column -= mtd->writesize;
553 readcmd = NAND_CMD_READOOB;
554 } else if (column < 256) {
555 /* First 256 bytes --> READ0 */
556 readcmd = NAND_CMD_READ0;
557 } else {
558 column -= 256;
559 readcmd = NAND_CMD_READ1;
560 }
561 chip->cmd_ctrl(mtd, readcmd, ctrl);
562 ctrl &= ~NAND_CTRL_CHANGE;
563 }
564 chip->cmd_ctrl(mtd, command, ctrl);
565
566 /*
567 * Address cycle, when necessary
568 */
569 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
570 /* Serially input address */
571 if (column != -1) {
572 /* Adjust columns for 16 bit buswidth */
573 if (chip->options & NAND_BUSWIDTH_16)
574 column >>= 1;
575 chip->cmd_ctrl(mtd, column, ctrl);
576 ctrl &= ~NAND_CTRL_CHANGE;
577 }
578 if (page_addr != -1) {
579 chip->cmd_ctrl(mtd, page_addr, ctrl);
580 ctrl &= ~NAND_CTRL_CHANGE;
581 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
582 /* One more address cycle for devices > 32MiB */
583 if (chip->chipsize > (32 << 20))
584 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
585 }
586 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
587
588 /*
589 * program and erase have their own busy handlers
590 * status and sequential in needs no delay
591 */
592 switch (command) {
593
594 case NAND_CMD_PAGEPROG:
595 case NAND_CMD_ERASE1:
596 case NAND_CMD_ERASE2:
597 case NAND_CMD_SEQIN:
598 case NAND_CMD_STATUS:
599 return;
600
601 case NAND_CMD_RESET:
602 if (chip->dev_ready)
603 break;
604 udelay(chip->chip_delay);
605 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
606 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
607 chip->cmd_ctrl(mtd,
608 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
609 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
610 (rst_sts_cnt--));
611 return;
612
613 /* This applies to read commands */
614 default:
615 /*
616 * If we don't have access to the busy pin, we apply the given
617 * command delay
618 */
619 if (!chip->dev_ready) {
620 udelay(chip->chip_delay);
621 return;
622 }
623 }
624 /* Apply this short delay always to ensure that we do wait tWB in
625 * any case on any machine. */
626 ndelay(100);
627
628 nand_wait_ready(mtd);
629 }
630
631 /**
632 * nand_command_lp - [DEFAULT] Send command to NAND large page device
633 * @mtd: MTD device structure
634 * @command: the command to be sent
635 * @column: the column address for this command, -1 if none
636 * @page_addr: the page address for this command, -1 if none
637 *
638 * Send command to NAND device. This is the version for the new large page
639 * devices We dont have the separate regions as we have in the small page
640 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
641 */
642 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
643 int column, int page_addr)
644 {
645 register struct nand_chip *chip = mtd->priv;
646 uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
647
648 /* Emulate NAND_CMD_READOOB */
649 if (command == NAND_CMD_READOOB) {
650 column += mtd->writesize;
651 command = NAND_CMD_READ0;
652 }
653
654 /* Command latch cycle */
655 chip->cmd_ctrl(mtd, command & 0xff,
656 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
657
658 if (column != -1 || page_addr != -1) {
659 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
660
661 /* Serially input address */
662 if (column != -1) {
663 /* Adjust columns for 16 bit buswidth */
664 if (chip->options & NAND_BUSWIDTH_16)
665 column >>= 1;
666 chip->cmd_ctrl(mtd, column, ctrl);
667 ctrl &= ~NAND_CTRL_CHANGE;
668 chip->cmd_ctrl(mtd, column >> 8, ctrl);
669 }
670 if (page_addr != -1) {
671 chip->cmd_ctrl(mtd, page_addr, ctrl);
672 chip->cmd_ctrl(mtd, page_addr >> 8,
673 NAND_NCE | NAND_ALE);
674 /* One more address cycle for devices > 128MiB */
675 if (chip->chipsize > (128 << 20))
676 chip->cmd_ctrl(mtd, page_addr >> 16,
677 NAND_NCE | NAND_ALE);
678 }
679 }
680 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
681
682 /*
683 * program and erase have their own busy handlers
684 * status, sequential in, and deplete1 need no delay
685 */
686 switch (command) {
687
688 case NAND_CMD_CACHEDPROG:
689 case NAND_CMD_PAGEPROG:
690 case NAND_CMD_ERASE1:
691 case NAND_CMD_ERASE2:
692 case NAND_CMD_SEQIN:
693 case NAND_CMD_RNDIN:
694 case NAND_CMD_STATUS:
695 case NAND_CMD_DEPLETE1:
696 return;
697
698 /*
699 * read error status commands require only a short delay
700 */
701 case NAND_CMD_STATUS_ERROR:
702 case NAND_CMD_STATUS_ERROR0:
703 case NAND_CMD_STATUS_ERROR1:
704 case NAND_CMD_STATUS_ERROR2:
705 case NAND_CMD_STATUS_ERROR3:
706 udelay(chip->chip_delay);
707 return;
708
709 case NAND_CMD_RESET:
710 if (chip->dev_ready)
711 break;
712 udelay(chip->chip_delay);
713 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
714 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
715 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
716 NAND_NCE | NAND_CTRL_CHANGE);
717 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
718 (rst_sts_cnt--));
719 return;
720
721 case NAND_CMD_RNDOUT:
722 /* No ready / busy check necessary */
723 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
724 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
725 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
726 NAND_NCE | NAND_CTRL_CHANGE);
727 return;
728
729 case NAND_CMD_READ0:
730 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
731 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
732 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
733 NAND_NCE | NAND_CTRL_CHANGE);
734
735 /* This applies to read commands */
736 default:
737 /*
738 * If we don't have access to the busy pin, we apply the given
739 * command delay
740 */
741 if (!chip->dev_ready) {
742 udelay(chip->chip_delay);
743 return;
744 }
745 }
746
747 /* Apply this short delay always to ensure that we do wait tWB in
748 * any case on any machine. */
749 ndelay(100);
750
751 nand_wait_ready(mtd);
752 }
753
754 /**
755 * nand_get_device - [GENERIC] Get chip for selected access
756 * @chip: the nand chip descriptor
757 * @mtd: MTD device structure
758 * @new_state: the state which is requested
759 *
760 * Get the device and lock it for exclusive access
761 */
762 /* XXX U-BOOT XXX */
763 #if 0
764 static int
765 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
766 {
767 spinlock_t *lock = &chip->controller->lock;
768 wait_queue_head_t *wq = &chip->controller->wq;
769 DECLARE_WAITQUEUE(wait, current);
770 retry:
771 spin_lock(lock);
772
773 /* Hardware controller shared among independend devices */
774 /* Hardware controller shared among independend devices */
775 if (!chip->controller->active)
776 chip->controller->active = chip;
777
778 if (chip->controller->active == chip && chip->state == FL_READY) {
779 chip->state = new_state;
780 spin_unlock(lock);
781 return 0;
782 }
783 if (new_state == FL_PM_SUSPENDED) {
784 spin_unlock(lock);
785 return (chip->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN;
786 }
787 set_current_state(TASK_UNINTERRUPTIBLE);
788 add_wait_queue(wq, &wait);
789 spin_unlock(lock);
790 schedule();
791 remove_wait_queue(wq, &wait);
792 goto retry;
793 }
794 #else
795 static int nand_get_device (struct nand_chip *this, struct mtd_info *mtd, int new_state)
796 {
797 this->state = new_state;
798 return 0;
799 }
800 #endif
801
802 /**
803 * nand_wait - [DEFAULT] wait until the command is done
804 * @mtd: MTD device structure
805 * @chip: NAND chip structure
806 *
807 * Wait for command done. This applies to erase and program only
808 * Erase can take up to 400ms and program up to 20ms according to
809 * general NAND and SmartMedia specs
810 */
811 /* XXX U-BOOT XXX */
812 #if 0
813 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
814 {
815
816 unsigned long timeo = jiffies;
817 int status, state = chip->state;
818
819 if (state == FL_ERASING)
820 timeo += (HZ * 400) / 1000;
821 else
822 timeo += (HZ * 20) / 1000;
823
824 led_trigger_event(nand_led_trigger, LED_FULL);
825
826 /* Apply this short delay always to ensure that we do wait tWB in
827 * any case on any machine. */
828 ndelay(100);
829
830 if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
831 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
832 else
833 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
834
835 while (time_before(jiffies, timeo)) {
836 if (chip->dev_ready) {
837 if (chip->dev_ready(mtd))
838 break;
839 } else {
840 if (chip->read_byte(mtd) & NAND_STATUS_READY)
841 break;
842 }
843 cond_resched();
844 }
845 led_trigger_event(nand_led_trigger, LED_OFF);
846
847 status = (int)chip->read_byte(mtd);
848 return status;
849 }
850 #else
851 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this)
852 {
853 unsigned long timeo;
854 int state = this->state;
855
856 if (state == FL_ERASING)
857 timeo = (CONFIG_SYS_HZ * 400) / 1000;
858 else
859 timeo = (CONFIG_SYS_HZ * 20) / 1000;
860
861 if ((state == FL_ERASING) && (this->options & NAND_IS_AND))
862 this->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
863 else
864 this->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
865
866 reset_timer();
867
868 while (1) {
869 if (get_timer(0) > timeo) {
870 printf("Timeout!");
871 return 0x01;
872 }
873
874 if (this->dev_ready) {
875 if (this->dev_ready(mtd))
876 break;
877 } else {
878 if (this->read_byte(mtd) & NAND_STATUS_READY)
879 break;
880 }
881 }
882 #ifdef PPCHAMELON_NAND_TIMER_HACK
883 reset_timer();
884 while (get_timer(0) < 10);
885 #endif /* PPCHAMELON_NAND_TIMER_HACK */
886
887 return this->read_byte(mtd);
888 }
889 #endif
890
891 /**
892 * nand_read_page_raw - [Intern] read raw page data without ecc
893 * @mtd: mtd info structure
894 * @chip: nand chip info structure
895 * @buf: buffer to store read data
896 */
897 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
898 uint8_t *buf)
899 {
900 chip->read_buf(mtd, buf, mtd->writesize);
901 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
902 return 0;
903 }
904
905 /**
906 * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
907 * @mtd: mtd info structure
908 * @chip: nand chip info structure
909 * @buf: buffer to store read data
910 */
911 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
912 uint8_t *buf)
913 {
914 int i, eccsize = chip->ecc.size;
915 int eccbytes = chip->ecc.bytes;
916 int eccsteps = chip->ecc.steps;
917 uint8_t *p = buf;
918 uint8_t *ecc_calc = chip->buffers->ecccalc;
919 uint8_t *ecc_code = chip->buffers->ecccode;
920 uint32_t *eccpos = chip->ecc.layout->eccpos;
921
922 chip->ecc.read_page_raw(mtd, chip, buf);
923
924 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
925 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
926
927 for (i = 0; i < chip->ecc.total; i++)
928 ecc_code[i] = chip->oob_poi[eccpos[i]];
929
930 eccsteps = chip->ecc.steps;
931 p = buf;
932
933 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
934 int stat;
935
936 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
937 if (stat < 0)
938 mtd->ecc_stats.failed++;
939 else
940 mtd->ecc_stats.corrected += stat;
941 }
942 return 0;
943 }
944
945 /**
946 * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
947 * @mtd: mtd info structure
948 * @chip: nand chip info structure
949 * @dataofs offset of requested data within the page
950 * @readlen data length
951 * @buf: buffer to store read data
952 */
953 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
954 {
955 int start_step, end_step, num_steps;
956 uint32_t *eccpos = chip->ecc.layout->eccpos;
957 uint8_t *p;
958 int data_col_addr, i, gaps = 0;
959 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
960 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
961
962 /* Column address wihin the page aligned to ECC size (256bytes). */
963 start_step = data_offs / chip->ecc.size;
964 end_step = (data_offs + readlen - 1) / chip->ecc.size;
965 num_steps = end_step - start_step + 1;
966
967 /* Data size aligned to ECC ecc.size*/
968 datafrag_len = num_steps * chip->ecc.size;
969 eccfrag_len = num_steps * chip->ecc.bytes;
970
971 data_col_addr = start_step * chip->ecc.size;
972 /* If we read not a page aligned data */
973 if (data_col_addr != 0)
974 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
975
976 p = bufpoi + data_col_addr;
977 chip->read_buf(mtd, p, datafrag_len);
978
979 /* Calculate ECC */
980 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
981 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
982
983 /* The performance is faster if to position offsets
984 according to ecc.pos. Let make sure here that
985 there are no gaps in ecc positions */
986 for (i = 0; i < eccfrag_len - 1; i++) {
987 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
988 eccpos[i + start_step * chip->ecc.bytes + 1]) {
989 gaps = 1;
990 break;
991 }
992 }
993 if (gaps) {
994 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
995 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
996 } else {
997 /* send the command to read the particular ecc bytes */
998 /* take care about buswidth alignment in read_buf */
999 aligned_pos = eccpos[start_step * chip->ecc.bytes] & ~(busw - 1);
1000 aligned_len = eccfrag_len;
1001 if (eccpos[start_step * chip->ecc.bytes] & (busw - 1))
1002 aligned_len++;
1003 if (eccpos[(start_step + num_steps) * chip->ecc.bytes] & (busw - 1))
1004 aligned_len++;
1005
1006 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize + aligned_pos, -1);
1007 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1008 }
1009
1010 for (i = 0; i < eccfrag_len; i++)
1011 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + start_step * chip->ecc.bytes]];
1012
1013 p = bufpoi + data_col_addr;
1014 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1015 int stat;
1016
1017 stat = chip->ecc.correct(mtd, p, &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1018 if (stat < 0)
1019 mtd->ecc_stats.failed++;
1020 else
1021 mtd->ecc_stats.corrected += stat;
1022 }
1023 return 0;
1024 }
1025
1026 /**
1027 * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
1028 * @mtd: mtd info structure
1029 * @chip: nand chip info structure
1030 * @buf: buffer to store read data
1031 *
1032 * Not for syndrome calculating ecc controllers which need a special oob layout
1033 */
1034 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1035 uint8_t *buf)
1036 {
1037 int i, eccsize = chip->ecc.size;
1038 int eccbytes = chip->ecc.bytes;
1039 int eccsteps = chip->ecc.steps;
1040 uint8_t *p = buf;
1041 uint8_t *ecc_calc = chip->buffers->ecccalc;
1042 uint8_t *ecc_code = chip->buffers->ecccode;
1043 uint32_t *eccpos = chip->ecc.layout->eccpos;
1044
1045 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1046 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1047 chip->read_buf(mtd, p, eccsize);
1048 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1049 }
1050 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1051
1052 for (i = 0; i < chip->ecc.total; i++)
1053 ecc_code[i] = chip->oob_poi[eccpos[i]];
1054
1055 eccsteps = chip->ecc.steps;
1056 p = buf;
1057
1058 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1059 int stat;
1060
1061 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1062 if (stat == -1)
1063 mtd->ecc_stats.failed++;
1064 else
1065 mtd->ecc_stats.corrected += stat;
1066 }
1067 return 0;
1068 }
1069
1070 /**
1071 * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
1072 * @mtd: mtd info structure
1073 * @chip: nand chip info structure
1074 * @buf: buffer to store read data
1075 *
1076 * The hw generator calculates the error syndrome automatically. Therefor
1077 * we need a special oob layout and handling.
1078 */
1079 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1080 uint8_t *buf)
1081 {
1082 int i, eccsize = chip->ecc.size;
1083 int eccbytes = chip->ecc.bytes;
1084 int eccsteps = chip->ecc.steps;
1085 uint8_t *p = buf;
1086 uint8_t *oob = chip->oob_poi;
1087
1088 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1089 int stat;
1090
1091 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1092 chip->read_buf(mtd, p, eccsize);
1093
1094 if (chip->ecc.prepad) {
1095 chip->read_buf(mtd, oob, chip->ecc.prepad);
1096 oob += chip->ecc.prepad;
1097 }
1098
1099 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1100 chip->read_buf(mtd, oob, eccbytes);
1101 stat = chip->ecc.correct(mtd, p, oob, NULL);
1102
1103 if (stat < 0)
1104 mtd->ecc_stats.failed++;
1105 else
1106 mtd->ecc_stats.corrected += stat;
1107
1108 oob += eccbytes;
1109
1110 if (chip->ecc.postpad) {
1111 chip->read_buf(mtd, oob, chip->ecc.postpad);
1112 oob += chip->ecc.postpad;
1113 }
1114 }
1115
1116 /* Calculate remaining oob bytes */
1117 i = mtd->oobsize - (oob - chip->oob_poi);
1118 if (i)
1119 chip->read_buf(mtd, oob, i);
1120
1121 return 0;
1122 }
1123
1124 /**
1125 * nand_transfer_oob - [Internal] Transfer oob to client buffer
1126 * @chip: nand chip structure
1127 * @oob: oob destination address
1128 * @ops: oob ops structure
1129 * @len: size of oob to transfer
1130 */
1131 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1132 struct mtd_oob_ops *ops, size_t len)
1133 {
1134 switch(ops->mode) {
1135
1136 case MTD_OOB_PLACE:
1137 case MTD_OOB_RAW:
1138 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1139 return oob + len;
1140
1141 case MTD_OOB_AUTO: {
1142 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1143 uint32_t boffs = 0, roffs = ops->ooboffs;
1144 size_t bytes = 0;
1145
1146 for(; free->length && len; free++, len -= bytes) {
1147 /* Read request not from offset 0 ? */
1148 if (unlikely(roffs)) {
1149 if (roffs >= free->length) {
1150 roffs -= free->length;
1151 continue;
1152 }
1153 boffs = free->offset + roffs;
1154 bytes = min_t(size_t, len,
1155 (free->length - roffs));
1156 roffs = 0;
1157 } else {
1158 bytes = min_t(size_t, len, free->length);
1159 boffs = free->offset;
1160 }
1161 memcpy(oob, chip->oob_poi + boffs, bytes);
1162 oob += bytes;
1163 }
1164 return oob;
1165 }
1166 default:
1167 BUG();
1168 }
1169 return NULL;
1170 }
1171
1172 /**
1173 * nand_do_read_ops - [Internal] Read data with ECC
1174 *
1175 * @mtd: MTD device structure
1176 * @from: offset to read from
1177 * @ops: oob ops structure
1178 *
1179 * Internal function. Called with chip held.
1180 */
1181 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1182 struct mtd_oob_ops *ops)
1183 {
1184 int chipnr, page, realpage, col, bytes, aligned;
1185 struct nand_chip *chip = mtd->priv;
1186 struct mtd_ecc_stats stats;
1187 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1188 int sndcmd = 1;
1189 int ret = 0;
1190 uint32_t readlen = ops->len;
1191 uint32_t oobreadlen = ops->ooblen;
1192 uint8_t *bufpoi, *oob, *buf;
1193
1194 stats = mtd->ecc_stats;
1195
1196 chipnr = (int)(from >> chip->chip_shift);
1197 chip->select_chip(mtd, chipnr);
1198
1199 realpage = (int)(from >> chip->page_shift);
1200 page = realpage & chip->pagemask;
1201
1202 col = (int)(from & (mtd->writesize - 1));
1203
1204 buf = ops->datbuf;
1205 oob = ops->oobbuf;
1206
1207 while(1) {
1208 bytes = min(mtd->writesize - col, readlen);
1209 aligned = (bytes == mtd->writesize);
1210
1211 /* Is the current page in the buffer ? */
1212 if (realpage != chip->pagebuf || oob) {
1213 bufpoi = aligned ? buf : chip->buffers->databuf;
1214
1215 if (likely(sndcmd)) {
1216 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1217 sndcmd = 0;
1218 }
1219
1220 /* Now read the page into the buffer */
1221 if (unlikely(ops->mode == MTD_OOB_RAW))
1222 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi);
1223 else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
1224 ret = chip->ecc.read_subpage(mtd, chip, col, bytes, bufpoi);
1225 else
1226 ret = chip->ecc.read_page(mtd, chip, bufpoi);
1227 if (ret < 0)
1228 break;
1229
1230 /* Transfer not aligned data */
1231 if (!aligned) {
1232 if (!NAND_SUBPAGE_READ(chip) && !oob)
1233 chip->pagebuf = realpage;
1234 memcpy(buf, chip->buffers->databuf + col, bytes);
1235 }
1236
1237 buf += bytes;
1238
1239 if (unlikely(oob)) {
1240 /* Raw mode does data:oob:data:oob */
1241 if (ops->mode != MTD_OOB_RAW) {
1242 int toread = min(oobreadlen,
1243 chip->ecc.layout->oobavail);
1244 if (toread) {
1245 oob = nand_transfer_oob(chip,
1246 oob, ops, toread);
1247 oobreadlen -= toread;
1248 }
1249 } else
1250 buf = nand_transfer_oob(chip,
1251 buf, ops, mtd->oobsize);
1252 }
1253
1254 if (!(chip->options & NAND_NO_READRDY)) {
1255 /*
1256 * Apply delay or wait for ready/busy pin. Do
1257 * this before the AUTOINCR check, so no
1258 * problems arise if a chip which does auto
1259 * increment is marked as NOAUTOINCR by the
1260 * board driver.
1261 */
1262 if (!chip->dev_ready)
1263 udelay(chip->chip_delay);
1264 else
1265 nand_wait_ready(mtd);
1266 }
1267 } else {
1268 memcpy(buf, chip->buffers->databuf + col, bytes);
1269 buf += bytes;
1270 }
1271
1272 readlen -= bytes;
1273
1274 if (!readlen)
1275 break;
1276
1277 /* For subsequent reads align to page boundary. */
1278 col = 0;
1279 /* Increment page address */
1280 realpage++;
1281
1282 page = realpage & chip->pagemask;
1283 /* Check, if we cross a chip boundary */
1284 if (!page) {
1285 chipnr++;
1286 chip->select_chip(mtd, -1);
1287 chip->select_chip(mtd, chipnr);
1288 }
1289
1290 /* Check, if the chip supports auto page increment
1291 * or if we have hit a block boundary.
1292 */
1293 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1294 sndcmd = 1;
1295 }
1296
1297 ops->retlen = ops->len - (size_t) readlen;
1298 if (oob)
1299 ops->oobretlen = ops->ooblen - oobreadlen;
1300
1301 if (ret)
1302 return ret;
1303
1304 if (mtd->ecc_stats.failed - stats.failed)
1305 return -EBADMSG;
1306
1307 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1308 }
1309
1310 /**
1311 * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
1312 * @mtd: MTD device structure
1313 * @from: offset to read from
1314 * @len: number of bytes to read
1315 * @retlen: pointer to variable to store the number of read bytes
1316 * @buf: the databuffer to put data
1317 *
1318 * Get hold of the chip and call nand_do_read
1319 */
1320 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1321 size_t *retlen, uint8_t *buf)
1322 {
1323 struct nand_chip *chip = mtd->priv;
1324 int ret;
1325
1326 /* Do not allow reads past end of device */
1327 if ((from + len) > mtd->size)
1328 return -EINVAL;
1329 if (!len)
1330 return 0;
1331
1332 nand_get_device(chip, mtd, FL_READING);
1333
1334 chip->ops.len = len;
1335 chip->ops.datbuf = buf;
1336 chip->ops.oobbuf = NULL;
1337
1338 ret = nand_do_read_ops(mtd, from, &chip->ops);
1339
1340 *retlen = chip->ops.retlen;
1341
1342 nand_release_device(mtd);
1343
1344 return ret;
1345 }
1346
1347 /**
1348 * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1349 * @mtd: mtd info structure
1350 * @chip: nand chip info structure
1351 * @page: page number to read
1352 * @sndcmd: flag whether to issue read command or not
1353 */
1354 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1355 int page, int sndcmd)
1356 {
1357 if (sndcmd) {
1358 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1359 sndcmd = 0;
1360 }
1361 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1362 return sndcmd;
1363 }
1364
1365 /**
1366 * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1367 * with syndromes
1368 * @mtd: mtd info structure
1369 * @chip: nand chip info structure
1370 * @page: page number to read
1371 * @sndcmd: flag whether to issue read command or not
1372 */
1373 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1374 int page, int sndcmd)
1375 {
1376 uint8_t *buf = chip->oob_poi;
1377 int length = mtd->oobsize;
1378 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1379 int eccsize = chip->ecc.size;
1380 uint8_t *bufpoi = buf;
1381 int i, toread, sndrnd = 0, pos;
1382
1383 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1384 for (i = 0; i < chip->ecc.steps; i++) {
1385 if (sndrnd) {
1386 pos = eccsize + i * (eccsize + chunk);
1387 if (mtd->writesize > 512)
1388 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1389 else
1390 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1391 } else
1392 sndrnd = 1;
1393 toread = min_t(int, length, chunk);
1394 chip->read_buf(mtd, bufpoi, toread);
1395 bufpoi += toread;
1396 length -= toread;
1397 }
1398 if (length > 0)
1399 chip->read_buf(mtd, bufpoi, length);
1400
1401 return 1;
1402 }
1403
1404 /**
1405 * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1406 * @mtd: mtd info structure
1407 * @chip: nand chip info structure
1408 * @page: page number to write
1409 */
1410 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1411 int page)
1412 {
1413 int status = 0;
1414 const uint8_t *buf = chip->oob_poi;
1415 int length = mtd->oobsize;
1416
1417 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1418 chip->write_buf(mtd, buf, length);
1419 /* Send command to program the OOB data */
1420 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1421
1422 status = chip->waitfunc(mtd, chip);
1423
1424 return status & NAND_STATUS_FAIL ? -EIO : 0;
1425 }
1426
1427 /**
1428 * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1429 * with syndrome - only for large page flash !
1430 * @mtd: mtd info structure
1431 * @chip: nand chip info structure
1432 * @page: page number to write
1433 */
1434 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1435 struct nand_chip *chip, int page)
1436 {
1437 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1438 int eccsize = chip->ecc.size, length = mtd->oobsize;
1439 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1440 const uint8_t *bufpoi = chip->oob_poi;
1441
1442 /*
1443 * data-ecc-data-ecc ... ecc-oob
1444 * or
1445 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1446 */
1447 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1448 pos = steps * (eccsize + chunk);
1449 steps = 0;
1450 } else
1451 pos = eccsize;
1452
1453 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1454 for (i = 0; i < steps; i++) {
1455 if (sndcmd) {
1456 if (mtd->writesize <= 512) {
1457 uint32_t fill = 0xFFFFFFFF;
1458
1459 len = eccsize;
1460 while (len > 0) {
1461 int num = min_t(int, len, 4);
1462 chip->write_buf(mtd, (uint8_t *)&fill,
1463 num);
1464 len -= num;
1465 }
1466 } else {
1467 pos = eccsize + i * (eccsize + chunk);
1468 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1469 }
1470 } else
1471 sndcmd = 1;
1472 len = min_t(int, length, chunk);
1473 chip->write_buf(mtd, bufpoi, len);
1474 bufpoi += len;
1475 length -= len;
1476 }
1477 if (length > 0)
1478 chip->write_buf(mtd, bufpoi, length);
1479
1480 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1481 status = chip->waitfunc(mtd, chip);
1482
1483 return status & NAND_STATUS_FAIL ? -EIO : 0;
1484 }
1485
1486 /**
1487 * nand_do_read_oob - [Intern] NAND read out-of-band
1488 * @mtd: MTD device structure
1489 * @from: offset to read from
1490 * @ops: oob operations description structure
1491 *
1492 * NAND read out-of-band data from the spare area
1493 */
1494 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1495 struct mtd_oob_ops *ops)
1496 {
1497 int page, realpage, chipnr, sndcmd = 1;
1498 struct nand_chip *chip = mtd->priv;
1499 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1500 int readlen = ops->ooblen;
1501 int len;
1502 uint8_t *buf = ops->oobbuf;
1503
1504 MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08Lx, len = %i\n",
1505 (unsigned long long)from, readlen);
1506
1507 if (ops->mode == MTD_OOB_AUTO)
1508 len = chip->ecc.layout->oobavail;
1509 else
1510 len = mtd->oobsize;
1511
1512 if (unlikely(ops->ooboffs >= len)) {
1513 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1514 "Attempt to start read outside oob\n");
1515 return -EINVAL;
1516 }
1517
1518 /* Do not allow reads past end of device */
1519 if (unlikely(from >= mtd->size ||
1520 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1521 (from >> chip->page_shift)) * len)) {
1522 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1523 "Attempt read beyond end of device\n");
1524 return -EINVAL;
1525 }
1526
1527 chipnr = (int)(from >> chip->chip_shift);
1528 chip->select_chip(mtd, chipnr);
1529
1530 /* Shift to get page */
1531 realpage = (int)(from >> chip->page_shift);
1532 page = realpage & chip->pagemask;
1533
1534 while(1) {
1535 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1536
1537 len = min(len, readlen);
1538 buf = nand_transfer_oob(chip, buf, ops, len);
1539
1540 if (!(chip->options & NAND_NO_READRDY)) {
1541 /*
1542 * Apply delay or wait for ready/busy pin. Do this
1543 * before the AUTOINCR check, so no problems arise if a
1544 * chip which does auto increment is marked as
1545 * NOAUTOINCR by the board driver.
1546 */
1547 if (!chip->dev_ready)
1548 udelay(chip->chip_delay);
1549 else
1550 nand_wait_ready(mtd);
1551 }
1552
1553 readlen -= len;
1554 if (!readlen)
1555 break;
1556
1557 /* Increment page address */
1558 realpage++;
1559
1560 page = realpage & chip->pagemask;
1561 /* Check, if we cross a chip boundary */
1562 if (!page) {
1563 chipnr++;
1564 chip->select_chip(mtd, -1);
1565 chip->select_chip(mtd, chipnr);
1566 }
1567
1568 /* Check, if the chip supports auto page increment
1569 * or if we have hit a block boundary.
1570 */
1571 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1572 sndcmd = 1;
1573 }
1574
1575 ops->oobretlen = ops->ooblen;
1576 return 0;
1577 }
1578
1579 /**
1580 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1581 * @mtd: MTD device structure
1582 * @from: offset to read from
1583 * @ops: oob operation description structure
1584 *
1585 * NAND read data and/or out-of-band data
1586 */
1587 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1588 struct mtd_oob_ops *ops)
1589 {
1590 struct nand_chip *chip = mtd->priv;
1591 int ret = -ENOTSUPP;
1592
1593 ops->retlen = 0;
1594
1595 /* Do not allow reads past end of device */
1596 if (ops->datbuf && (from + ops->len) > mtd->size) {
1597 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1598 "Attempt read beyond end of device\n");
1599 return -EINVAL;
1600 }
1601
1602 nand_get_device(chip, mtd, FL_READING);
1603
1604 switch(ops->mode) {
1605 case MTD_OOB_PLACE:
1606 case MTD_OOB_AUTO:
1607 case MTD_OOB_RAW:
1608 break;
1609
1610 default:
1611 goto out;
1612 }
1613
1614 if (!ops->datbuf)
1615 ret = nand_do_read_oob(mtd, from, ops);
1616 else
1617 ret = nand_do_read_ops(mtd, from, ops);
1618
1619 out:
1620 nand_release_device(mtd);
1621 return ret;
1622 }
1623
1624
1625 /**
1626 * nand_write_page_raw - [Intern] raw page write function
1627 * @mtd: mtd info structure
1628 * @chip: nand chip info structure
1629 * @buf: data buffer
1630 */
1631 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1632 const uint8_t *buf)
1633 {
1634 chip->write_buf(mtd, buf, mtd->writesize);
1635 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1636 }
1637
1638 /**
1639 * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
1640 * @mtd: mtd info structure
1641 * @chip: nand chip info structure
1642 * @buf: data buffer
1643 */
1644 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1645 const uint8_t *buf)
1646 {
1647 int i, eccsize = chip->ecc.size;
1648 int eccbytes = chip->ecc.bytes;
1649 int eccsteps = chip->ecc.steps;
1650 uint8_t *ecc_calc = chip->buffers->ecccalc;
1651 const uint8_t *p = buf;
1652 uint32_t *eccpos = chip->ecc.layout->eccpos;
1653
1654 /* Software ecc calculation */
1655 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1656 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1657
1658 for (i = 0; i < chip->ecc.total; i++)
1659 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1660
1661 chip->ecc.write_page_raw(mtd, chip, buf);
1662 }
1663
1664 /**
1665 * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
1666 * @mtd: mtd info structure
1667 * @chip: nand chip info structure
1668 * @buf: data buffer
1669 */
1670 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1671 const uint8_t *buf)
1672 {
1673 int i, eccsize = chip->ecc.size;
1674 int eccbytes = chip->ecc.bytes;
1675 int eccsteps = chip->ecc.steps;
1676 uint8_t *ecc_calc = chip->buffers->ecccalc;
1677 const uint8_t *p = buf;
1678 uint32_t *eccpos = chip->ecc.layout->eccpos;
1679
1680 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1681 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1682 chip->write_buf(mtd, p, eccsize);
1683 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1684 }
1685
1686 for (i = 0; i < chip->ecc.total; i++)
1687 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1688
1689 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1690 }
1691
1692 /**
1693 * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
1694 * @mtd: mtd info structure
1695 * @chip: nand chip info structure
1696 * @buf: data buffer
1697 *
1698 * The hw generator calculates the error syndrome automatically. Therefor
1699 * we need a special oob layout and handling.
1700 */
1701 static void nand_write_page_syndrome(struct mtd_info *mtd,
1702 struct nand_chip *chip, const uint8_t *buf)
1703 {
1704 int i, eccsize = chip->ecc.size;
1705 int eccbytes = chip->ecc.bytes;
1706 int eccsteps = chip->ecc.steps;
1707 const uint8_t *p = buf;
1708 uint8_t *oob = chip->oob_poi;
1709
1710 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1711
1712 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1713 chip->write_buf(mtd, p, eccsize);
1714
1715 if (chip->ecc.prepad) {
1716 chip->write_buf(mtd, oob, chip->ecc.prepad);
1717 oob += chip->ecc.prepad;
1718 }
1719
1720 chip->ecc.calculate(mtd, p, oob);
1721 chip->write_buf(mtd, oob, eccbytes);
1722 oob += eccbytes;
1723
1724 if (chip->ecc.postpad) {
1725 chip->write_buf(mtd, oob, chip->ecc.postpad);
1726 oob += chip->ecc.postpad;
1727 }
1728 }
1729
1730 /* Calculate remaining oob bytes */
1731 i = mtd->oobsize - (oob - chip->oob_poi);
1732 if (i)
1733 chip->write_buf(mtd, oob, i);
1734 }
1735
1736 /**
1737 * nand_write_page - [REPLACEABLE] write one page
1738 * @mtd: MTD device structure
1739 * @chip: NAND chip descriptor
1740 * @buf: the data to write
1741 * @page: page number to write
1742 * @cached: cached programming
1743 * @raw: use _raw version of write_page
1744 */
1745 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1746 const uint8_t *buf, int page, int cached, int raw)
1747 {
1748 int status;
1749
1750 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1751
1752 if (unlikely(raw))
1753 chip->ecc.write_page_raw(mtd, chip, buf);
1754 else
1755 chip->ecc.write_page(mtd, chip, buf);
1756
1757 /*
1758 * Cached progamming disabled for now, Not sure if its worth the
1759 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
1760 */
1761 cached = 0;
1762
1763 if (!cached || !(chip->options & NAND_CACHEPRG)) {
1764
1765 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1766 status = chip->waitfunc(mtd, chip);
1767 /*
1768 * See if operation failed and additional status checks are
1769 * available
1770 */
1771 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1772 status = chip->errstat(mtd, chip, FL_WRITING, status,
1773 page);
1774
1775 if (status & NAND_STATUS_FAIL)
1776 return -EIO;
1777 } else {
1778 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
1779 status = chip->waitfunc(mtd, chip);
1780 }
1781
1782 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1783 /* Send command to read back the data */
1784 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1785
1786 if (chip->verify_buf(mtd, buf, mtd->writesize))
1787 return -EIO;
1788 #endif
1789 return 0;
1790 }
1791
1792 /**
1793 * nand_fill_oob - [Internal] Transfer client buffer to oob
1794 * @chip: nand chip structure
1795 * @oob: oob data buffer
1796 * @ops: oob ops structure
1797 */
1798 static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob,
1799 struct mtd_oob_ops *ops)
1800 {
1801 size_t len = ops->ooblen;
1802
1803 switch(ops->mode) {
1804
1805 case MTD_OOB_PLACE:
1806 case MTD_OOB_RAW:
1807 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
1808 return oob + len;
1809
1810 case MTD_OOB_AUTO: {
1811 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1812 uint32_t boffs = 0, woffs = ops->ooboffs;
1813 size_t bytes = 0;
1814
1815 for(; free->length && len; free++, len -= bytes) {
1816 /* Write request not from offset 0 ? */
1817 if (unlikely(woffs)) {
1818 if (woffs >= free->length) {
1819 woffs -= free->length;
1820 continue;
1821 }
1822 boffs = free->offset + woffs;
1823 bytes = min_t(size_t, len,
1824 (free->length - woffs));
1825 woffs = 0;
1826 } else {
1827 bytes = min_t(size_t, len, free->length);
1828 boffs = free->offset;
1829 }
1830 memcpy(chip->oob_poi + boffs, oob, bytes);
1831 oob += bytes;
1832 }
1833 return oob;
1834 }
1835 default:
1836 BUG();
1837 }
1838 return NULL;
1839 }
1840
1841 #define NOTALIGNED(x) (x & (chip->subpagesize - 1)) != 0
1842
1843 /**
1844 * nand_do_write_ops - [Internal] NAND write with ECC
1845 * @mtd: MTD device structure
1846 * @to: offset to write to
1847 * @ops: oob operations description structure
1848 *
1849 * NAND write with ECC
1850 */
1851 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
1852 struct mtd_oob_ops *ops)
1853 {
1854 int chipnr, realpage, page, blockmask, column;
1855 struct nand_chip *chip = mtd->priv;
1856 uint32_t writelen = ops->len;
1857 uint8_t *oob = ops->oobbuf;
1858 uint8_t *buf = ops->datbuf;
1859 int ret, subpage;
1860
1861 ops->retlen = 0;
1862 if (!writelen)
1863 return 0;
1864
1865 /* reject writes, which are not page aligned */
1866 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
1867 printk(KERN_NOTICE "nand_write: "
1868 "Attempt to write not page aligned data\n");
1869 return -EINVAL;
1870 }
1871
1872 column = to & (mtd->writesize - 1);
1873 subpage = column || (writelen & (mtd->writesize - 1));
1874
1875 if (subpage && oob)
1876 return -EINVAL;
1877
1878 chipnr = (int)(to >> chip->chip_shift);
1879 chip->select_chip(mtd, chipnr);
1880
1881 /* Check, if it is write protected */
1882 if (nand_check_wp(mtd)) {
1883 printk (KERN_NOTICE "nand_do_write_ops: Device is write protected\n");
1884 return -EIO;
1885 }
1886
1887 realpage = (int)(to >> chip->page_shift);
1888 page = realpage & chip->pagemask;
1889 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1890
1891 /* Invalidate the page cache, when we write to the cached page */
1892 if (to <= (chip->pagebuf << chip->page_shift) &&
1893 (chip->pagebuf << chip->page_shift) < (to + ops->len))
1894 chip->pagebuf = -1;
1895
1896 /* If we're not given explicit OOB data, let it be 0xFF */
1897 if (likely(!oob))
1898 memset(chip->oob_poi, 0xff, mtd->oobsize);
1899
1900 while(1) {
1901 int bytes = mtd->writesize;
1902 int cached = writelen > bytes && page != blockmask;
1903 uint8_t *wbuf = buf;
1904
1905 /* Partial page write ? */
1906 if (unlikely(column || writelen < (mtd->writesize - 1))) {
1907 cached = 0;
1908 bytes = min_t(int, bytes - column, (int) writelen);
1909 chip->pagebuf = -1;
1910 memset(chip->buffers->databuf, 0xff, mtd->writesize);
1911 memcpy(&chip->buffers->databuf[column], buf, bytes);
1912 wbuf = chip->buffers->databuf;
1913 }
1914
1915 if (unlikely(oob))
1916 oob = nand_fill_oob(chip, oob, ops);
1917
1918 ret = chip->write_page(mtd, chip, wbuf, page, cached,
1919 (ops->mode == MTD_OOB_RAW));
1920 if (ret)
1921 break;
1922
1923 writelen -= bytes;
1924 if (!writelen)
1925 break;
1926
1927 column = 0;
1928 buf += bytes;
1929 realpage++;
1930
1931 page = realpage & chip->pagemask;
1932 /* Check, if we cross a chip boundary */
1933 if (!page) {
1934 chipnr++;
1935 chip->select_chip(mtd, -1);
1936 chip->select_chip(mtd, chipnr);
1937 }
1938 }
1939
1940 ops->retlen = ops->len - writelen;
1941 if (unlikely(oob))
1942 ops->oobretlen = ops->ooblen;
1943 return ret;
1944 }
1945
1946 /**
1947 * nand_write - [MTD Interface] NAND write with ECC
1948 * @mtd: MTD device structure
1949 * @to: offset to write to
1950 * @len: number of bytes to write
1951 * @retlen: pointer to variable to store the number of written bytes
1952 * @buf: the data to write
1953 *
1954 * NAND write with ECC
1955 */
1956 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
1957 size_t *retlen, const uint8_t *buf)
1958 {
1959 struct nand_chip *chip = mtd->priv;
1960 int ret;
1961
1962 /* Do not allow reads past end of device */
1963 if ((to + len) > mtd->size)
1964 return -EINVAL;
1965 if (!len)
1966 return 0;
1967
1968 nand_get_device(chip, mtd, FL_WRITING);
1969
1970 chip->ops.len = len;
1971 chip->ops.datbuf = (uint8_t *)buf;
1972 chip->ops.oobbuf = NULL;
1973
1974 ret = nand_do_write_ops(mtd, to, &chip->ops);
1975
1976 *retlen = chip->ops.retlen;
1977
1978 nand_release_device(mtd);
1979
1980 return ret;
1981 }
1982
1983 /**
1984 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
1985 * @mtd: MTD device structure
1986 * @to: offset to write to
1987 * @ops: oob operation description structure
1988 *
1989 * NAND write out-of-band
1990 */
1991 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
1992 struct mtd_oob_ops *ops)
1993 {
1994 int chipnr, page, status, len;
1995 struct nand_chip *chip = mtd->priv;
1996
1997 MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n",
1998 (unsigned int)to, (int)ops->ooblen);
1999
2000 if (ops->mode == MTD_OOB_AUTO)
2001 len = chip->ecc.layout->oobavail;
2002 else
2003 len = mtd->oobsize;
2004
2005 /* Do not allow write past end of page */
2006 if ((ops->ooboffs + ops->ooblen) > len) {
2007 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: "
2008 "Attempt to write past end of page\n");
2009 return -EINVAL;
2010 }
2011
2012 if (unlikely(ops->ooboffs >= len)) {
2013 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
2014 "Attempt to start write outside oob\n");
2015 return -EINVAL;
2016 }
2017
2018 /* Do not allow reads past end of device */
2019 if (unlikely(to >= mtd->size ||
2020 ops->ooboffs + ops->ooblen >
2021 ((mtd->size >> chip->page_shift) -
2022 (to >> chip->page_shift)) * len)) {
2023 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
2024 "Attempt write beyond end of device\n");
2025 return -EINVAL;
2026 }
2027
2028 chipnr = (int)(to >> chip->chip_shift);
2029 chip->select_chip(mtd, chipnr);
2030
2031 /* Shift to get page */
2032 page = (int)(to >> chip->page_shift);
2033
2034 /*
2035 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2036 * of my DiskOnChip 2000 test units) will clear the whole data page too
2037 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2038 * it in the doc2000 driver in August 1999. dwmw2.
2039 */
2040 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2041
2042 /* Check, if it is write protected */
2043 if (nand_check_wp(mtd))
2044 return -EROFS;
2045
2046 /* Invalidate the page cache, if we write to the cached page */
2047 if (page == chip->pagebuf)
2048 chip->pagebuf = -1;
2049
2050 memset(chip->oob_poi, 0xff, mtd->oobsize);
2051 nand_fill_oob(chip, ops->oobbuf, ops);
2052 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2053 memset(chip->oob_poi, 0xff, mtd->oobsize);
2054
2055 if (status)
2056 return status;
2057
2058 ops->oobretlen = ops->ooblen;
2059
2060 return 0;
2061 }
2062
2063 /**
2064 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2065 * @mtd: MTD device structure
2066 * @to: offset to write to
2067 * @ops: oob operation description structure
2068 */
2069 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2070 struct mtd_oob_ops *ops)
2071 {
2072 struct nand_chip *chip = mtd->priv;
2073 int ret = -ENOTSUPP;
2074
2075 ops->retlen = 0;
2076
2077 /* Do not allow writes past end of device */
2078 if (ops->datbuf && (to + ops->len) > mtd->size) {
2079 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
2080 "Attempt read beyond end of device\n");
2081 return -EINVAL;
2082 }
2083
2084 nand_get_device(chip, mtd, FL_WRITING);
2085
2086 switch(ops->mode) {
2087 case MTD_OOB_PLACE:
2088 case MTD_OOB_AUTO:
2089 case MTD_OOB_RAW:
2090 break;
2091
2092 default:
2093 goto out;
2094 }
2095
2096 if (!ops->datbuf)
2097 ret = nand_do_write_oob(mtd, to, ops);
2098 else
2099 ret = nand_do_write_ops(mtd, to, ops);
2100
2101 out:
2102 nand_release_device(mtd);
2103 return ret;
2104 }
2105
2106 /**
2107 * single_erease_cmd - [GENERIC] NAND standard block erase command function
2108 * @mtd: MTD device structure
2109 * @page: the page address of the block which will be erased
2110 *
2111 * Standard erase command for NAND chips
2112 */
2113 static void single_erase_cmd(struct mtd_info *mtd, int page)
2114 {
2115 struct nand_chip *chip = mtd->priv;
2116 /* Send commands to erase a block */
2117 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2118 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2119 }
2120
2121 /**
2122 * multi_erease_cmd - [GENERIC] AND specific block erase command function
2123 * @mtd: MTD device structure
2124 * @page: the page address of the block which will be erased
2125 *
2126 * AND multi block erase command function
2127 * Erase 4 consecutive blocks
2128 */
2129 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2130 {
2131 struct nand_chip *chip = mtd->priv;
2132 /* Send commands to erase a block */
2133 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2134 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2135 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2136 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2137 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2138 }
2139
2140 /**
2141 * nand_erase - [MTD Interface] erase block(s)
2142 * @mtd: MTD device structure
2143 * @instr: erase instruction
2144 *
2145 * Erase one ore more blocks
2146 */
2147 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2148 {
2149 return nand_erase_nand(mtd, instr, 0);
2150 }
2151
2152 #define BBT_PAGE_MASK 0xffffff3f
2153 /**
2154 * nand_erase_nand - [Internal] erase block(s)
2155 * @mtd: MTD device structure
2156 * @instr: erase instruction
2157 * @allowbbt: allow erasing the bbt area
2158 *
2159 * Erase one ore more blocks
2160 */
2161 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2162 int allowbbt)
2163 {
2164 int page, len, status, pages_per_block, ret, chipnr;
2165 struct nand_chip *chip = mtd->priv;
2166 int rewrite_bbt[CONFIG_SYS_NAND_MAX_CHIPS]={0};
2167 unsigned int bbt_masked_page = 0xffffffff;
2168
2169 MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%08x, len = %i\n",
2170 (unsigned int) instr->addr, (unsigned int) instr->len);
2171
2172 /* Start address must align on block boundary */
2173 if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) {
2174 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n");
2175 return -EINVAL;
2176 }
2177
2178 /* Length must align on block boundary */
2179 if (instr->len & ((1 << chip->phys_erase_shift) - 1)) {
2180 MTDDEBUG (MTD_DEBUG_LEVEL0,
2181 "nand_erase: Length not block aligned\n");
2182 return -EINVAL;
2183 }
2184
2185 /* Do not allow erase past end of device */
2186 if ((instr->len + instr->addr) > mtd->size) {
2187 MTDDEBUG (MTD_DEBUG_LEVEL0,
2188 "nand_erase: Erase past end of device\n");
2189 return -EINVAL;
2190 }
2191
2192 instr->fail_addr = 0xffffffff;
2193
2194 /* Grab the lock and see if the device is available */
2195 nand_get_device(chip, mtd, FL_ERASING);
2196
2197 /* Shift to get first page */
2198 page = (int)(instr->addr >> chip->page_shift);
2199 chipnr = (int)(instr->addr >> chip->chip_shift);
2200
2201 /* Calculate pages in each block */
2202 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2203
2204 /* Select the NAND device */
2205 chip->select_chip(mtd, chipnr);
2206
2207 /* Check, if it is write protected */
2208 if (nand_check_wp(mtd)) {
2209 MTDDEBUG (MTD_DEBUG_LEVEL0,
2210 "nand_erase: Device is write protected!!!\n");
2211 instr->state = MTD_ERASE_FAILED;
2212 goto erase_exit;
2213 }
2214
2215 /*
2216 * If BBT requires refresh, set the BBT page mask to see if the BBT
2217 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2218 * can not be matched. This is also done when the bbt is actually
2219 * erased to avoid recusrsive updates
2220 */
2221 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2222 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2223
2224 /* Loop through the pages */
2225 len = instr->len;
2226
2227 instr->state = MTD_ERASING;
2228
2229 while (len) {
2230 /*
2231 * heck if we have a bad block, we do not erase bad blocks !
2232 */
2233 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2234 chip->page_shift, 0, allowbbt)) {
2235 printk(KERN_WARNING "nand_erase: attempt to erase a "
2236 "bad block at page 0x%08x\n", page);
2237 instr->state = MTD_ERASE_FAILED;
2238 goto erase_exit;
2239 }
2240
2241 /*
2242 * Invalidate the page cache, if we erase the block which
2243 * contains the current cached page
2244 */
2245 if (page <= chip->pagebuf && chip->pagebuf <
2246 (page + pages_per_block))
2247 chip->pagebuf = -1;
2248
2249 chip->erase_cmd(mtd, page & chip->pagemask);
2250
2251 status = chip->waitfunc(mtd, chip);
2252
2253 /*
2254 * See if operation failed and additional status checks are
2255 * available
2256 */
2257 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2258 status = chip->errstat(mtd, chip, FL_ERASING,
2259 status, page);
2260
2261 /* See if block erase succeeded */
2262 if (status & NAND_STATUS_FAIL) {
2263 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: "
2264 "Failed erase, page 0x%08x\n", page);
2265 instr->state = MTD_ERASE_FAILED;
2266 instr->fail_addr = (page << chip->page_shift);
2267 goto erase_exit;
2268 }
2269
2270 /*
2271 * If BBT requires refresh, set the BBT rewrite flag to the
2272 * page being erased
2273 */
2274 if (bbt_masked_page != 0xffffffff &&
2275 (page & BBT_PAGE_MASK) == bbt_masked_page)
2276 rewrite_bbt[chipnr] = (page << chip->page_shift);
2277
2278 /* Increment page address and decrement length */
2279 len -= (1 << chip->phys_erase_shift);
2280 page += pages_per_block;
2281
2282 /* Check, if we cross a chip boundary */
2283 if (len && !(page & chip->pagemask)) {
2284 chipnr++;
2285 chip->select_chip(mtd, -1);
2286 chip->select_chip(mtd, chipnr);
2287
2288 /*
2289 * If BBT requires refresh and BBT-PERCHIP, set the BBT
2290 * page mask to see if this BBT should be rewritten
2291 */
2292 if (bbt_masked_page != 0xffffffff &&
2293 (chip->bbt_td->options & NAND_BBT_PERCHIP))
2294 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2295 BBT_PAGE_MASK;
2296 }
2297 }
2298 instr->state = MTD_ERASE_DONE;
2299
2300 erase_exit:
2301
2302 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2303
2304 /* Deselect and wake up anyone waiting on the device */
2305 nand_release_device(mtd);
2306
2307 /* Do call back function */
2308 if (!ret)
2309 mtd_erase_callback(instr);
2310
2311 /*
2312 * If BBT requires refresh and erase was successful, rewrite any
2313 * selected bad block tables
2314 */
2315 if (bbt_masked_page == 0xffffffff || ret)
2316 return ret;
2317
2318 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2319 if (!rewrite_bbt[chipnr])
2320 continue;
2321 /* update the BBT for chip */
2322 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase_nand: nand_update_bbt "
2323 "(%d:0x%0x 0x%0x)\n", chipnr, rewrite_bbt[chipnr],
2324 chip->bbt_td->pages[chipnr]);
2325 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2326 }
2327
2328 /* Return more or less happy */
2329 return ret;
2330 }
2331
2332 /**
2333 * nand_sync - [MTD Interface] sync
2334 * @mtd: MTD device structure
2335 *
2336 * Sync is actually a wait for chip ready function
2337 */
2338 static void nand_sync(struct mtd_info *mtd)
2339 {
2340 struct nand_chip *chip = mtd->priv;
2341
2342 MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_sync: called\n");
2343
2344 /* Grab the lock and see if the device is available */
2345 nand_get_device(chip, mtd, FL_SYNCING);
2346 /* Release it and go back */
2347 nand_release_device(mtd);
2348 }
2349
2350 /**
2351 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2352 * @mtd: MTD device structure
2353 * @offs: offset relative to mtd start
2354 */
2355 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2356 {
2357 /* Check for invalid offset */
2358 if (offs > mtd->size)
2359 return -EINVAL;
2360
2361 return nand_block_checkbad(mtd, offs, 1, 0);
2362 }
2363
2364 /**
2365 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2366 * @mtd: MTD device structure
2367 * @ofs: offset relative to mtd start
2368 */
2369 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2370 {
2371 struct nand_chip *chip = mtd->priv;
2372 int ret;
2373
2374 if ((ret = nand_block_isbad(mtd, ofs))) {
2375 /* If it was bad already, return success and do nothing. */
2376 if (ret > 0)
2377 return 0;
2378 return ret;
2379 }
2380
2381 return chip->block_markbad(mtd, ofs);
2382 }
2383
2384 /**
2385 * nand_suspend - [MTD Interface] Suspend the NAND flash
2386 * @mtd: MTD device structure
2387 */
2388 static int nand_suspend(struct mtd_info *mtd)
2389 {
2390 struct nand_chip *chip = mtd->priv;
2391
2392 return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
2393 }
2394
2395 /**
2396 * nand_resume - [MTD Interface] Resume the NAND flash
2397 * @mtd: MTD device structure
2398 */
2399 static void nand_resume(struct mtd_info *mtd)
2400 {
2401 struct nand_chip *chip = mtd->priv;
2402
2403 if (chip->state == FL_PM_SUSPENDED)
2404 nand_release_device(mtd);
2405 else
2406 printk(KERN_ERR "nand_resume() called for a chip which is not "
2407 "in suspended state\n");
2408 }
2409
2410 /*
2411 * Set default functions
2412 */
2413 static void nand_set_defaults(struct nand_chip *chip, int busw)
2414 {
2415 /* check for proper chip_delay setup, set 20us if not */
2416 if (!chip->chip_delay)
2417 chip->chip_delay = 20;
2418
2419 /* check, if a user supplied command function given */
2420 if (chip->cmdfunc == NULL)
2421 chip->cmdfunc = nand_command;
2422
2423 /* check, if a user supplied wait function given */
2424 if (chip->waitfunc == NULL)
2425 chip->waitfunc = nand_wait;
2426
2427 if (!chip->select_chip)
2428 chip->select_chip = nand_select_chip;
2429 if (!chip->read_byte)
2430 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2431 if (!chip->read_word)
2432 chip->read_word = nand_read_word;
2433 if (!chip->block_bad)
2434 chip->block_bad = nand_block_bad;
2435 if (!chip->block_markbad)
2436 chip->block_markbad = nand_default_block_markbad;
2437 if (!chip->write_buf)
2438 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2439 if (!chip->read_buf)
2440 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2441 if (!chip->verify_buf)
2442 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2443 if (!chip->scan_bbt)
2444 chip->scan_bbt = nand_default_bbt;
2445
2446 if (!chip->controller) {
2447 chip->controller = &chip->hwcontrol;
2448
2449 /* XXX U-BOOT XXX */
2450 #if 0
2451 spin_lock_init(&chip->controller->lock);
2452 init_waitqueue_head(&chip->controller->wq);
2453 #endif
2454 }
2455
2456 }
2457
2458 /*
2459 * Get the flash and manufacturer id and lookup if the type is supported
2460 */
2461 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2462 struct nand_chip *chip,
2463 int busw, int *maf_id)
2464 {
2465 struct nand_flash_dev *type = NULL;
2466 int i, dev_id, maf_idx;
2467 int tmp_id, tmp_manf;
2468
2469 /* Select the device */
2470 chip->select_chip(mtd, 0);
2471
2472 /*
2473 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2474 * after power-up
2475 */
2476 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2477
2478 /* Send the command for reading device ID */
2479 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2480
2481 /* Read manufacturer and device IDs */
2482 *maf_id = chip->read_byte(mtd);
2483 dev_id = chip->read_byte(mtd);
2484
2485 /* Try again to make sure, as some systems the bus-hold or other
2486 * interface concerns can cause random data which looks like a
2487 * possibly credible NAND flash to appear. If the two results do
2488 * not match, ignore the device completely.
2489 */
2490
2491 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2492
2493 /* Read manufacturer and device IDs */
2494
2495 tmp_manf = chip->read_byte(mtd);
2496 tmp_id = chip->read_byte(mtd);
2497
2498 if (tmp_manf != *maf_id || tmp_id != dev_id) {
2499 printk(KERN_INFO "%s: second ID read did not match "
2500 "%02x,%02x against %02x,%02x\n", __func__,
2501 *maf_id, dev_id, tmp_manf, tmp_id);
2502 return ERR_PTR(-ENODEV);
2503 }
2504
2505 /* Lookup the flash id */
2506 for (i = 0; nand_flash_ids[i].name != NULL; i++) {
2507 if (dev_id == nand_flash_ids[i].id) {
2508 type = &nand_flash_ids[i];
2509 break;
2510 }
2511 }
2512
2513 if (!type)
2514 return ERR_PTR(-ENODEV);
2515
2516 if (!mtd->name)
2517 mtd->name = type->name;
2518
2519 chip->chipsize = type->chipsize << 20;
2520
2521 /* Newer devices have all the information in additional id bytes */
2522 if (!type->pagesize) {
2523 int extid;
2524 /* The 3rd id byte holds MLC / multichip data */
2525 chip->cellinfo = chip->read_byte(mtd);
2526 /* The 4th id byte is the important one */
2527 extid = chip->read_byte(mtd);
2528 /* Calc pagesize */
2529 mtd->writesize = 1024 << (extid & 0x3);
2530 extid >>= 2;
2531 /* Calc oobsize */
2532 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
2533 extid >>= 2;
2534 /* Calc blocksize. Blocksize is multiples of 64KiB */
2535 mtd->erasesize = (64 * 1024) << (extid & 0x03);
2536 extid >>= 2;
2537 /* Get buswidth information */
2538 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
2539
2540 } else {
2541 /*
2542 * Old devices have chip data hardcoded in the device id table
2543 */
2544 mtd->erasesize = type->erasesize;
2545 mtd->writesize = type->pagesize;
2546 mtd->oobsize = mtd->writesize / 32;
2547 busw = type->options & NAND_BUSWIDTH_16;
2548 }
2549
2550 /* Try to identify manufacturer */
2551 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
2552 if (nand_manuf_ids[maf_idx].id == *maf_id)
2553 break;
2554 }
2555
2556 /*
2557 * Check, if buswidth is correct. Hardware drivers should set
2558 * chip correct !
2559 */
2560 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
2561 printk(KERN_INFO "NAND device: Manufacturer ID:"
2562 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2563 dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2564 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
2565 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
2566 busw ? 16 : 8);
2567 return ERR_PTR(-EINVAL);
2568 }
2569
2570 /* Calculate the address shift from the page size */
2571 chip->page_shift = ffs(mtd->writesize) - 1;
2572 /* Convert chipsize to number of pages per chip -1. */
2573 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2574
2575 chip->bbt_erase_shift = chip->phys_erase_shift =
2576 ffs(mtd->erasesize) - 1;
2577 chip->chip_shift = ffs(chip->chipsize) - 1;
2578
2579 /* Set the bad block position */
2580 chip->badblockpos = mtd->writesize > 512 ?
2581 NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
2582
2583 /* Get chip options, preserve non chip based options */
2584 chip->options &= ~NAND_CHIPOPTIONS_MSK;
2585 chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
2586
2587 /*
2588 * Set chip as a default. Board drivers can override it, if necessary
2589 */
2590 chip->options |= NAND_NO_AUTOINCR;
2591
2592 /* Check if chip is a not a samsung device. Do not clear the
2593 * options for chips which are not having an extended id.
2594 */
2595 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
2596 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
2597
2598 /* Check for AND chips with 4 page planes */
2599 if (chip->options & NAND_4PAGE_ARRAY)
2600 chip->erase_cmd = multi_erase_cmd;
2601 else
2602 chip->erase_cmd = single_erase_cmd;
2603
2604 /* Do not replace user supplied command function ! */
2605 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
2606 chip->cmdfunc = nand_command_lp;
2607
2608 MTDDEBUG (MTD_DEBUG_LEVEL0, "NAND device: Manufacturer ID:"
2609 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id,
2610 nand_manuf_ids[maf_idx].name, type->name);
2611
2612 return type;
2613 }
2614
2615 /**
2616 * nand_scan_ident - [NAND Interface] Scan for the NAND device
2617 * @mtd: MTD device structure
2618 * @maxchips: Number of chips to scan for
2619 *
2620 * This is the first phase of the normal nand_scan() function. It
2621 * reads the flash ID and sets up MTD fields accordingly.
2622 *
2623 * The mtd->owner field must be set to the module of the caller.
2624 */
2625 int nand_scan_ident(struct mtd_info *mtd, int maxchips)
2626 {
2627 int i, busw, nand_maf_id;
2628 struct nand_chip *chip = mtd->priv;
2629 struct nand_flash_dev *type;
2630
2631 /* Get buswidth to select the correct functions */
2632 busw = chip->options & NAND_BUSWIDTH_16;
2633 /* Set the default functions */
2634 nand_set_defaults(chip, busw);
2635
2636 /* Read the flash type */
2637 type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id);
2638
2639 if (IS_ERR(type)) {
2640 #ifndef CONFIG_SYS_NAND_QUIET_TEST
2641 printk(KERN_WARNING "No NAND device found!!!\n");
2642 #endif
2643 chip->select_chip(mtd, -1);
2644 return PTR_ERR(type);
2645 }
2646
2647 /* Check for a chip array */
2648 for (i = 1; i < maxchips; i++) {
2649 chip->select_chip(mtd, i);
2650 /* See comment in nand_get_flash_type for reset */
2651 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2652 /* Send the command for reading device ID */
2653 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2654 /* Read manufacturer and device IDs */
2655 if (nand_maf_id != chip->read_byte(mtd) ||
2656 type->id != chip->read_byte(mtd))
2657 break;
2658 }
2659 #ifdef DEBUG
2660 if (i > 1)
2661 printk(KERN_INFO "%d NAND chips detected\n", i);
2662 #endif
2663
2664 /* Store the number of chips and calc total size for mtd */
2665 chip->numchips = i;
2666 mtd->size = i * chip->chipsize;
2667
2668 return 0;
2669 }
2670
2671
2672 /**
2673 * nand_scan_tail - [NAND Interface] Scan for the NAND device
2674 * @mtd: MTD device structure
2675 * @maxchips: Number of chips to scan for
2676 *
2677 * This is the second phase of the normal nand_scan() function. It
2678 * fills out all the uninitialized function pointers with the defaults
2679 * and scans for a bad block table if appropriate.
2680 */
2681 int nand_scan_tail(struct mtd_info *mtd)
2682 {
2683 int i;
2684 struct nand_chip *chip = mtd->priv;
2685
2686 if (!(chip->options & NAND_OWN_BUFFERS))
2687 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
2688 if (!chip->buffers)
2689 return -ENOMEM;
2690
2691 /* Set the internal oob buffer location, just after the page data */
2692 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
2693
2694 /*
2695 * If no default placement scheme is given, select an appropriate one
2696 */
2697 if (!chip->ecc.layout) {
2698 switch (mtd->oobsize) {
2699 case 8:
2700 chip->ecc.layout = &nand_oob_8;
2701 break;
2702 case 16:
2703 chip->ecc.layout = &nand_oob_16;
2704 break;
2705 case 64:
2706 chip->ecc.layout = &nand_oob_64;
2707 break;
2708 case 128:
2709 chip->ecc.layout = &nand_oob_128;
2710 break;
2711 default:
2712 printk(KERN_WARNING "No oob scheme defined for "
2713 "oobsize %d\n", mtd->oobsize);
2714 /* BUG(); */
2715 }
2716 }
2717
2718 if (!chip->write_page)
2719 chip->write_page = nand_write_page;
2720
2721 /*
2722 * check ECC mode, default to software if 3byte/512byte hardware ECC is
2723 * selected and we have 256 byte pagesize fallback to software ECC
2724 */
2725 if (!chip->ecc.read_page_raw)
2726 chip->ecc.read_page_raw = nand_read_page_raw;
2727 if (!chip->ecc.write_page_raw)
2728 chip->ecc.write_page_raw = nand_write_page_raw;
2729
2730 switch (chip->ecc.mode) {
2731 case NAND_ECC_HW:
2732 /* Use standard hwecc read page function ? */
2733 if (!chip->ecc.read_page)
2734 chip->ecc.read_page = nand_read_page_hwecc;
2735 if (!chip->ecc.write_page)
2736 chip->ecc.write_page = nand_write_page_hwecc;
2737 if (!chip->ecc.read_oob)
2738 chip->ecc.read_oob = nand_read_oob_std;
2739 if (!chip->ecc.write_oob)
2740 chip->ecc.write_oob = nand_write_oob_std;
2741
2742 case NAND_ECC_HW_SYNDROME:
2743 if ((!chip->ecc.calculate || !chip->ecc.correct ||
2744 !chip->ecc.hwctl) &&
2745 (!chip->ecc.read_page ||
2746 chip->ecc.read_page == nand_read_page_hwecc ||
2747 !chip->ecc.write_page ||
2748 chip->ecc.write_page == nand_write_page_hwecc)) {
2749 printk(KERN_WARNING "No ECC functions supplied, "
2750 "Hardware ECC not possible\n");
2751 BUG();
2752 }
2753 /* Use standard syndrome read/write page function ? */
2754 if (!chip->ecc.read_page)
2755 chip->ecc.read_page = nand_read_page_syndrome;
2756 if (!chip->ecc.write_page)
2757 chip->ecc.write_page = nand_write_page_syndrome;
2758 if (!chip->ecc.read_oob)
2759 chip->ecc.read_oob = nand_read_oob_syndrome;
2760 if (!chip->ecc.write_oob)
2761 chip->ecc.write_oob = nand_write_oob_syndrome;
2762
2763 if (mtd->writesize >= chip->ecc.size)
2764 break;
2765 printk(KERN_WARNING "%d byte HW ECC not possible on "
2766 "%d byte page size, fallback to SW ECC\n",
2767 chip->ecc.size, mtd->writesize);
2768 chip->ecc.mode = NAND_ECC_SOFT;
2769
2770 case NAND_ECC_SOFT:
2771 chip->ecc.calculate = nand_calculate_ecc;
2772 chip->ecc.correct = nand_correct_data;
2773 chip->ecc.read_page = nand_read_page_swecc;
2774 chip->ecc.read_subpage = nand_read_subpage;
2775 chip->ecc.write_page = nand_write_page_swecc;
2776 chip->ecc.read_oob = nand_read_oob_std;
2777 chip->ecc.write_oob = nand_write_oob_std;
2778 chip->ecc.size = 256;
2779 chip->ecc.bytes = 3;
2780 break;
2781
2782 case NAND_ECC_NONE:
2783 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
2784 "This is not recommended !!\n");
2785 chip->ecc.read_page = nand_read_page_raw;
2786 chip->ecc.write_page = nand_write_page_raw;
2787 chip->ecc.read_oob = nand_read_oob_std;
2788 chip->ecc.write_oob = nand_write_oob_std;
2789 chip->ecc.size = mtd->writesize;
2790 chip->ecc.bytes = 0;
2791 break;
2792
2793 default:
2794 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
2795 chip->ecc.mode);
2796 BUG();
2797 }
2798
2799 /*
2800 * The number of bytes available for a client to place data into
2801 * the out of band area
2802 */
2803 chip->ecc.layout->oobavail = 0;
2804 for (i = 0; chip->ecc.layout->oobfree[i].length; i++)
2805 chip->ecc.layout->oobavail +=
2806 chip->ecc.layout->oobfree[i].length;
2807 mtd->oobavail = chip->ecc.layout->oobavail;
2808
2809 /*
2810 * Set the number of read / write steps for one page depending on ECC
2811 * mode
2812 */
2813 chip->ecc.steps = mtd->writesize / chip->ecc.size;
2814 if(chip->ecc.steps * chip->ecc.size != mtd->writesize) {
2815 printk(KERN_WARNING "Invalid ecc parameters\n");
2816 BUG();
2817 }
2818 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
2819
2820 /*
2821 * Allow subpage writes up to ecc.steps. Not possible for MLC
2822 * FLASH.
2823 */
2824 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2825 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
2826 switch(chip->ecc.steps) {
2827 case 2:
2828 mtd->subpage_sft = 1;
2829 break;
2830 case 4:
2831 case 8:
2832 mtd->subpage_sft = 2;
2833 break;
2834 }
2835 }
2836 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
2837
2838 /* Initialize state */
2839 chip->state = FL_READY;
2840
2841 /* De-select the device */
2842 chip->select_chip(mtd, -1);
2843
2844 /* Invalidate the pagebuffer reference */
2845 chip->pagebuf = -1;
2846
2847 /* Fill in remaining MTD driver data */
2848 mtd->type = MTD_NANDFLASH;
2849 mtd->flags = MTD_CAP_NANDFLASH;
2850 mtd->erase = nand_erase;
2851 mtd->point = NULL;
2852 mtd->unpoint = NULL;
2853 mtd->read = nand_read;
2854 mtd->write = nand_write;
2855 mtd->read_oob = nand_read_oob;
2856 mtd->write_oob = nand_write_oob;
2857 mtd->sync = nand_sync;
2858 mtd->lock = NULL;
2859 mtd->unlock = NULL;
2860 mtd->suspend = nand_suspend;
2861 mtd->resume = nand_resume;
2862 mtd->block_isbad = nand_block_isbad;
2863 mtd->block_markbad = nand_block_markbad;
2864
2865 /* propagate ecc.layout to mtd_info */
2866 mtd->ecclayout = chip->ecc.layout;
2867
2868 /* Check, if we should skip the bad block table scan */
2869 if (chip->options & NAND_SKIP_BBTSCAN)
2870 chip->options |= NAND_BBT_SCANNED;
2871
2872 return 0;
2873 }
2874
2875 /* module_text_address() isn't exported, and it's mostly a pointless
2876 test if this is a module _anyway_ -- they'd have to try _really_ hard
2877 to call us from in-kernel code if the core NAND support is modular. */
2878 #ifdef MODULE
2879 #define caller_is_module() (1)
2880 #else
2881 #define caller_is_module() \
2882 module_text_address((unsigned long)__builtin_return_address(0))
2883 #endif
2884
2885 /**
2886 * nand_scan - [NAND Interface] Scan for the NAND device
2887 * @mtd: MTD device structure
2888 * @maxchips: Number of chips to scan for
2889 *
2890 * This fills out all the uninitialized function pointers
2891 * with the defaults.
2892 * The flash ID is read and the mtd/chip structures are
2893 * filled with the appropriate values.
2894 * The mtd->owner field must be set to the module of the caller
2895 *
2896 */
2897 int nand_scan(struct mtd_info *mtd, int maxchips)
2898 {
2899 int ret;
2900
2901 /* Many callers got this wrong, so check for it for a while... */
2902 /* XXX U-BOOT XXX */
2903 #if 0
2904 if (!mtd->owner && caller_is_module()) {
2905 printk(KERN_CRIT "nand_scan() called with NULL mtd->owner!\n");
2906 BUG();
2907 }
2908 #endif
2909
2910 ret = nand_scan_ident(mtd, maxchips);
2911 if (!ret)
2912 ret = nand_scan_tail(mtd);
2913 return ret;
2914 }
2915
2916 /**
2917 * nand_release - [NAND Interface] Free resources held by the NAND device
2918 * @mtd: MTD device structure
2919 */
2920 void nand_release(struct mtd_info *mtd)
2921 {
2922 struct nand_chip *chip = mtd->priv;
2923
2924 #ifdef CONFIG_MTD_PARTITIONS
2925 /* Deregister partitions */
2926 del_mtd_partitions(mtd);
2927 #endif
2928 /* Deregister the device */
2929 /* XXX U-BOOT XXX */
2930 #if 0
2931 del_mtd_device(mtd);
2932 #endif
2933
2934 /* Free bad block table memory */
2935 kfree(chip->bbt);
2936 if (!(chip->options & NAND_OWN_BUFFERS))
2937 kfree(chip->buffers);
2938 }
2939
2940 /* XXX U-BOOT XXX */
2941 #if 0
2942 EXPORT_SYMBOL_GPL(nand_scan);
2943 EXPORT_SYMBOL_GPL(nand_scan_ident);
2944 EXPORT_SYMBOL_GPL(nand_scan_tail);
2945 EXPORT_SYMBOL_GPL(nand_release);
2946
2947 static int __init nand_base_init(void)
2948 {
2949 led_trigger_register_simple("nand-disk", &nand_led_trigger);
2950 return 0;
2951 }
2952
2953 static void __exit nand_base_exit(void)
2954 {
2955 led_trigger_unregister_simple(nand_led_trigger);
2956 }
2957
2958 module_init(nand_base_init);
2959 module_exit(nand_base_exit);
2960
2961 MODULE_LICENSE("GPL");
2962 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>");
2963 MODULE_DESCRIPTION("Generic NAND flash driver code");
2964 #endif
"Das U-Boot" Source Tree