]> git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/mtd/nand/nand_base.c
projects / people / ms / u-boot.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
NAND: ADD page Parameter to all read_page/read_page_raw API's
[people/ms/u-boot.git] / drivers / mtd / nand / nand_base.c
1 /*
2 * drivers/mtd/nand.c
3 *
4 * Overview:
5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
8 *
9 * Additional technical information is available on
10 * http://www.linux-mtd.infradead.org/doc/nand.html
11 *
12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
14 *
15 * Credits:
16 * David Woodhouse for adding multichip support
17 *
18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
20 *
21 * TODO:
22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
24 * if we have HW ecc support.
25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
27 * BBT table is not serialized, has to be fixed
28 *
29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License version 2 as
31 * published by the Free Software Foundation.
32 *
33 */
34
35 /* XXX U-BOOT XXX */
36 #if 0
37 #include <linux/module.h>
38 #include <linux/delay.h>
39 #include <linux/errno.h>
40 #include <linux/err.h>
41 #include <linux/sched.h>
42 #include <linux/slab.h>
43 #include <linux/types.h>
44 #include <linux/mtd/mtd.h>
45 #include <linux/mtd/nand.h>
46 #include <linux/mtd/nand_ecc.h>
47 #include <linux/mtd/compatmac.h>
48 #include <linux/interrupt.h>
49 #include <linux/bitops.h>
50 #include <linux/leds.h>
51 #include <asm/io.h>
52
53 #ifdef CONFIG_MTD_PARTITIONS
54 #include <linux/mtd/partitions.h>
55 #endif
56
57 #endif
58
59 #include <common.h>
60
61 #define ENOTSUPP 524 /* Operation is not supported */
62
63 #include <malloc.h>
64 #include <watchdog.h>
65 #include <linux/err.h>
66 #include <linux/mtd/compat.h>
67 #include <linux/mtd/mtd.h>
68 #include <linux/mtd/nand.h>
69 #include <linux/mtd/nand_ecc.h>
70
71 #ifdef CONFIG_MTD_PARTITIONS
72 #include <linux/mtd/partitions.h>
73 #endif
74
75 #include <asm/io.h>
76 #include <asm/errno.h>
77
78 #ifdef CONFIG_JFFS2_NAND
79 #include <jffs2/jffs2.h>
80 #endif
81
82 /*
83 * CONFIG_SYS_NAND_RESET_CNT is used as a timeout mechanism when resetting
84 * a flash. NAND flash is initialized prior to interrupts so standard timers
85 * can't be used. CONFIG_SYS_NAND_RESET_CNT should be set to a value
86 * which is greater than (max NAND reset time / NAND status read time).
87 * A conservative default of 200000 (500 us / 25 ns) is used as a default.
88 */
89 #ifndef CONFIG_SYS_NAND_RESET_CNT
90 #define CONFIG_SYS_NAND_RESET_CNT 200000
91 #endif
92
93 /* Define default oob placement schemes for large and small page devices */
94 static struct nand_ecclayout nand_oob_8 = {
95 .eccbytes = 3,
96 .eccpos = {0, 1, 2},
97 .oobfree = {
98 {.offset = 3,
99 .length = 2},
100 {.offset = 6,
101 .length = 2}}
102 };
103
104 static struct nand_ecclayout nand_oob_16 = {
105 .eccbytes = 6,
106 .eccpos = {0, 1, 2, 3, 6, 7},
107 .oobfree = {
108 {.offset = 8,
109 . length = 8}}
110 };
111
112 static struct nand_ecclayout nand_oob_64 = {
113 .eccbytes = 24,
114 .eccpos = {
115 40, 41, 42, 43, 44, 45, 46, 47,
116 48, 49, 50, 51, 52, 53, 54, 55,
117 56, 57, 58, 59, 60, 61, 62, 63},
118 .oobfree = {
119 {.offset = 2,
120 .length = 38}}
121 };
122
123 static struct nand_ecclayout nand_oob_128 = {
124 .eccbytes = 48,
125 .eccpos = {
126 80, 81, 82, 83, 84, 85, 86, 87,
127 88, 89, 90, 91, 92, 93, 94, 95,
128 96, 97, 98, 99, 100, 101, 102, 103,
129 104, 105, 106, 107, 108, 109, 110, 111,
130 112, 113, 114, 115, 116, 117, 118, 119,
131 120, 121, 122, 123, 124, 125, 126, 127},
132 .oobfree = {
133 {.offset = 2,
134 .length = 78}}
135 };
136
137
138 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
139 int new_state);
140
141 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
142 struct mtd_oob_ops *ops);
143
144 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this);
145
146 /*
147 * For devices which display every fart in the system on a separate LED. Is
148 * compiled away when LED support is disabled.
149 */
150 /* XXX U-BOOT XXX */
151 #if 0
152 DEFINE_LED_TRIGGER(nand_led_trigger);
153 #endif
154
155 /**
156 * nand_release_device - [GENERIC] release chip
157 * @mtd: MTD device structure
158 *
159 * Deselect, release chip lock and wake up anyone waiting on the device
160 */
161 /* XXX U-BOOT XXX */
162 #if 0
163 static void nand_release_device(struct mtd_info *mtd)
164 {
165 struct nand_chip *chip = mtd->priv;
166
167 /* De-select the NAND device */
168 chip->select_chip(mtd, -1);
169
170 /* Release the controller and the chip */
171 spin_lock(&chip->controller->lock);
172 chip->controller->active = NULL;
173 chip->state = FL_READY;
174 wake_up(&chip->controller->wq);
175 spin_unlock(&chip->controller->lock);
176 }
177 #else
178 static void nand_release_device (struct mtd_info *mtd)
179 {
180 struct nand_chip *this = mtd->priv;
181 this->select_chip(mtd, -1); /* De-select the NAND device */
182 }
183 #endif
184
185 /**
186 * nand_read_byte - [DEFAULT] read one byte from the chip
187 * @mtd: MTD device structure
188 *
189 * Default read function for 8bit buswith
190 */
191 static uint8_t nand_read_byte(struct mtd_info *mtd)
192 {
193 struct nand_chip *chip = mtd->priv;
194 return readb(chip->IO_ADDR_R);
195 }
196
197 /**
198 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
199 * @mtd: MTD device structure
200 *
201 * Default read function for 16bit buswith with
202 * endianess conversion
203 */
204 static uint8_t nand_read_byte16(struct mtd_info *mtd)
205 {
206 struct nand_chip *chip = mtd->priv;
207 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
208 }
209
210 /**
211 * nand_read_word - [DEFAULT] read one word from the chip
212 * @mtd: MTD device structure
213 *
214 * Default read function for 16bit buswith without
215 * endianess conversion
216 */
217 static u16 nand_read_word(struct mtd_info *mtd)
218 {
219 struct nand_chip *chip = mtd->priv;
220 return readw(chip->IO_ADDR_R);
221 }
222
223 /**
224 * nand_select_chip - [DEFAULT] control CE line
225 * @mtd: MTD device structure
226 * @chipnr: chipnumber to select, -1 for deselect
227 *
228 * Default select function for 1 chip devices.
229 */
230 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
231 {
232 struct nand_chip *chip = mtd->priv;
233
234 switch (chipnr) {
235 case -1:
236 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
237 break;
238 case 0:
239 break;
240
241 default:
242 BUG();
243 }
244 }
245
246 /**
247 * nand_write_buf - [DEFAULT] write buffer to chip
248 * @mtd: MTD device structure
249 * @buf: data buffer
250 * @len: number of bytes to write
251 *
252 * Default write function for 8bit buswith
253 */
254 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
255 {
256 int i;
257 struct nand_chip *chip = mtd->priv;
258
259 for (i = 0; i < len; i++)
260 writeb(buf[i], chip->IO_ADDR_W);
261 }
262
263 /**
264 * nand_read_buf - [DEFAULT] read chip data into buffer
265 * @mtd: MTD device structure
266 * @buf: buffer to store date
267 * @len: number of bytes to read
268 *
269 * Default read function for 8bit buswith
270 */
271 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
272 {
273 int i;
274 struct nand_chip *chip = mtd->priv;
275
276 for (i = 0; i < len; i++)
277 buf[i] = readb(chip->IO_ADDR_R);
278 }
279
280 /**
281 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
282 * @mtd: MTD device structure
283 * @buf: buffer containing the data to compare
284 * @len: number of bytes to compare
285 *
286 * Default verify function for 8bit buswith
287 */
288 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
289 {
290 int i;
291 struct nand_chip *chip = mtd->priv;
292
293 for (i = 0; i < len; i++)
294 if (buf[i] != readb(chip->IO_ADDR_R))
295 return -EFAULT;
296 return 0;
297 }
298
299 /**
300 * nand_write_buf16 - [DEFAULT] write buffer to chip
301 * @mtd: MTD device structure
302 * @buf: data buffer
303 * @len: number of bytes to write
304 *
305 * Default write function for 16bit buswith
306 */
307 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
308 {
309 int i;
310 struct nand_chip *chip = mtd->priv;
311 u16 *p = (u16 *) buf;
312 len >>= 1;
313
314 for (i = 0; i < len; i++)
315 writew(p[i], chip->IO_ADDR_W);
316
317 }
318
319 /**
320 * nand_read_buf16 - [DEFAULT] read chip data into buffer
321 * @mtd: MTD device structure
322 * @buf: buffer to store date
323 * @len: number of bytes to read
324 *
325 * Default read function for 16bit buswith
326 */
327 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
328 {
329 int i;
330 struct nand_chip *chip = mtd->priv;
331 u16 *p = (u16 *) buf;
332 len >>= 1;
333
334 for (i = 0; i < len; i++)
335 p[i] = readw(chip->IO_ADDR_R);
336 }
337
338 /**
339 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
340 * @mtd: MTD device structure
341 * @buf: buffer containing the data to compare
342 * @len: number of bytes to compare
343 *
344 * Default verify function for 16bit buswith
345 */
346 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
347 {
348 int i;
349 struct nand_chip *chip = mtd->priv;
350 u16 *p = (u16 *) buf;
351 len >>= 1;
352
353 for (i = 0; i < len; i++)
354 if (p[i] != readw(chip->IO_ADDR_R))
355 return -EFAULT;
356
357 return 0;
358 }
359
360 /**
361 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
362 * @mtd: MTD device structure
363 * @ofs: offset from device start
364 * @getchip: 0, if the chip is already selected
365 *
366 * Check, if the block is bad.
367 */
368 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
369 {
370 int page, chipnr, res = 0;
371 struct nand_chip *chip = mtd->priv;
372 u16 bad;
373
374 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
375
376 if (getchip) {
377 chipnr = (int)(ofs >> chip->chip_shift);
378
379 nand_get_device(chip, mtd, FL_READING);
380
381 /* Select the NAND device */
382 chip->select_chip(mtd, chipnr);
383 }
384
385 if (chip->options & NAND_BUSWIDTH_16) {
386 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
387 page);
388 bad = cpu_to_le16(chip->read_word(mtd));
389 if (chip->badblockpos & 0x1)
390 bad >>= 8;
391 if ((bad & 0xFF) != 0xff)
392 res = 1;
393 } else {
394 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
395 if (chip->read_byte(mtd) != 0xff)
396 res = 1;
397 }
398
399 if (getchip)
400 nand_release_device(mtd);
401
402 return res;
403 }
404
405 /**
406 * nand_default_block_markbad - [DEFAULT] mark a block bad
407 * @mtd: MTD device structure
408 * @ofs: offset from device start
409 *
410 * This is the default implementation, which can be overridden by
411 * a hardware specific driver.
412 */
413 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
414 {
415 struct nand_chip *chip = mtd->priv;
416 uint8_t buf[2] = { 0, 0 };
417 int block, ret;
418
419 /* Get block number */
420 block = (int)(ofs >> chip->bbt_erase_shift);
421 if (chip->bbt)
422 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
423
424 /* Do we have a flash based bad block table ? */
425 if (chip->options & NAND_USE_FLASH_BBT)
426 ret = nand_update_bbt(mtd, ofs);
427 else {
428 /* We write two bytes, so we dont have to mess with 16 bit
429 * access
430 */
431 nand_get_device(chip, mtd, FL_WRITING);
432 ofs += mtd->oobsize;
433 chip->ops.len = chip->ops.ooblen = 2;
434 chip->ops.datbuf = NULL;
435 chip->ops.oobbuf = buf;
436 chip->ops.ooboffs = chip->badblockpos & ~0x01;
437
438 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
439 nand_release_device(mtd);
440 }
441 if (!ret)
442 mtd->ecc_stats.badblocks++;
443
444 return ret;
445 }
446
447 /**
448 * nand_check_wp - [GENERIC] check if the chip is write protected
449 * @mtd: MTD device structure
450 * Check, if the device is write protected
451 *
452 * The function expects, that the device is already selected
453 */
454 static int nand_check_wp(struct mtd_info *mtd)
455 {
456 struct nand_chip *chip = mtd->priv;
457 /* Check the WP bit */
458 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
459 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
460 }
461
462 /**
463 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
464 * @mtd: MTD device structure
465 * @ofs: offset from device start
466 * @getchip: 0, if the chip is already selected
467 * @allowbbt: 1, if its allowed to access the bbt area
468 *
469 * Check, if the block is bad. Either by reading the bad block table or
470 * calling of the scan function.
471 */
472 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
473 int allowbbt)
474 {
475 struct nand_chip *chip = mtd->priv;
476
477 if (!(chip->options & NAND_BBT_SCANNED)) {
478 chip->options |= NAND_BBT_SCANNED;
479 chip->scan_bbt(mtd);
480 }
481
482 if (!chip->bbt)
483 return chip->block_bad(mtd, ofs, getchip);
484
485 /* Return info from the table */
486 return nand_isbad_bbt(mtd, ofs, allowbbt);
487 }
488
489 /*
490 * Wait for the ready pin, after a command
491 * The timeout is catched later.
492 */
493 /* XXX U-BOOT XXX */
494 #if 0
495 void nand_wait_ready(struct mtd_info *mtd)
496 {
497 struct nand_chip *chip = mtd->priv;
498 unsigned long timeo = jiffies + 2;
499
500 led_trigger_event(nand_led_trigger, LED_FULL);
501 /* wait until command is processed or timeout occures */
502 do {
503 if (chip->dev_ready(mtd))
504 break;
505 touch_softlockup_watchdog();
506 } while (time_before(jiffies, timeo));
507 led_trigger_event(nand_led_trigger, LED_OFF);
508 }
509 EXPORT_SYMBOL_GPL(nand_wait_ready);
510 #else
511 void nand_wait_ready(struct mtd_info *mtd)
512 {
513 struct nand_chip *chip = mtd->priv;
514 u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
515
516 reset_timer();
517
518 /* wait until command is processed or timeout occures */
519 while (get_timer(0) < timeo) {
520 if (chip->dev_ready)
521 if (chip->dev_ready(mtd))
522 break;
523 }
524 }
525 #endif
526
527 /**
528 * nand_command - [DEFAULT] Send command to NAND device
529 * @mtd: MTD device structure
530 * @command: the command to be sent
531 * @column: the column address for this command, -1 if none
532 * @page_addr: the page address for this command, -1 if none
533 *
534 * Send command to NAND device. This function is used for small page
535 * devices (256/512 Bytes per page)
536 */
537 static void nand_command(struct mtd_info *mtd, unsigned int command,
538 int column, int page_addr)
539 {
540 register struct nand_chip *chip = mtd->priv;
541 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
542 uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
543
544 /*
545 * Write out the command to the device.
546 */
547 if (command == NAND_CMD_SEQIN) {
548 int readcmd;
549
550 if (column >= mtd->writesize) {
551 /* OOB area */
552 column -= mtd->writesize;
553 readcmd = NAND_CMD_READOOB;
554 } else if (column < 256) {
555 /* First 256 bytes --> READ0 */
556 readcmd = NAND_CMD_READ0;
557 } else {
558 column -= 256;
559 readcmd = NAND_CMD_READ1;
560 }
561 chip->cmd_ctrl(mtd, readcmd, ctrl);
562 ctrl &= ~NAND_CTRL_CHANGE;
563 }
564 chip->cmd_ctrl(mtd, command, ctrl);
565
566 /*
567 * Address cycle, when necessary
568 */
569 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
570 /* Serially input address */
571 if (column != -1) {
572 /* Adjust columns for 16 bit buswidth */
573 if (chip->options & NAND_BUSWIDTH_16)
574 column >>= 1;
575 chip->cmd_ctrl(mtd, column, ctrl);
576 ctrl &= ~NAND_CTRL_CHANGE;
577 }
578 if (page_addr != -1) {
579 chip->cmd_ctrl(mtd, page_addr, ctrl);
580 ctrl &= ~NAND_CTRL_CHANGE;
581 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
582 /* One more address cycle for devices > 32MiB */
583 if (chip->chipsize > (32 << 20))
584 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
585 }
586 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
587
588 /*
589 * program and erase have their own busy handlers
590 * status and sequential in needs no delay
591 */
592 switch (command) {
593
594 case NAND_CMD_PAGEPROG:
595 case NAND_CMD_ERASE1:
596 case NAND_CMD_ERASE2:
597 case NAND_CMD_SEQIN:
598 case NAND_CMD_STATUS:
599 return;
600
601 case NAND_CMD_RESET:
602 if (chip->dev_ready)
603 break;
604 udelay(chip->chip_delay);
605 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
606 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
607 chip->cmd_ctrl(mtd,
608 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
609 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
610 (rst_sts_cnt--));
611 return;
612
613 /* This applies to read commands */
614 default:
615 /*
616 * If we don't have access to the busy pin, we apply the given
617 * command delay
618 */
619 if (!chip->dev_ready) {
620 udelay(chip->chip_delay);
621 return;
622 }
623 }
624 /* Apply this short delay always to ensure that we do wait tWB in
625 * any case on any machine. */
626 ndelay(100);
627
628 nand_wait_ready(mtd);
629 }
630
631 /**
632 * nand_command_lp - [DEFAULT] Send command to NAND large page device
633 * @mtd: MTD device structure
634 * @command: the command to be sent
635 * @column: the column address for this command, -1 if none
636 * @page_addr: the page address for this command, -1 if none
637 *
638 * Send command to NAND device. This is the version for the new large page
639 * devices We dont have the separate regions as we have in the small page
640 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
641 */
642 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
643 int column, int page_addr)
644 {
645 register struct nand_chip *chip = mtd->priv;
646 uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
647
648 /* Emulate NAND_CMD_READOOB */
649 if (command == NAND_CMD_READOOB) {
650 column += mtd->writesize;
651 command = NAND_CMD_READ0;
652 }
653
654 /* Command latch cycle */
655 chip->cmd_ctrl(mtd, command & 0xff,
656 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
657
658 if (column != -1 || page_addr != -1) {
659 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
660
661 /* Serially input address */
662 if (column != -1) {
663 /* Adjust columns for 16 bit buswidth */
664 if (chip->options & NAND_BUSWIDTH_16)
665 column >>= 1;
666 chip->cmd_ctrl(mtd, column, ctrl);
667 ctrl &= ~NAND_CTRL_CHANGE;
668 chip->cmd_ctrl(mtd, column >> 8, ctrl);
669 }
670 if (page_addr != -1) {
671 chip->cmd_ctrl(mtd, page_addr, ctrl);
672 chip->cmd_ctrl(mtd, page_addr >> 8,
673 NAND_NCE | NAND_ALE);
674 /* One more address cycle for devices > 128MiB */
675 if (chip->chipsize > (128 << 20))
676 chip->cmd_ctrl(mtd, page_addr >> 16,
677 NAND_NCE | NAND_ALE);
678 }
679 }
680 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
681
682 /*
683 * program and erase have their own busy handlers
684 * status, sequential in, and deplete1 need no delay
685 */
686 switch (command) {
687
688 case NAND_CMD_CACHEDPROG:
689 case NAND_CMD_PAGEPROG:
690 case NAND_CMD_ERASE1:
691 case NAND_CMD_ERASE2:
692 case NAND_CMD_SEQIN:
693 case NAND_CMD_RNDIN:
694 case NAND_CMD_STATUS:
695 case NAND_CMD_DEPLETE1:
696 return;
697
698 /*
699 * read error status commands require only a short delay
700 */
701 case NAND_CMD_STATUS_ERROR:
702 case NAND_CMD_STATUS_ERROR0:
703 case NAND_CMD_STATUS_ERROR1:
704 case NAND_CMD_STATUS_ERROR2:
705 case NAND_CMD_STATUS_ERROR3:
706 udelay(chip->chip_delay);
707 return;
708
709 case NAND_CMD_RESET:
710 if (chip->dev_ready)
711 break;
712 udelay(chip->chip_delay);
713 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
714 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
715 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
716 NAND_NCE | NAND_CTRL_CHANGE);
717 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
718 (rst_sts_cnt--));
719 return;
720
721 case NAND_CMD_RNDOUT:
722 /* No ready / busy check necessary */
723 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
724 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
725 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
726 NAND_NCE | NAND_CTRL_CHANGE);
727 return;
728
729 case NAND_CMD_READ0:
730 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
731 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
732 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
733 NAND_NCE | NAND_CTRL_CHANGE);
734
735 /* This applies to read commands */
736 default:
737 /*
738 * If we don't have access to the busy pin, we apply the given
739 * command delay
740 */
741 if (!chip->dev_ready) {
742 udelay(chip->chip_delay);
743 return;
744 }
745 }
746
747 /* Apply this short delay always to ensure that we do wait tWB in
748 * any case on any machine. */
749 ndelay(100);
750
751 nand_wait_ready(mtd);
752 }
753
754 /**
755 * nand_get_device - [GENERIC] Get chip for selected access
756 * @chip: the nand chip descriptor
757 * @mtd: MTD device structure
758 * @new_state: the state which is requested
759 *
760 * Get the device and lock it for exclusive access
761 */
762 /* XXX U-BOOT XXX */
763 #if 0
764 static int
765 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
766 {
767 spinlock_t *lock = &chip->controller->lock;
768 wait_queue_head_t *wq = &chip->controller->wq;
769 DECLARE_WAITQUEUE(wait, current);
770 retry:
771 spin_lock(lock);
772
773 /* Hardware controller shared among independend devices */
774 /* Hardware controller shared among independend devices */
775 if (!chip->controller->active)
776 chip->controller->active = chip;
777
778 if (chip->controller->active == chip && chip->state == FL_READY) {
779 chip->state = new_state;
780 spin_unlock(lock);
781 return 0;
782 }
783 if (new_state == FL_PM_SUSPENDED) {
784 spin_unlock(lock);
785 return (chip->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN;
786 }
787 set_current_state(TASK_UNINTERRUPTIBLE);
788 add_wait_queue(wq, &wait);
789 spin_unlock(lock);
790 schedule();
791 remove_wait_queue(wq, &wait);
792 goto retry;
793 }
794 #else
795 static int nand_get_device (struct nand_chip *this, struct mtd_info *mtd, int new_state)
796 {
797 this->state = new_state;
798 return 0;
799 }
800 #endif
801
802 /**
803 * nand_wait - [DEFAULT] wait until the command is done
804 * @mtd: MTD device structure
805 * @chip: NAND chip structure
806 *
807 * Wait for command done. This applies to erase and program only
808 * Erase can take up to 400ms and program up to 20ms according to
809 * general NAND and SmartMedia specs
810 */
811 /* XXX U-BOOT XXX */
812 #if 0
813 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
814 {
815
816 unsigned long timeo = jiffies;
817 int status, state = chip->state;
818
819 if (state == FL_ERASING)
820 timeo += (HZ * 400) / 1000;
821 else
822 timeo += (HZ * 20) / 1000;
823
824 led_trigger_event(nand_led_trigger, LED_FULL);
825
826 /* Apply this short delay always to ensure that we do wait tWB in
827 * any case on any machine. */
828 ndelay(100);
829
830 if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
831 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
832 else
833 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
834
835 while (time_before(jiffies, timeo)) {
836 if (chip->dev_ready) {
837 if (chip->dev_ready(mtd))
838 break;
839 } else {
840 if (chip->read_byte(mtd) & NAND_STATUS_READY)
841 break;
842 }
843 cond_resched();
844 }
845 led_trigger_event(nand_led_trigger, LED_OFF);
846
847 status = (int)chip->read_byte(mtd);
848 return status;
849 }
850 #else
851 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this)
852 {
853 unsigned long timeo;
854 int state = this->state;
855
856 if (state == FL_ERASING)
857 timeo = (CONFIG_SYS_HZ * 400) / 1000;
858 else
859 timeo = (CONFIG_SYS_HZ * 20) / 1000;
860
861 if ((state == FL_ERASING) && (this->options & NAND_IS_AND))
862 this->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
863 else
864 this->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
865
866 reset_timer();
867
868 while (1) {
869 if (get_timer(0) > timeo) {
870 printf("Timeout!");
871 return 0x01;
872 }
873
874 if (this->dev_ready) {
875 if (this->dev_ready(mtd))
876 break;
877 } else {
878 if (this->read_byte(mtd) & NAND_STATUS_READY)
879 break;
880 }
881 }
882 #ifdef PPCHAMELON_NAND_TIMER_HACK
883 reset_timer();
884 while (get_timer(0) < 10);
885 #endif /* PPCHAMELON_NAND_TIMER_HACK */
886
887 return this->read_byte(mtd);
888 }
889 #endif
890
891 /**
892 * nand_read_page_raw - [Intern] read raw page data without ecc
893 * @mtd: mtd info structure
894 * @chip: nand chip info structure
895 * @buf: buffer to store read data
896 */
897 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
898 uint8_t *buf, int page)
899 {
900 chip->read_buf(mtd, buf, mtd->writesize);
901 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
902 return 0;
903 }
904
905 /**
906 * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
907 * @mtd: mtd info structure
908 * @chip: nand chip info structure
909 * @buf: buffer to store read data
910 */
911 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
912 uint8_t *buf, int page)
913 {
914 int i, eccsize = chip->ecc.size;
915 int eccbytes = chip->ecc.bytes;
916 int eccsteps = chip->ecc.steps;
917 uint8_t *p = buf;
918 uint8_t *ecc_calc = chip->buffers->ecccalc;
919 uint8_t *ecc_code = chip->buffers->ecccode;
920 uint32_t *eccpos = chip->ecc.layout->eccpos;
921
922 chip->ecc.read_page_raw(mtd, chip, buf, page);
923
924 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
925 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
926
927 for (i = 0; i < chip->ecc.total; i++)
928 ecc_code[i] = chip->oob_poi[eccpos[i]];
929
930 eccsteps = chip->ecc.steps;
931 p = buf;
932
933 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
934 int stat;
935
936 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
937 if (stat < 0)
938 mtd->ecc_stats.failed++;
939 else
940 mtd->ecc_stats.corrected += stat;
941 }
942 return 0;
943 }
944
945 /**
946 * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
947 * @mtd: mtd info structure
948 * @chip: nand chip info structure
949 * @dataofs offset of requested data within the page
950 * @readlen data length
951 * @buf: buffer to store read data
952 */
953 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
954 {
955 int start_step, end_step, num_steps;
956 uint32_t *eccpos = chip->ecc.layout->eccpos;
957 uint8_t *p;
958 int data_col_addr, i, gaps = 0;
959 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
960 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
961
962 /* Column address wihin the page aligned to ECC size (256bytes). */
963 start_step = data_offs / chip->ecc.size;
964 end_step = (data_offs + readlen - 1) / chip->ecc.size;
965 num_steps = end_step - start_step + 1;
966
967 /* Data size aligned to ECC ecc.size*/
968 datafrag_len = num_steps * chip->ecc.size;
969 eccfrag_len = num_steps * chip->ecc.bytes;
970
971 data_col_addr = start_step * chip->ecc.size;
972 /* If we read not a page aligned data */
973 if (data_col_addr != 0)
974 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
975
976 p = bufpoi + data_col_addr;
977 chip->read_buf(mtd, p, datafrag_len);
978
979 /* Calculate ECC */
980 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
981 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
982
983 /* The performance is faster if to position offsets
984 according to ecc.pos. Let make sure here that
985 there are no gaps in ecc positions */
986 for (i = 0; i < eccfrag_len - 1; i++) {
987 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
988 eccpos[i + start_step * chip->ecc.bytes + 1]) {
989 gaps = 1;
990 break;
991 }
992 }
993 if (gaps) {
994 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
995 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
996 } else {
997 /* send the command to read the particular ecc bytes */
998 /* take care about buswidth alignment in read_buf */
999 aligned_pos = eccpos[start_step * chip->ecc.bytes] & ~(busw - 1);
1000 aligned_len = eccfrag_len;
1001 if (eccpos[start_step * chip->ecc.bytes] & (busw - 1))
1002 aligned_len++;
1003 if (eccpos[(start_step + num_steps) * chip->ecc.bytes] & (busw - 1))
1004 aligned_len++;
1005
1006 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize + aligned_pos, -1);
1007 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1008 }
1009
1010 for (i = 0; i < eccfrag_len; i++)
1011 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + start_step * chip->ecc.bytes]];
1012
1013 p = bufpoi + data_col_addr;
1014 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1015 int stat;
1016
1017 stat = chip->ecc.correct(mtd, p, &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1018 if (stat < 0)
1019 mtd->ecc_stats.failed++;
1020 else
1021 mtd->ecc_stats.corrected += stat;
1022 }
1023 return 0;
1024 }
1025
1026 /**
1027 * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
1028 * @mtd: mtd info structure
1029 * @chip: nand chip info structure
1030 * @buf: buffer to store read data
1031 *
1032 * Not for syndrome calculating ecc controllers which need a special oob layout
1033 */
1034 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1035 uint8_t *buf, int page)
1036 {
1037 int i, eccsize = chip->ecc.size;
1038 int eccbytes = chip->ecc.bytes;
1039 int eccsteps = chip->ecc.steps;
1040 uint8_t *p = buf;
1041 uint8_t *ecc_calc = chip->buffers->ecccalc;
1042 uint8_t *ecc_code = chip->buffers->ecccode;
1043 uint32_t *eccpos = chip->ecc.layout->eccpos;
1044
1045 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1046 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1047 chip->read_buf(mtd, p, eccsize);
1048 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1049 }
1050 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1051
1052 for (i = 0; i < chip->ecc.total; i++)
1053 ecc_code[i] = chip->oob_poi[eccpos[i]];
1054
1055 eccsteps = chip->ecc.steps;
1056 p = buf;
1057
1058 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1059 int stat;
1060
1061 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1062 if (stat == -1)
1063 mtd->ecc_stats.failed++;
1064 else
1065 mtd->ecc_stats.corrected += stat;
1066 }
1067 return 0;
1068 }
1069
1070 /**
1071 * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
1072 * @mtd: mtd info structure
1073 * @chip: nand chip info structure
1074 * @buf: buffer to store read data
1075 *
1076 * The hw generator calculates the error syndrome automatically. Therefor
1077 * we need a special oob layout and handling.
1078 */
1079 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1080 uint8_t *buf, int page)
1081 {
1082 int i, eccsize = chip->ecc.size;
1083 int eccbytes = chip->ecc.bytes;
1084 int eccsteps = chip->ecc.steps;
1085 uint8_t *p = buf;
1086 uint8_t *oob = chip->oob_poi;
1087
1088 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1089 int stat;
1090
1091 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1092 chip->read_buf(mtd, p, eccsize);
1093
1094 if (chip->ecc.prepad) {
1095 chip->read_buf(mtd, oob, chip->ecc.prepad);
1096 oob += chip->ecc.prepad;
1097 }
1098
1099 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1100 chip->read_buf(mtd, oob, eccbytes);
1101 stat = chip->ecc.correct(mtd, p, oob, NULL);
1102
1103 if (stat < 0)
1104 mtd->ecc_stats.failed++;
1105 else
1106 mtd->ecc_stats.corrected += stat;
1107
1108 oob += eccbytes;
1109
1110 if (chip->ecc.postpad) {
1111 chip->read_buf(mtd, oob, chip->ecc.postpad);
1112 oob += chip->ecc.postpad;
1113 }
1114 }
1115
1116 /* Calculate remaining oob bytes */
1117 i = mtd->oobsize - (oob - chip->oob_poi);
1118 if (i)
1119 chip->read_buf(mtd, oob, i);
1120
1121 return 0;
1122 }
1123
1124 /**
1125 * nand_transfer_oob - [Internal] Transfer oob to client buffer
1126 * @chip: nand chip structure
1127 * @oob: oob destination address
1128 * @ops: oob ops structure
1129 * @len: size of oob to transfer
1130 */
1131 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1132 struct mtd_oob_ops *ops, size_t len)
1133 {
1134 switch(ops->mode) {
1135
1136 case MTD_OOB_PLACE:
1137 case MTD_OOB_RAW:
1138 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1139 return oob + len;
1140
1141 case MTD_OOB_AUTO: {
1142 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1143 uint32_t boffs = 0, roffs = ops->ooboffs;
1144 size_t bytes = 0;
1145
1146 for(; free->length && len; free++, len -= bytes) {
1147 /* Read request not from offset 0 ? */
1148 if (unlikely(roffs)) {
1149 if (roffs >= free->length) {
1150 roffs -= free->length;
1151 continue;
1152 }
1153 boffs = free->offset + roffs;
1154 bytes = min_t(size_t, len,
1155 (free->length - roffs));
1156 roffs = 0;
1157 } else {
1158 bytes = min_t(size_t, len, free->length);
1159 boffs = free->offset;
1160 }
1161 memcpy(oob, chip->oob_poi + boffs, bytes);
1162 oob += bytes;
1163 }
1164 return oob;
1165 }
1166 default:
1167 BUG();
1168 }
1169 return NULL;
1170 }
1171
1172 /**
1173 * nand_do_read_ops - [Internal] Read data with ECC
1174 *
1175 * @mtd: MTD device structure
1176 * @from: offset to read from
1177 * @ops: oob ops structure
1178 *
1179 * Internal function. Called with chip held.
1180 */
1181 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1182 struct mtd_oob_ops *ops)
1183 {
1184 int chipnr, page, realpage, col, bytes, aligned;
1185 struct nand_chip *chip = mtd->priv;
1186 struct mtd_ecc_stats stats;
1187 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1188 int sndcmd = 1;
1189 int ret = 0;
1190 uint32_t readlen = ops->len;
1191 uint32_t oobreadlen = ops->ooblen;
1192 uint8_t *bufpoi, *oob, *buf;
1193
1194 stats = mtd->ecc_stats;
1195
1196 chipnr = (int)(from >> chip->chip_shift);
1197 chip->select_chip(mtd, chipnr);
1198
1199 realpage = (int)(from >> chip->page_shift);
1200 page = realpage & chip->pagemask;
1201
1202 col = (int)(from & (mtd->writesize - 1));
1203
1204 buf = ops->datbuf;
1205 oob = ops->oobbuf;
1206
1207 while(1) {
1208 bytes = min(mtd->writesize - col, readlen);
1209 aligned = (bytes == mtd->writesize);
1210
1211 /* Is the current page in the buffer ? */
1212 if (realpage != chip->pagebuf || oob) {
1213 bufpoi = aligned ? buf : chip->buffers->databuf;
1214
1215 if (likely(sndcmd)) {
1216 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1217 sndcmd = 0;
1218 }
1219
1220 /* Now read the page into the buffer */
1221 if (unlikely(ops->mode == MTD_OOB_RAW))
1222 ret = chip->ecc.read_page_raw(mtd, chip,
1223 bufpoi, page);
1224 else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
1225 ret = chip->ecc.read_subpage(mtd, chip, col, bytes, bufpoi);
1226 else
1227 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1228 page);
1229 if (ret < 0)
1230 break;
1231
1232 /* Transfer not aligned data */
1233 if (!aligned) {
1234 if (!NAND_SUBPAGE_READ(chip) && !oob)
1235 chip->pagebuf = realpage;
1236 memcpy(buf, chip->buffers->databuf + col, bytes);
1237 }
1238
1239 buf += bytes;
1240
1241 if (unlikely(oob)) {
1242 /* Raw mode does data:oob:data:oob */
1243 if (ops->mode != MTD_OOB_RAW) {
1244 int toread = min(oobreadlen,
1245 chip->ecc.layout->oobavail);
1246 if (toread) {
1247 oob = nand_transfer_oob(chip,
1248 oob, ops, toread);
1249 oobreadlen -= toread;
1250 }
1251 } else
1252 buf = nand_transfer_oob(chip,
1253 buf, ops, mtd->oobsize);
1254 }
1255
1256 if (!(chip->options & NAND_NO_READRDY)) {
1257 /*
1258 * Apply delay or wait for ready/busy pin. Do
1259 * this before the AUTOINCR check, so no
1260 * problems arise if a chip which does auto
1261 * increment is marked as NOAUTOINCR by the
1262 * board driver.
1263 */
1264 if (!chip->dev_ready)
1265 udelay(chip->chip_delay);
1266 else
1267 nand_wait_ready(mtd);
1268 }
1269 } else {
1270 memcpy(buf, chip->buffers->databuf + col, bytes);
1271 buf += bytes;
1272 }
1273
1274 readlen -= bytes;
1275
1276 if (!readlen)
1277 break;
1278
1279 /* For subsequent reads align to page boundary. */
1280 col = 0;
1281 /* Increment page address */
1282 realpage++;
1283
1284 page = realpage & chip->pagemask;
1285 /* Check, if we cross a chip boundary */
1286 if (!page) {
1287 chipnr++;
1288 chip->select_chip(mtd, -1);
1289 chip->select_chip(mtd, chipnr);
1290 }
1291
1292 /* Check, if the chip supports auto page increment
1293 * or if we have hit a block boundary.
1294 */
1295 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1296 sndcmd = 1;
1297 }
1298
1299 ops->retlen = ops->len - (size_t) readlen;
1300 if (oob)
1301 ops->oobretlen = ops->ooblen - oobreadlen;
1302
1303 if (ret)
1304 return ret;
1305
1306 if (mtd->ecc_stats.failed - stats.failed)
1307 return -EBADMSG;
1308
1309 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1310 }
1311
1312 /**
1313 * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
1314 * @mtd: MTD device structure
1315 * @from: offset to read from
1316 * @len: number of bytes to read
1317 * @retlen: pointer to variable to store the number of read bytes
1318 * @buf: the databuffer to put data
1319 *
1320 * Get hold of the chip and call nand_do_read
1321 */
1322 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1323 size_t *retlen, uint8_t *buf)
1324 {
1325 struct nand_chip *chip = mtd->priv;
1326 int ret;
1327
1328 /* Do not allow reads past end of device */
1329 if ((from + len) > mtd->size)
1330 return -EINVAL;
1331 if (!len)
1332 return 0;
1333
1334 nand_get_device(chip, mtd, FL_READING);
1335
1336 chip->ops.len = len;
1337 chip->ops.datbuf = buf;
1338 chip->ops.oobbuf = NULL;
1339
1340 ret = nand_do_read_ops(mtd, from, &chip->ops);
1341
1342 *retlen = chip->ops.retlen;
1343
1344 nand_release_device(mtd);
1345
1346 return ret;
1347 }
1348
1349 /**
1350 * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1351 * @mtd: mtd info structure
1352 * @chip: nand chip info structure
1353 * @page: page number to read
1354 * @sndcmd: flag whether to issue read command or not
1355 */
1356 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1357 int page, int sndcmd)
1358 {
1359 if (sndcmd) {
1360 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1361 sndcmd = 0;
1362 }
1363 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1364 return sndcmd;
1365 }
1366
1367 /**
1368 * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1369 * with syndromes
1370 * @mtd: mtd info structure
1371 * @chip: nand chip info structure
1372 * @page: page number to read
1373 * @sndcmd: flag whether to issue read command or not
1374 */
1375 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1376 int page, int sndcmd)
1377 {
1378 uint8_t *buf = chip->oob_poi;
1379 int length = mtd->oobsize;
1380 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1381 int eccsize = chip->ecc.size;
1382 uint8_t *bufpoi = buf;
1383 int i, toread, sndrnd = 0, pos;
1384
1385 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1386 for (i = 0; i < chip->ecc.steps; i++) {
1387 if (sndrnd) {
1388 pos = eccsize + i * (eccsize + chunk);
1389 if (mtd->writesize > 512)
1390 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1391 else
1392 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1393 } else
1394 sndrnd = 1;
1395 toread = min_t(int, length, chunk);
1396 chip->read_buf(mtd, bufpoi, toread);
1397 bufpoi += toread;
1398 length -= toread;
1399 }
1400 if (length > 0)
1401 chip->read_buf(mtd, bufpoi, length);
1402
1403 return 1;
1404 }
1405
1406 /**
1407 * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1408 * @mtd: mtd info structure
1409 * @chip: nand chip info structure
1410 * @page: page number to write
1411 */
1412 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1413 int page)
1414 {
1415 int status = 0;
1416 const uint8_t *buf = chip->oob_poi;
1417 int length = mtd->oobsize;
1418
1419 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1420 chip->write_buf(mtd, buf, length);
1421 /* Send command to program the OOB data */
1422 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1423
1424 status = chip->waitfunc(mtd, chip);
1425
1426 return status & NAND_STATUS_FAIL ? -EIO : 0;
1427 }
1428
1429 /**
1430 * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1431 * with syndrome - only for large page flash !
1432 * @mtd: mtd info structure
1433 * @chip: nand chip info structure
1434 * @page: page number to write
1435 */
1436 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1437 struct nand_chip *chip, int page)
1438 {
1439 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1440 int eccsize = chip->ecc.size, length = mtd->oobsize;
1441 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1442 const uint8_t *bufpoi = chip->oob_poi;
1443
1444 /*
1445 * data-ecc-data-ecc ... ecc-oob
1446 * or
1447 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1448 */
1449 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1450 pos = steps * (eccsize + chunk);
1451 steps = 0;
1452 } else
1453 pos = eccsize;
1454
1455 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1456 for (i = 0; i < steps; i++) {
1457 if (sndcmd) {
1458 if (mtd->writesize <= 512) {
1459 uint32_t fill = 0xFFFFFFFF;
1460
1461 len = eccsize;
1462 while (len > 0) {
1463 int num = min_t(int, len, 4);
1464 chip->write_buf(mtd, (uint8_t *)&fill,
1465 num);
1466 len -= num;
1467 }
1468 } else {
1469 pos = eccsize + i * (eccsize + chunk);
1470 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1471 }
1472 } else
1473 sndcmd = 1;
1474 len = min_t(int, length, chunk);
1475 chip->write_buf(mtd, bufpoi, len);
1476 bufpoi += len;
1477 length -= len;
1478 }
1479 if (length > 0)
1480 chip->write_buf(mtd, bufpoi, length);
1481
1482 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1483 status = chip->waitfunc(mtd, chip);
1484
1485 return status & NAND_STATUS_FAIL ? -EIO : 0;
1486 }
1487
1488 /**
1489 * nand_do_read_oob - [Intern] NAND read out-of-band
1490 * @mtd: MTD device structure
1491 * @from: offset to read from
1492 * @ops: oob operations description structure
1493 *
1494 * NAND read out-of-band data from the spare area
1495 */
1496 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1497 struct mtd_oob_ops *ops)
1498 {
1499 int page, realpage, chipnr, sndcmd = 1;
1500 struct nand_chip *chip = mtd->priv;
1501 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1502 int readlen = ops->ooblen;
1503 int len;
1504 uint8_t *buf = ops->oobbuf;
1505
1506 MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08Lx, len = %i\n",
1507 (unsigned long long)from, readlen);
1508
1509 if (ops->mode == MTD_OOB_AUTO)
1510 len = chip->ecc.layout->oobavail;
1511 else
1512 len = mtd->oobsize;
1513
1514 if (unlikely(ops->ooboffs >= len)) {
1515 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1516 "Attempt to start read outside oob\n");
1517 return -EINVAL;
1518 }
1519
1520 /* Do not allow reads past end of device */
1521 if (unlikely(from >= mtd->size ||
1522 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1523 (from >> chip->page_shift)) * len)) {
1524 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1525 "Attempt read beyond end of device\n");
1526 return -EINVAL;
1527 }
1528
1529 chipnr = (int)(from >> chip->chip_shift);
1530 chip->select_chip(mtd, chipnr);
1531
1532 /* Shift to get page */
1533 realpage = (int)(from >> chip->page_shift);
1534 page = realpage & chip->pagemask;
1535
1536 while(1) {
1537 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1538
1539 len = min(len, readlen);
1540 buf = nand_transfer_oob(chip, buf, ops, len);
1541
1542 if (!(chip->options & NAND_NO_READRDY)) {
1543 /*
1544 * Apply delay or wait for ready/busy pin. Do this
1545 * before the AUTOINCR check, so no problems arise if a
1546 * chip which does auto increment is marked as
1547 * NOAUTOINCR by the board driver.
1548 */
1549 if (!chip->dev_ready)
1550 udelay(chip->chip_delay);
1551 else
1552 nand_wait_ready(mtd);
1553 }
1554
1555 readlen -= len;
1556 if (!readlen)
1557 break;
1558
1559 /* Increment page address */
1560 realpage++;
1561
1562 page = realpage & chip->pagemask;
1563 /* Check, if we cross a chip boundary */
1564 if (!page) {
1565 chipnr++;
1566 chip->select_chip(mtd, -1);
1567 chip->select_chip(mtd, chipnr);
1568 }
1569
1570 /* Check, if the chip supports auto page increment
1571 * or if we have hit a block boundary.
1572 */
1573 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1574 sndcmd = 1;
1575 }
1576
1577 ops->oobretlen = ops->ooblen;
1578 return 0;
1579 }
1580
1581 /**
1582 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1583 * @mtd: MTD device structure
1584 * @from: offset to read from
1585 * @ops: oob operation description structure
1586 *
1587 * NAND read data and/or out-of-band data
1588 */
1589 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1590 struct mtd_oob_ops *ops)
1591 {
1592 struct nand_chip *chip = mtd->priv;
1593 int ret = -ENOTSUPP;
1594
1595 ops->retlen = 0;
1596
1597 /* Do not allow reads past end of device */
1598 if (ops->datbuf && (from + ops->len) > mtd->size) {
1599 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1600 "Attempt read beyond end of device\n");
1601 return -EINVAL;
1602 }
1603
1604 nand_get_device(chip, mtd, FL_READING);
1605
1606 switch(ops->mode) {
1607 case MTD_OOB_PLACE:
1608 case MTD_OOB_AUTO:
1609 case MTD_OOB_RAW:
1610 break;
1611
1612 default:
1613 goto out;
1614 }
1615
1616 if (!ops->datbuf)
1617 ret = nand_do_read_oob(mtd, from, ops);
1618 else
1619 ret = nand_do_read_ops(mtd, from, ops);
1620
1621 out:
1622 nand_release_device(mtd);
1623 return ret;
1624 }
1625
1626
1627 /**
1628 * nand_write_page_raw - [Intern] raw page write function
1629 * @mtd: mtd info structure
1630 * @chip: nand chip info structure
1631 * @buf: data buffer
1632 */
1633 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1634 const uint8_t *buf)
1635 {
1636 chip->write_buf(mtd, buf, mtd->writesize);
1637 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1638 }
1639
1640 /**
1641 * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
1642 * @mtd: mtd info structure
1643 * @chip: nand chip info structure
1644 * @buf: data buffer
1645 */
1646 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1647 const uint8_t *buf)
1648 {
1649 int i, eccsize = chip->ecc.size;
1650 int eccbytes = chip->ecc.bytes;
1651 int eccsteps = chip->ecc.steps;
1652 uint8_t *ecc_calc = chip->buffers->ecccalc;
1653 const uint8_t *p = buf;
1654 uint32_t *eccpos = chip->ecc.layout->eccpos;
1655
1656 /* Software ecc calculation */
1657 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1658 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1659
1660 for (i = 0; i < chip->ecc.total; i++)
1661 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1662
1663 chip->ecc.write_page_raw(mtd, chip, buf);
1664 }
1665
1666 /**
1667 * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
1668 * @mtd: mtd info structure
1669 * @chip: nand chip info structure
1670 * @buf: data buffer
1671 */
1672 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1673 const uint8_t *buf)
1674 {
1675 int i, eccsize = chip->ecc.size;
1676 int eccbytes = chip->ecc.bytes;
1677 int eccsteps = chip->ecc.steps;
1678 uint8_t *ecc_calc = chip->buffers->ecccalc;
1679 const uint8_t *p = buf;
1680 uint32_t *eccpos = chip->ecc.layout->eccpos;
1681
1682 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1683 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1684 chip->write_buf(mtd, p, eccsize);
1685 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1686 }
1687
1688 for (i = 0; i < chip->ecc.total; i++)
1689 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1690
1691 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1692 }
1693
1694 /**
1695 * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
1696 * @mtd: mtd info structure
1697 * @chip: nand chip info structure
1698 * @buf: data buffer
1699 *
1700 * The hw generator calculates the error syndrome automatically. Therefor
1701 * we need a special oob layout and handling.
1702 */
1703 static void nand_write_page_syndrome(struct mtd_info *mtd,
1704 struct nand_chip *chip, const uint8_t *buf)
1705 {
1706 int i, eccsize = chip->ecc.size;
1707 int eccbytes = chip->ecc.bytes;
1708 int eccsteps = chip->ecc.steps;
1709 const uint8_t *p = buf;
1710 uint8_t *oob = chip->oob_poi;
1711
1712 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1713
1714 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1715 chip->write_buf(mtd, p, eccsize);
1716
1717 if (chip->ecc.prepad) {
1718 chip->write_buf(mtd, oob, chip->ecc.prepad);
1719 oob += chip->ecc.prepad;
1720 }
1721
1722 chip->ecc.calculate(mtd, p, oob);
1723 chip->write_buf(mtd, oob, eccbytes);
1724 oob += eccbytes;
1725
1726 if (chip->ecc.postpad) {
1727 chip->write_buf(mtd, oob, chip->ecc.postpad);
1728 oob += chip->ecc.postpad;
1729 }
1730 }
1731
1732 /* Calculate remaining oob bytes */
1733 i = mtd->oobsize - (oob - chip->oob_poi);
1734 if (i)
1735 chip->write_buf(mtd, oob, i);
1736 }
1737
1738 /**
1739 * nand_write_page - [REPLACEABLE] write one page
1740 * @mtd: MTD device structure
1741 * @chip: NAND chip descriptor
1742 * @buf: the data to write
1743 * @page: page number to write
1744 * @cached: cached programming
1745 * @raw: use _raw version of write_page
1746 */
1747 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1748 const uint8_t *buf, int page, int cached, int raw)
1749 {
1750 int status;
1751
1752 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1753
1754 if (unlikely(raw))
1755 chip->ecc.write_page_raw(mtd, chip, buf);
1756 else
1757 chip->ecc.write_page(mtd, chip, buf);
1758
1759 /*
1760 * Cached progamming disabled for now, Not sure if its worth the
1761 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
1762 */
1763 cached = 0;
1764
1765 if (!cached || !(chip->options & NAND_CACHEPRG)) {
1766
1767 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1768 status = chip->waitfunc(mtd, chip);
1769 /*
1770 * See if operation failed and additional status checks are
1771 * available
1772 */
1773 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1774 status = chip->errstat(mtd, chip, FL_WRITING, status,
1775 page);
1776
1777 if (status & NAND_STATUS_FAIL)
1778 return -EIO;
1779 } else {
1780 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
1781 status = chip->waitfunc(mtd, chip);
1782 }
1783
1784 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1785 /* Send command to read back the data */
1786 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1787
1788 if (chip->verify_buf(mtd, buf, mtd->writesize))
1789 return -EIO;
1790 #endif
1791 return 0;
1792 }
1793
1794 /**
1795 * nand_fill_oob - [Internal] Transfer client buffer to oob
1796 * @chip: nand chip structure
1797 * @oob: oob data buffer
1798 * @ops: oob ops structure
1799 */
1800 static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob,
1801 struct mtd_oob_ops *ops)
1802 {
1803 size_t len = ops->ooblen;
1804
1805 switch(ops->mode) {
1806
1807 case MTD_OOB_PLACE:
1808 case MTD_OOB_RAW:
1809 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
1810 return oob + len;
1811
1812 case MTD_OOB_AUTO: {
1813 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1814 uint32_t boffs = 0, woffs = ops->ooboffs;
1815 size_t bytes = 0;
1816
1817 for(; free->length && len; free++, len -= bytes) {
1818 /* Write request not from offset 0 ? */
1819 if (unlikely(woffs)) {
1820 if (woffs >= free->length) {
1821 woffs -= free->length;
1822 continue;
1823 }
1824 boffs = free->offset + woffs;
1825 bytes = min_t(size_t, len,
1826 (free->length - woffs));
1827 woffs = 0;
1828 } else {
1829 bytes = min_t(size_t, len, free->length);
1830 boffs = free->offset;
1831 }
1832 memcpy(chip->oob_poi + boffs, oob, bytes);
1833 oob += bytes;
1834 }
1835 return oob;
1836 }
1837 default:
1838 BUG();
1839 }
1840 return NULL;
1841 }
1842
1843 #define NOTALIGNED(x) (x & (chip->subpagesize - 1)) != 0
1844
1845 /**
1846 * nand_do_write_ops - [Internal] NAND write with ECC
1847 * @mtd: MTD device structure
1848 * @to: offset to write to
1849 * @ops: oob operations description structure
1850 *
1851 * NAND write with ECC
1852 */
1853 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
1854 struct mtd_oob_ops *ops)
1855 {
1856 int chipnr, realpage, page, blockmask, column;
1857 struct nand_chip *chip = mtd->priv;
1858 uint32_t writelen = ops->len;
1859 uint8_t *oob = ops->oobbuf;
1860 uint8_t *buf = ops->datbuf;
1861 int ret, subpage;
1862
1863 ops->retlen = 0;
1864 if (!writelen)
1865 return 0;
1866
1867 /* reject writes, which are not page aligned */
1868 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
1869 printk(KERN_NOTICE "nand_write: "
1870 "Attempt to write not page aligned data\n");
1871 return -EINVAL;
1872 }
1873
1874 column = to & (mtd->writesize - 1);
1875 subpage = column || (writelen & (mtd->writesize - 1));
1876
1877 if (subpage && oob)
1878 return -EINVAL;
1879
1880 chipnr = (int)(to >> chip->chip_shift);
1881 chip->select_chip(mtd, chipnr);
1882
1883 /* Check, if it is write protected */
1884 if (nand_check_wp(mtd)) {
1885 printk (KERN_NOTICE "nand_do_write_ops: Device is write protected\n");
1886 return -EIO;
1887 }
1888
1889 realpage = (int)(to >> chip->page_shift);
1890 page = realpage & chip->pagemask;
1891 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1892
1893 /* Invalidate the page cache, when we write to the cached page */
1894 if (to <= (chip->pagebuf << chip->page_shift) &&
1895 (chip->pagebuf << chip->page_shift) < (to + ops->len))
1896 chip->pagebuf = -1;
1897
1898 /* If we're not given explicit OOB data, let it be 0xFF */
1899 if (likely(!oob))
1900 memset(chip->oob_poi, 0xff, mtd->oobsize);
1901
1902 while(1) {
1903 int bytes = mtd->writesize;
1904 int cached = writelen > bytes && page != blockmask;
1905 uint8_t *wbuf = buf;
1906
1907 /* Partial page write ? */
1908 if (unlikely(column || writelen < (mtd->writesize - 1))) {
1909 cached = 0;
1910 bytes = min_t(int, bytes - column, (int) writelen);
1911 chip->pagebuf = -1;
1912 memset(chip->buffers->databuf, 0xff, mtd->writesize);
1913 memcpy(&chip->buffers->databuf[column], buf, bytes);
1914 wbuf = chip->buffers->databuf;
1915 }
1916
1917 if (unlikely(oob))
1918 oob = nand_fill_oob(chip, oob, ops);
1919
1920 ret = chip->write_page(mtd, chip, wbuf, page, cached,
1921 (ops->mode == MTD_OOB_RAW));
1922 if (ret)
1923 break;
1924
1925 writelen -= bytes;
1926 if (!writelen)
1927 break;
1928
1929 column = 0;
1930 buf += bytes;
1931 realpage++;
1932
1933 page = realpage & chip->pagemask;
1934 /* Check, if we cross a chip boundary */
1935 if (!page) {
1936 chipnr++;
1937 chip->select_chip(mtd, -1);
1938 chip->select_chip(mtd, chipnr);
1939 }
1940 }
1941
1942 ops->retlen = ops->len - writelen;
1943 if (unlikely(oob))
1944 ops->oobretlen = ops->ooblen;
1945 return ret;
1946 }
1947
1948 /**
1949 * nand_write - [MTD Interface] NAND write with ECC
1950 * @mtd: MTD device structure
1951 * @to: offset to write to
1952 * @len: number of bytes to write
1953 * @retlen: pointer to variable to store the number of written bytes
1954 * @buf: the data to write
1955 *
1956 * NAND write with ECC
1957 */
1958 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
1959 size_t *retlen, const uint8_t *buf)
1960 {
1961 struct nand_chip *chip = mtd->priv;
1962 int ret;
1963
1964 /* Do not allow reads past end of device */
1965 if ((to + len) > mtd->size)
1966 return -EINVAL;
1967 if (!len)
1968 return 0;
1969
1970 nand_get_device(chip, mtd, FL_WRITING);
1971
1972 chip->ops.len = len;
1973 chip->ops.datbuf = (uint8_t *)buf;
1974 chip->ops.oobbuf = NULL;
1975
1976 ret = nand_do_write_ops(mtd, to, &chip->ops);
1977
1978 *retlen = chip->ops.retlen;
1979
1980 nand_release_device(mtd);
1981
1982 return ret;
1983 }
1984
1985 /**
1986 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
1987 * @mtd: MTD device structure
1988 * @to: offset to write to
1989 * @ops: oob operation description structure
1990 *
1991 * NAND write out-of-band
1992 */
1993 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
1994 struct mtd_oob_ops *ops)
1995 {
1996 int chipnr, page, status, len;
1997 struct nand_chip *chip = mtd->priv;
1998
1999 MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n",
2000 (unsigned int)to, (int)ops->ooblen);
2001
2002 if (ops->mode == MTD_OOB_AUTO)
2003 len = chip->ecc.layout->oobavail;
2004 else
2005 len = mtd->oobsize;
2006
2007 /* Do not allow write past end of page */
2008 if ((ops->ooboffs + ops->ooblen) > len) {
2009 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: "
2010 "Attempt to write past end of page\n");
2011 return -EINVAL;
2012 }
2013
2014 if (unlikely(ops->ooboffs >= len)) {
2015 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
2016 "Attempt to start write outside oob\n");
2017 return -EINVAL;
2018 }
2019
2020 /* Do not allow reads past end of device */
2021 if (unlikely(to >= mtd->size ||
2022 ops->ooboffs + ops->ooblen >
2023 ((mtd->size >> chip->page_shift) -
2024 (to >> chip->page_shift)) * len)) {
2025 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
2026 "Attempt write beyond end of device\n");
2027 return -EINVAL;
2028 }
2029
2030 chipnr = (int)(to >> chip->chip_shift);
2031 chip->select_chip(mtd, chipnr);
2032
2033 /* Shift to get page */
2034 page = (int)(to >> chip->page_shift);
2035
2036 /*
2037 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2038 * of my DiskOnChip 2000 test units) will clear the whole data page too
2039 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2040 * it in the doc2000 driver in August 1999. dwmw2.
2041 */
2042 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2043
2044 /* Check, if it is write protected */
2045 if (nand_check_wp(mtd))
2046 return -EROFS;
2047
2048 /* Invalidate the page cache, if we write to the cached page */
2049 if (page == chip->pagebuf)
2050 chip->pagebuf = -1;
2051
2052 memset(chip->oob_poi, 0xff, mtd->oobsize);
2053 nand_fill_oob(chip, ops->oobbuf, ops);
2054 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2055 memset(chip->oob_poi, 0xff, mtd->oobsize);
2056
2057 if (status)
2058 return status;
2059
2060 ops->oobretlen = ops->ooblen;
2061
2062 return 0;
2063 }
2064
2065 /**
2066 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2067 * @mtd: MTD device structure
2068 * @to: offset to write to
2069 * @ops: oob operation description structure
2070 */
2071 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2072 struct mtd_oob_ops *ops)
2073 {
2074 struct nand_chip *chip = mtd->priv;
2075 int ret = -ENOTSUPP;
2076
2077 ops->retlen = 0;
2078
2079 /* Do not allow writes past end of device */
2080 if (ops->datbuf && (to + ops->len) > mtd->size) {
2081 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
2082 "Attempt read beyond end of device\n");
2083 return -EINVAL;
2084 }
2085
2086 nand_get_device(chip, mtd, FL_WRITING);
2087
2088 switch(ops->mode) {
2089 case MTD_OOB_PLACE:
2090 case MTD_OOB_AUTO:
2091 case MTD_OOB_RAW:
2092 break;
2093
2094 default:
2095 goto out;
2096 }
2097
2098 if (!ops->datbuf)
2099 ret = nand_do_write_oob(mtd, to, ops);
2100 else
2101 ret = nand_do_write_ops(mtd, to, ops);
2102
2103 out:
2104 nand_release_device(mtd);
2105 return ret;
2106 }
2107
2108 /**
2109 * single_erease_cmd - [GENERIC] NAND standard block erase command function
2110 * @mtd: MTD device structure
2111 * @page: the page address of the block which will be erased
2112 *
2113 * Standard erase command for NAND chips
2114 */
2115 static void single_erase_cmd(struct mtd_info *mtd, int page)
2116 {
2117 struct nand_chip *chip = mtd->priv;
2118 /* Send commands to erase a block */
2119 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2120 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2121 }
2122
2123 /**
2124 * multi_erease_cmd - [GENERIC] AND specific block erase command function
2125 * @mtd: MTD device structure
2126 * @page: the page address of the block which will be erased
2127 *
2128 * AND multi block erase command function
2129 * Erase 4 consecutive blocks
2130 */
2131 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2132 {
2133 struct nand_chip *chip = mtd->priv;
2134 /* Send commands to erase a block */
2135 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2136 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2137 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2138 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2139 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2140 }
2141
2142 /**
2143 * nand_erase - [MTD Interface] erase block(s)
2144 * @mtd: MTD device structure
2145 * @instr: erase instruction
2146 *
2147 * Erase one ore more blocks
2148 */
2149 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2150 {
2151 return nand_erase_nand(mtd, instr, 0);
2152 }
2153
2154 #define BBT_PAGE_MASK 0xffffff3f
2155 /**
2156 * nand_erase_nand - [Internal] erase block(s)
2157 * @mtd: MTD device structure
2158 * @instr: erase instruction
2159 * @allowbbt: allow erasing the bbt area
2160 *
2161 * Erase one ore more blocks
2162 */
2163 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2164 int allowbbt)
2165 {
2166 int page, len, status, pages_per_block, ret, chipnr;
2167 struct nand_chip *chip = mtd->priv;
2168 int rewrite_bbt[CONFIG_SYS_NAND_MAX_CHIPS]={0};
2169 unsigned int bbt_masked_page = 0xffffffff;
2170
2171 MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%08x, len = %i\n",
2172 (unsigned int) instr->addr, (unsigned int) instr->len);
2173
2174 /* Start address must align on block boundary */
2175 if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) {
2176 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n");
2177 return -EINVAL;
2178 }
2179
2180 /* Length must align on block boundary */
2181 if (instr->len & ((1 << chip->phys_erase_shift) - 1)) {
2182 MTDDEBUG (MTD_DEBUG_LEVEL0,
2183 "nand_erase: Length not block aligned\n");
2184 return -EINVAL;
2185 }
2186
2187 /* Do not allow erase past end of device */
2188 if ((instr->len + instr->addr) > mtd->size) {
2189 MTDDEBUG (MTD_DEBUG_LEVEL0,
2190 "nand_erase: Erase past end of device\n");
2191 return -EINVAL;
2192 }
2193
2194 instr->fail_addr = 0xffffffff;
2195
2196 /* Grab the lock and see if the device is available */
2197 nand_get_device(chip, mtd, FL_ERASING);
2198
2199 /* Shift to get first page */
2200 page = (int)(instr->addr >> chip->page_shift);
2201 chipnr = (int)(instr->addr >> chip->chip_shift);
2202
2203 /* Calculate pages in each block */
2204 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2205
2206 /* Select the NAND device */
2207 chip->select_chip(mtd, chipnr);
2208
2209 /* Check, if it is write protected */
2210 if (nand_check_wp(mtd)) {
2211 MTDDEBUG (MTD_DEBUG_LEVEL0,
2212 "nand_erase: Device is write protected!!!\n");
2213 instr->state = MTD_ERASE_FAILED;
2214 goto erase_exit;
2215 }
2216
2217 /*
2218 * If BBT requires refresh, set the BBT page mask to see if the BBT
2219 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2220 * can not be matched. This is also done when the bbt is actually
2221 * erased to avoid recusrsive updates
2222 */
2223 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2224 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2225
2226 /* Loop through the pages */
2227 len = instr->len;
2228
2229 instr->state = MTD_ERASING;
2230
2231 while (len) {
2232 /*
2233 * heck if we have a bad block, we do not erase bad blocks !
2234 */
2235 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2236 chip->page_shift, 0, allowbbt)) {
2237 printk(KERN_WARNING "nand_erase: attempt to erase a "
2238 "bad block at page 0x%08x\n", page);
2239 instr->state = MTD_ERASE_FAILED;
2240 goto erase_exit;
2241 }
2242
2243 /*
2244 * Invalidate the page cache, if we erase the block which
2245 * contains the current cached page
2246 */
2247 if (page <= chip->pagebuf && chip->pagebuf <
2248 (page + pages_per_block))
2249 chip->pagebuf = -1;
2250
2251 chip->erase_cmd(mtd, page & chip->pagemask);
2252
2253 status = chip->waitfunc(mtd, chip);
2254
2255 /*
2256 * See if operation failed and additional status checks are
2257 * available
2258 */
2259 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2260 status = chip->errstat(mtd, chip, FL_ERASING,
2261 status, page);
2262
2263 /* See if block erase succeeded */
2264 if (status & NAND_STATUS_FAIL) {
2265 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: "
2266 "Failed erase, page 0x%08x\n", page);
2267 instr->state = MTD_ERASE_FAILED;
2268 instr->fail_addr = (page << chip->page_shift);
2269 goto erase_exit;
2270 }
2271
2272 /*
2273 * If BBT requires refresh, set the BBT rewrite flag to the
2274 * page being erased
2275 */
2276 if (bbt_masked_page != 0xffffffff &&
2277 (page & BBT_PAGE_MASK) == bbt_masked_page)
2278 rewrite_bbt[chipnr] = (page << chip->page_shift);
2279
2280 /* Increment page address and decrement length */
2281 len -= (1 << chip->phys_erase_shift);
2282 page += pages_per_block;
2283
2284 /* Check, if we cross a chip boundary */
2285 if (len && !(page & chip->pagemask)) {
2286 chipnr++;
2287 chip->select_chip(mtd, -1);
2288 chip->select_chip(mtd, chipnr);
2289
2290 /*
2291 * If BBT requires refresh and BBT-PERCHIP, set the BBT
2292 * page mask to see if this BBT should be rewritten
2293 */
2294 if (bbt_masked_page != 0xffffffff &&
2295 (chip->bbt_td->options & NAND_BBT_PERCHIP))
2296 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2297 BBT_PAGE_MASK;
2298 }
2299 }
2300 instr->state = MTD_ERASE_DONE;
2301
2302 erase_exit:
2303
2304 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2305
2306 /* Deselect and wake up anyone waiting on the device */
2307 nand_release_device(mtd);
2308
2309 /* Do call back function */
2310 if (!ret)
2311 mtd_erase_callback(instr);
2312
2313 /*
2314 * If BBT requires refresh and erase was successful, rewrite any
2315 * selected bad block tables
2316 */
2317 if (bbt_masked_page == 0xffffffff || ret)
2318 return ret;
2319
2320 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2321 if (!rewrite_bbt[chipnr])
2322 continue;
2323 /* update the BBT for chip */
2324 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase_nand: nand_update_bbt "
2325 "(%d:0x%0x 0x%0x)\n", chipnr, rewrite_bbt[chipnr],
2326 chip->bbt_td->pages[chipnr]);
2327 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2328 }
2329
2330 /* Return more or less happy */
2331 return ret;
2332 }
2333
2334 /**
2335 * nand_sync - [MTD Interface] sync
2336 * @mtd: MTD device structure
2337 *
2338 * Sync is actually a wait for chip ready function
2339 */
2340 static void nand_sync(struct mtd_info *mtd)
2341 {
2342 struct nand_chip *chip = mtd->priv;
2343
2344 MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_sync: called\n");
2345
2346 /* Grab the lock and see if the device is available */
2347 nand_get_device(chip, mtd, FL_SYNCING);
2348 /* Release it and go back */
2349 nand_release_device(mtd);
2350 }
2351
2352 /**
2353 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2354 * @mtd: MTD device structure
2355 * @offs: offset relative to mtd start
2356 */
2357 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2358 {
2359 /* Check for invalid offset */
2360 if (offs > mtd->size)
2361 return -EINVAL;
2362
2363 return nand_block_checkbad(mtd, offs, 1, 0);
2364 }
2365
2366 /**
2367 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2368 * @mtd: MTD device structure
2369 * @ofs: offset relative to mtd start
2370 */
2371 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2372 {
2373 struct nand_chip *chip = mtd->priv;
2374 int ret;
2375
2376 if ((ret = nand_block_isbad(mtd, ofs))) {
2377 /* If it was bad already, return success and do nothing. */
2378 if (ret > 0)
2379 return 0;
2380 return ret;
2381 }
2382
2383 return chip->block_markbad(mtd, ofs);
2384 }
2385
2386 /**
2387 * nand_suspend - [MTD Interface] Suspend the NAND flash
2388 * @mtd: MTD device structure
2389 */
2390 static int nand_suspend(struct mtd_info *mtd)
2391 {
2392 struct nand_chip *chip = mtd->priv;
2393
2394 return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
2395 }
2396
2397 /**
2398 * nand_resume - [MTD Interface] Resume the NAND flash
2399 * @mtd: MTD device structure
2400 */
2401 static void nand_resume(struct mtd_info *mtd)
2402 {
2403 struct nand_chip *chip = mtd->priv;
2404
2405 if (chip->state == FL_PM_SUSPENDED)
2406 nand_release_device(mtd);
2407 else
2408 printk(KERN_ERR "nand_resume() called for a chip which is not "
2409 "in suspended state\n");
2410 }
2411
2412 /*
2413 * Set default functions
2414 */
2415 static void nand_set_defaults(struct nand_chip *chip, int busw)
2416 {
2417 /* check for proper chip_delay setup, set 20us if not */
2418 if (!chip->chip_delay)
2419 chip->chip_delay = 20;
2420
2421 /* check, if a user supplied command function given */
2422 if (chip->cmdfunc == NULL)
2423 chip->cmdfunc = nand_command;
2424
2425 /* check, if a user supplied wait function given */
2426 if (chip->waitfunc == NULL)
2427 chip->waitfunc = nand_wait;
2428
2429 if (!chip->select_chip)
2430 chip->select_chip = nand_select_chip;
2431 if (!chip->read_byte)
2432 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2433 if (!chip->read_word)
2434 chip->read_word = nand_read_word;
2435 if (!chip->block_bad)
2436 chip->block_bad = nand_block_bad;
2437 if (!chip->block_markbad)
2438 chip->block_markbad = nand_default_block_markbad;
2439 if (!chip->write_buf)
2440 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2441 if (!chip->read_buf)
2442 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2443 if (!chip->verify_buf)
2444 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2445 if (!chip->scan_bbt)
2446 chip->scan_bbt = nand_default_bbt;
2447
2448 if (!chip->controller) {
2449 chip->controller = &chip->hwcontrol;
2450
2451 /* XXX U-BOOT XXX */
2452 #if 0
2453 spin_lock_init(&chip->controller->lock);
2454 init_waitqueue_head(&chip->controller->wq);
2455 #endif
2456 }
2457
2458 }
2459
2460 /*
2461 * Get the flash and manufacturer id and lookup if the type is supported
2462 */
2463 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2464 struct nand_chip *chip,
2465 int busw, int *maf_id)
2466 {
2467 struct nand_flash_dev *type = NULL;
2468 int i, dev_id, maf_idx;
2469 int tmp_id, tmp_manf;
2470
2471 /* Select the device */
2472 chip->select_chip(mtd, 0);
2473
2474 /*
2475 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2476 * after power-up
2477 */
2478 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2479
2480 /* Send the command for reading device ID */
2481 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2482
2483 /* Read manufacturer and device IDs */
2484 *maf_id = chip->read_byte(mtd);
2485 dev_id = chip->read_byte(mtd);
2486
2487 /* Try again to make sure, as some systems the bus-hold or other
2488 * interface concerns can cause random data which looks like a
2489 * possibly credible NAND flash to appear. If the two results do
2490 * not match, ignore the device completely.
2491 */
2492
2493 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2494
2495 /* Read manufacturer and device IDs */
2496
2497 tmp_manf = chip->read_byte(mtd);
2498 tmp_id = chip->read_byte(mtd);
2499
2500 if (tmp_manf != *maf_id || tmp_id != dev_id) {
2501 printk(KERN_INFO "%s: second ID read did not match "
2502 "%02x,%02x against %02x,%02x\n", __func__,
2503 *maf_id, dev_id, tmp_manf, tmp_id);
2504 return ERR_PTR(-ENODEV);
2505 }
2506
2507 /* Lookup the flash id */
2508 for (i = 0; nand_flash_ids[i].name != NULL; i++) {
2509 if (dev_id == nand_flash_ids[i].id) {
2510 type = &nand_flash_ids[i];
2511 break;
2512 }
2513 }
2514
2515 if (!type)
2516 return ERR_PTR(-ENODEV);
2517
2518 if (!mtd->name)
2519 mtd->name = type->name;
2520
2521 chip->chipsize = type->chipsize << 20;
2522
2523 /* Newer devices have all the information in additional id bytes */
2524 if (!type->pagesize) {
2525 int extid;
2526 /* The 3rd id byte holds MLC / multichip data */
2527 chip->cellinfo = chip->read_byte(mtd);
2528 /* The 4th id byte is the important one */
2529 extid = chip->read_byte(mtd);
2530 /* Calc pagesize */
2531 mtd->writesize = 1024 << (extid & 0x3);
2532 extid >>= 2;
2533 /* Calc oobsize */
2534 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
2535 extid >>= 2;
2536 /* Calc blocksize. Blocksize is multiples of 64KiB */
2537 mtd->erasesize = (64 * 1024) << (extid & 0x03);
2538 extid >>= 2;
2539 /* Get buswidth information */
2540 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
2541
2542 } else {
2543 /*
2544 * Old devices have chip data hardcoded in the device id table
2545 */
2546 mtd->erasesize = type->erasesize;
2547 mtd->writesize = type->pagesize;
2548 mtd->oobsize = mtd->writesize / 32;
2549 busw = type->options & NAND_BUSWIDTH_16;
2550 }
2551
2552 /* Try to identify manufacturer */
2553 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
2554 if (nand_manuf_ids[maf_idx].id == *maf_id)
2555 break;
2556 }
2557
2558 /*
2559 * Check, if buswidth is correct. Hardware drivers should set
2560 * chip correct !
2561 */
2562 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
2563 printk(KERN_INFO "NAND device: Manufacturer ID:"
2564 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2565 dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2566 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
2567 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
2568 busw ? 16 : 8);
2569 return ERR_PTR(-EINVAL);
2570 }
2571
2572 /* Calculate the address shift from the page size */
2573 chip->page_shift = ffs(mtd->writesize) - 1;
2574 /* Convert chipsize to number of pages per chip -1. */
2575 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2576
2577 chip->bbt_erase_shift = chip->phys_erase_shift =
2578 ffs(mtd->erasesize) - 1;
2579 chip->chip_shift = ffs(chip->chipsize) - 1;
2580
2581 /* Set the bad block position */
2582 chip->badblockpos = mtd->writesize > 512 ?
2583 NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
2584
2585 /* Get chip options, preserve non chip based options */
2586 chip->options &= ~NAND_CHIPOPTIONS_MSK;
2587 chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
2588
2589 /*
2590 * Set chip as a default. Board drivers can override it, if necessary
2591 */
2592 chip->options |= NAND_NO_AUTOINCR;
2593
2594 /* Check if chip is a not a samsung device. Do not clear the
2595 * options for chips which are not having an extended id.
2596 */
2597 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
2598 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
2599
2600 /* Check for AND chips with 4 page planes */
2601 if (chip->options & NAND_4PAGE_ARRAY)
2602 chip->erase_cmd = multi_erase_cmd;
2603 else
2604 chip->erase_cmd = single_erase_cmd;
2605
2606 /* Do not replace user supplied command function ! */
2607 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
2608 chip->cmdfunc = nand_command_lp;
2609
2610 MTDDEBUG (MTD_DEBUG_LEVEL0, "NAND device: Manufacturer ID:"
2611 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id,
2612 nand_manuf_ids[maf_idx].name, type->name);
2613
2614 return type;
2615 }
2616
2617 /**
2618 * nand_scan_ident - [NAND Interface] Scan for the NAND device
2619 * @mtd: MTD device structure
2620 * @maxchips: Number of chips to scan for
2621 *
2622 * This is the first phase of the normal nand_scan() function. It
2623 * reads the flash ID and sets up MTD fields accordingly.
2624 *
2625 * The mtd->owner field must be set to the module of the caller.
2626 */
2627 int nand_scan_ident(struct mtd_info *mtd, int maxchips)
2628 {
2629 int i, busw, nand_maf_id;
2630 struct nand_chip *chip = mtd->priv;
2631 struct nand_flash_dev *type;
2632
2633 /* Get buswidth to select the correct functions */
2634 busw = chip->options & NAND_BUSWIDTH_16;
2635 /* Set the default functions */
2636 nand_set_defaults(chip, busw);
2637
2638 /* Read the flash type */
2639 type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id);
2640
2641 if (IS_ERR(type)) {
2642 #ifndef CONFIG_SYS_NAND_QUIET_TEST
2643 printk(KERN_WARNING "No NAND device found!!!\n");
2644 #endif
2645 chip->select_chip(mtd, -1);
2646 return PTR_ERR(type);
2647 }
2648
2649 /* Check for a chip array */
2650 for (i = 1; i < maxchips; i++) {
2651 chip->select_chip(mtd, i);
2652 /* See comment in nand_get_flash_type for reset */
2653 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2654 /* Send the command for reading device ID */
2655 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2656 /* Read manufacturer and device IDs */
2657 if (nand_maf_id != chip->read_byte(mtd) ||
2658 type->id != chip->read_byte(mtd))
2659 break;
2660 }
2661 #ifdef DEBUG
2662 if (i > 1)
2663 printk(KERN_INFO "%d NAND chips detected\n", i);
2664 #endif
2665
2666 /* Store the number of chips and calc total size for mtd */
2667 chip->numchips = i;
2668 mtd->size = i * chip->chipsize;
2669
2670 return 0;
2671 }
2672
2673
2674 /**
2675 * nand_scan_tail - [NAND Interface] Scan for the NAND device
2676 * @mtd: MTD device structure
2677 * @maxchips: Number of chips to scan for
2678 *
2679 * This is the second phase of the normal nand_scan() function. It
2680 * fills out all the uninitialized function pointers with the defaults
2681 * and scans for a bad block table if appropriate.
2682 */
2683 int nand_scan_tail(struct mtd_info *mtd)
2684 {
2685 int i;
2686 struct nand_chip *chip = mtd->priv;
2687
2688 if (!(chip->options & NAND_OWN_BUFFERS))
2689 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
2690 if (!chip->buffers)
2691 return -ENOMEM;
2692
2693 /* Set the internal oob buffer location, just after the page data */
2694 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
2695
2696 /*
2697 * If no default placement scheme is given, select an appropriate one
2698 */
2699 if (!chip->ecc.layout) {
2700 switch (mtd->oobsize) {
2701 case 8:
2702 chip->ecc.layout = &nand_oob_8;
2703 break;
2704 case 16:
2705 chip->ecc.layout = &nand_oob_16;
2706 break;
2707 case 64:
2708 chip->ecc.layout = &nand_oob_64;
2709 break;
2710 case 128:
2711 chip->ecc.layout = &nand_oob_128;
2712 break;
2713 default:
2714 printk(KERN_WARNING "No oob scheme defined for "
2715 "oobsize %d\n", mtd->oobsize);
2716 /* BUG(); */
2717 }
2718 }
2719
2720 if (!chip->write_page)
2721 chip->write_page = nand_write_page;
2722
2723 /*
2724 * check ECC mode, default to software if 3byte/512byte hardware ECC is
2725 * selected and we have 256 byte pagesize fallback to software ECC
2726 */
2727 if (!chip->ecc.read_page_raw)
2728 chip->ecc.read_page_raw = nand_read_page_raw;
2729 if (!chip->ecc.write_page_raw)
2730 chip->ecc.write_page_raw = nand_write_page_raw;
2731
2732 switch (chip->ecc.mode) {
2733 case NAND_ECC_HW:
2734 /* Use standard hwecc read page function ? */
2735 if (!chip->ecc.read_page)
2736 chip->ecc.read_page = nand_read_page_hwecc;
2737 if (!chip->ecc.write_page)
2738 chip->ecc.write_page = nand_write_page_hwecc;
2739 if (!chip->ecc.read_oob)
2740 chip->ecc.read_oob = nand_read_oob_std;
2741 if (!chip->ecc.write_oob)
2742 chip->ecc.write_oob = nand_write_oob_std;
2743
2744 case NAND_ECC_HW_SYNDROME:
2745 if ((!chip->ecc.calculate || !chip->ecc.correct ||
2746 !chip->ecc.hwctl) &&
2747 (!chip->ecc.read_page ||
2748 chip->ecc.read_page == nand_read_page_hwecc ||
2749 !chip->ecc.write_page ||
2750 chip->ecc.write_page == nand_write_page_hwecc)) {
2751 printk(KERN_WARNING "No ECC functions supplied, "
2752 "Hardware ECC not possible\n");
2753 BUG();
2754 }
2755 /* Use standard syndrome read/write page function ? */
2756 if (!chip->ecc.read_page)
2757 chip->ecc.read_page = nand_read_page_syndrome;
2758 if (!chip->ecc.write_page)
2759 chip->ecc.write_page = nand_write_page_syndrome;
2760 if (!chip->ecc.read_oob)
2761 chip->ecc.read_oob = nand_read_oob_syndrome;
2762 if (!chip->ecc.write_oob)
2763 chip->ecc.write_oob = nand_write_oob_syndrome;
2764
2765 if (mtd->writesize >= chip->ecc.size)
2766 break;
2767 printk(KERN_WARNING "%d byte HW ECC not possible on "
2768 "%d byte page size, fallback to SW ECC\n",
2769 chip->ecc.size, mtd->writesize);
2770 chip->ecc.mode = NAND_ECC_SOFT;
2771
2772 case NAND_ECC_SOFT:
2773 chip->ecc.calculate = nand_calculate_ecc;
2774 chip->ecc.correct = nand_correct_data;
2775 chip->ecc.read_page = nand_read_page_swecc;
2776 chip->ecc.read_subpage = nand_read_subpage;
2777 chip->ecc.write_page = nand_write_page_swecc;
2778 chip->ecc.read_oob = nand_read_oob_std;
2779 chip->ecc.write_oob = nand_write_oob_std;
2780 chip->ecc.size = 256;
2781 chip->ecc.bytes = 3;
2782 break;
2783
2784 case NAND_ECC_NONE:
2785 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
2786 "This is not recommended !!\n");
2787 chip->ecc.read_page = nand_read_page_raw;
2788 chip->ecc.write_page = nand_write_page_raw;
2789 chip->ecc.read_oob = nand_read_oob_std;
2790 chip->ecc.write_oob = nand_write_oob_std;
2791 chip->ecc.size = mtd->writesize;
2792 chip->ecc.bytes = 0;
2793 break;
2794
2795 default:
2796 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
2797 chip->ecc.mode);
2798 BUG();
2799 }
2800
2801 /*
2802 * The number of bytes available for a client to place data into
2803 * the out of band area
2804 */
2805 chip->ecc.layout->oobavail = 0;
2806 for (i = 0; chip->ecc.layout->oobfree[i].length; i++)
2807 chip->ecc.layout->oobavail +=
2808 chip->ecc.layout->oobfree[i].length;
2809 mtd->oobavail = chip->ecc.layout->oobavail;
2810
2811 /*
2812 * Set the number of read / write steps for one page depending on ECC
2813 * mode
2814 */
2815 chip->ecc.steps = mtd->writesize / chip->ecc.size;
2816 if(chip->ecc.steps * chip->ecc.size != mtd->writesize) {
2817 printk(KERN_WARNING "Invalid ecc parameters\n");
2818 BUG();
2819 }
2820 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
2821
2822 /*
2823 * Allow subpage writes up to ecc.steps. Not possible for MLC
2824 * FLASH.
2825 */
2826 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2827 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
2828 switch(chip->ecc.steps) {
2829 case 2:
2830 mtd->subpage_sft = 1;
2831 break;
2832 case 4:
2833 case 8:
2834 mtd->subpage_sft = 2;
2835 break;
2836 }
2837 }
2838 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
2839
2840 /* Initialize state */
2841 chip->state = FL_READY;
2842
2843 /* De-select the device */
2844 chip->select_chip(mtd, -1);
2845
2846 /* Invalidate the pagebuffer reference */
2847 chip->pagebuf = -1;
2848
2849 /* Fill in remaining MTD driver data */
2850 mtd->type = MTD_NANDFLASH;
2851 mtd->flags = MTD_CAP_NANDFLASH;
2852 mtd->erase = nand_erase;
2853 mtd->point = NULL;
2854 mtd->unpoint = NULL;
2855 mtd->read = nand_read;
2856 mtd->write = nand_write;
2857 mtd->read_oob = nand_read_oob;
2858 mtd->write_oob = nand_write_oob;
2859 mtd->sync = nand_sync;
2860 mtd->lock = NULL;
2861 mtd->unlock = NULL;
2862 mtd->suspend = nand_suspend;
2863 mtd->resume = nand_resume;
2864 mtd->block_isbad = nand_block_isbad;
2865 mtd->block_markbad = nand_block_markbad;
2866
2867 /* propagate ecc.layout to mtd_info */
2868 mtd->ecclayout = chip->ecc.layout;
2869
2870 /* Check, if we should skip the bad block table scan */
2871 if (chip->options & NAND_SKIP_BBTSCAN)
2872 chip->options |= NAND_BBT_SCANNED;
2873
2874 return 0;
2875 }
2876
2877 /* module_text_address() isn't exported, and it's mostly a pointless
2878 test if this is a module _anyway_ -- they'd have to try _really_ hard
2879 to call us from in-kernel code if the core NAND support is modular. */
2880 #ifdef MODULE
2881 #define caller_is_module() (1)
2882 #else
2883 #define caller_is_module() \
2884 module_text_address((unsigned long)__builtin_return_address(0))
2885 #endif
2886
2887 /**
2888 * nand_scan - [NAND Interface] Scan for the NAND device
2889 * @mtd: MTD device structure
2890 * @maxchips: Number of chips to scan for
2891 *
2892 * This fills out all the uninitialized function pointers
2893 * with the defaults.
2894 * The flash ID is read and the mtd/chip structures are
2895 * filled with the appropriate values.
2896 * The mtd->owner field must be set to the module of the caller
2897 *
2898 */
2899 int nand_scan(struct mtd_info *mtd, int maxchips)
2900 {
2901 int ret;
2902
2903 /* Many callers got this wrong, so check for it for a while... */
2904 /* XXX U-BOOT XXX */
2905 #if 0
2906 if (!mtd->owner && caller_is_module()) {
2907 printk(KERN_CRIT "nand_scan() called with NULL mtd->owner!\n");
2908 BUG();
2909 }
2910 #endif
2911
2912 ret = nand_scan_ident(mtd, maxchips);
2913 if (!ret)
2914 ret = nand_scan_tail(mtd);
2915 return ret;
2916 }
2917
2918 /**
2919 * nand_release - [NAND Interface] Free resources held by the NAND device
2920 * @mtd: MTD device structure
2921 */
2922 void nand_release(struct mtd_info *mtd)
2923 {
2924 struct nand_chip *chip = mtd->priv;
2925
2926 #ifdef CONFIG_MTD_PARTITIONS
2927 /* Deregister partitions */
2928 del_mtd_partitions(mtd);
2929 #endif
2930 /* Deregister the device */
2931 /* XXX U-BOOT XXX */
2932 #if 0
2933 del_mtd_device(mtd);
2934 #endif
2935
2936 /* Free bad block table memory */
2937 kfree(chip->bbt);
2938 if (!(chip->options & NAND_OWN_BUFFERS))
2939 kfree(chip->buffers);
2940 }
2941
2942 /* XXX U-BOOT XXX */
2943 #if 0
2944 EXPORT_SYMBOL_GPL(nand_scan);
2945 EXPORT_SYMBOL_GPL(nand_scan_ident);
2946 EXPORT_SYMBOL_GPL(nand_scan_tail);
2947 EXPORT_SYMBOL_GPL(nand_release);
2948
2949 static int __init nand_base_init(void)
2950 {
2951 led_trigger_register_simple("nand-disk", &nand_led_trigger);
2952 return 0;
2953 }
2954
2955 static void __exit nand_base_exit(void)
2956 {
2957 led_trigger_unregister_simple(nand_led_trigger);
2958 }
2959
2960 module_init(nand_base_init);
2961 module_exit(nand_base_exit);
2962
2963 MODULE_LICENSE("GPL");
2964 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>");
2965 MODULE_DESCRIPTION("Generic NAND flash driver code");
2966 #endif
"Das U-Boot" Source Tree