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nand: Move the sub-page read support enable to a flag
[people/ms/u-boot.git] / drivers / mtd / nand / nand_base.c
1 /*
2 * drivers/mtd/nand.c
3 *
4 * Overview:
5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
8 *
9 * Additional technical information is available on
10 * http://www.linux-mtd.infradead.org/doc/nand.html
11 *
12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
14 *
15 * Credits:
16 * David Woodhouse for adding multichip support
17 *
18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
20 *
21 * TODO:
22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
24 * if we have HW ecc support.
25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
27 * BBT table is not serialized, has to be fixed
28 *
29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License version 2 as
31 * published by the Free Software Foundation.
32 *
33 */
34
35 #include <common.h>
36
37 #define ENOTSUPP 524 /* Operation is not supported */
38
39 #include <malloc.h>
40 #include <watchdog.h>
41 #include <linux/err.h>
42 #include <linux/compat.h>
43 #include <linux/mtd/mtd.h>
44 #include <linux/mtd/nand.h>
45 #include <linux/mtd/nand_ecc.h>
46 #include <linux/mtd/nand_bch.h>
47
48 #ifdef CONFIG_MTD_PARTITIONS
49 #include <linux/mtd/partitions.h>
50 #endif
51
52 #include <asm/io.h>
53 #include <asm/errno.h>
54
55 /*
56 * CONFIG_SYS_NAND_RESET_CNT is used as a timeout mechanism when resetting
57 * a flash. NAND flash is initialized prior to interrupts so standard timers
58 * can't be used. CONFIG_SYS_NAND_RESET_CNT should be set to a value
59 * which is greater than (max NAND reset time / NAND status read time).
60 * A conservative default of 200000 (500 us / 25 ns) is used as a default.
61 */
62 #ifndef CONFIG_SYS_NAND_RESET_CNT
63 #define CONFIG_SYS_NAND_RESET_CNT 200000
64 #endif
65
66 /* Define default oob placement schemes for large and small page devices */
67 static struct nand_ecclayout nand_oob_8 = {
68 .eccbytes = 3,
69 .eccpos = {0, 1, 2},
70 .oobfree = {
71 {.offset = 3,
72 .length = 2},
73 {.offset = 6,
74 .length = 2} }
75 };
76
77 static struct nand_ecclayout nand_oob_16 = {
78 .eccbytes = 6,
79 .eccpos = {0, 1, 2, 3, 6, 7},
80 .oobfree = {
81 {.offset = 8,
82 . length = 8} }
83 };
84
85 static struct nand_ecclayout nand_oob_64 = {
86 .eccbytes = 24,
87 .eccpos = {
88 40, 41, 42, 43, 44, 45, 46, 47,
89 48, 49, 50, 51, 52, 53, 54, 55,
90 56, 57, 58, 59, 60, 61, 62, 63},
91 .oobfree = {
92 {.offset = 2,
93 .length = 38} }
94 };
95
96 static struct nand_ecclayout nand_oob_128 = {
97 .eccbytes = 48,
98 .eccpos = {
99 80, 81, 82, 83, 84, 85, 86, 87,
100 88, 89, 90, 91, 92, 93, 94, 95,
101 96, 97, 98, 99, 100, 101, 102, 103,
102 104, 105, 106, 107, 108, 109, 110, 111,
103 112, 113, 114, 115, 116, 117, 118, 119,
104 120, 121, 122, 123, 124, 125, 126, 127},
105 .oobfree = {
106 {.offset = 2,
107 .length = 78} }
108 };
109
110 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
111 int new_state);
112
113 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
114 struct mtd_oob_ops *ops);
115
116 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this);
117
118 static int check_offs_len(struct mtd_info *mtd,
119 loff_t ofs, uint64_t len)
120 {
121 struct nand_chip *chip = mtd->priv;
122 int ret = 0;
123
124 /* Start address must align on block boundary */
125 if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
126 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Unaligned address\n", __func__);
127 ret = -EINVAL;
128 }
129
130 /* Length must align on block boundary */
131 if (len & ((1 << chip->phys_erase_shift) - 1)) {
132 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Length not block aligned\n",
133 __func__);
134 ret = -EINVAL;
135 }
136
137 /* Do not allow past end of device */
138 if (ofs + len > mtd->size) {
139 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Past end of device\n",
140 __func__);
141 ret = -EINVAL;
142 }
143
144 return ret;
145 }
146
147 /**
148 * nand_release_device - [GENERIC] release chip
149 * @mtd: MTD device structure
150 *
151 * Deselect, release chip lock and wake up anyone waiting on the device
152 */
153 static void nand_release_device(struct mtd_info *mtd)
154 {
155 struct nand_chip *chip = mtd->priv;
156
157 /* De-select the NAND device */
158 chip->select_chip(mtd, -1);
159 }
160
161 /**
162 * nand_read_byte - [DEFAULT] read one byte from the chip
163 * @mtd: MTD device structure
164 *
165 * Default read function for 8bit buswith
166 */
167 uint8_t nand_read_byte(struct mtd_info *mtd)
168 {
169 struct nand_chip *chip = mtd->priv;
170 return readb(chip->IO_ADDR_R);
171 }
172
173 /**
174 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
175 * @mtd: MTD device structure
176 *
177 * Default read function for 16bit buswith with
178 * endianess conversion
179 */
180 static uint8_t nand_read_byte16(struct mtd_info *mtd)
181 {
182 struct nand_chip *chip = mtd->priv;
183 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
184 }
185
186 /**
187 * nand_read_word - [DEFAULT] read one word from the chip
188 * @mtd: MTD device structure
189 *
190 * Default read function for 16bit buswith without
191 * endianess conversion
192 */
193 static u16 nand_read_word(struct mtd_info *mtd)
194 {
195 struct nand_chip *chip = mtd->priv;
196 return readw(chip->IO_ADDR_R);
197 }
198
199 /**
200 * nand_select_chip - [DEFAULT] control CE line
201 * @mtd: MTD device structure
202 * @chipnr: chipnumber to select, -1 for deselect
203 *
204 * Default select function for 1 chip devices.
205 */
206 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
207 {
208 struct nand_chip *chip = mtd->priv;
209
210 switch (chipnr) {
211 case -1:
212 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
213 break;
214 case 0:
215 break;
216
217 default:
218 BUG();
219 }
220 }
221
222 /**
223 * nand_write_buf - [DEFAULT] write buffer to chip
224 * @mtd: MTD device structure
225 * @buf: data buffer
226 * @len: number of bytes to write
227 *
228 * Default write function for 8bit buswith
229 */
230 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
231 {
232 int i;
233 struct nand_chip *chip = mtd->priv;
234
235 for (i = 0; i < len; i++)
236 writeb(buf[i], chip->IO_ADDR_W);
237 }
238
239 /**
240 * nand_read_buf - [DEFAULT] read chip data into buffer
241 * @mtd: MTD device structure
242 * @buf: buffer to store date
243 * @len: number of bytes to read
244 *
245 * Default read function for 8bit buswith
246 */
247 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
248 {
249 int i;
250 struct nand_chip *chip = mtd->priv;
251
252 for (i = 0; i < len; i++)
253 buf[i] = readb(chip->IO_ADDR_R);
254 }
255
256 /**
257 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
258 * @mtd: MTD device structure
259 * @buf: buffer containing the data to compare
260 * @len: number of bytes to compare
261 *
262 * Default verify function for 8bit buswith
263 */
264 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
265 {
266 int i;
267 struct nand_chip *chip = mtd->priv;
268
269 for (i = 0; i < len; i++)
270 if (buf[i] != readb(chip->IO_ADDR_R))
271 return -EFAULT;
272 return 0;
273 }
274
275 /**
276 * nand_write_buf16 - [DEFAULT] write buffer to chip
277 * @mtd: MTD device structure
278 * @buf: data buffer
279 * @len: number of bytes to write
280 *
281 * Default write function for 16bit buswith
282 */
283 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
284 {
285 int i;
286 struct nand_chip *chip = mtd->priv;
287 u16 *p = (u16 *) buf;
288 len >>= 1;
289
290 for (i = 0; i < len; i++)
291 writew(p[i], chip->IO_ADDR_W);
292
293 }
294
295 /**
296 * nand_read_buf16 - [DEFAULT] read chip data into buffer
297 * @mtd: MTD device structure
298 * @buf: buffer to store date
299 * @len: number of bytes to read
300 *
301 * Default read function for 16bit buswith
302 */
303 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
304 {
305 int i;
306 struct nand_chip *chip = mtd->priv;
307 u16 *p = (u16 *) buf;
308 len >>= 1;
309
310 for (i = 0; i < len; i++)
311 p[i] = readw(chip->IO_ADDR_R);
312 }
313
314 /**
315 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
316 * @mtd: MTD device structure
317 * @buf: buffer containing the data to compare
318 * @len: number of bytes to compare
319 *
320 * Default verify function for 16bit buswith
321 */
322 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
323 {
324 int i;
325 struct nand_chip *chip = mtd->priv;
326 u16 *p = (u16 *) buf;
327 len >>= 1;
328
329 for (i = 0; i < len; i++)
330 if (p[i] != readw(chip->IO_ADDR_R))
331 return -EFAULT;
332
333 return 0;
334 }
335
336 /**
337 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
338 * @mtd: MTD device structure
339 * @ofs: offset from device start
340 * @getchip: 0, if the chip is already selected
341 *
342 * Check, if the block is bad.
343 */
344 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
345 {
346 int page, chipnr, res = 0;
347 struct nand_chip *chip = mtd->priv;
348 u16 bad;
349
350 if (chip->options & NAND_BBT_SCANLASTPAGE)
351 ofs += mtd->erasesize - mtd->writesize;
352
353 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
354
355 if (getchip) {
356 chipnr = (int)(ofs >> chip->chip_shift);
357
358 nand_get_device(chip, mtd, FL_READING);
359
360 /* Select the NAND device */
361 chip->select_chip(mtd, chipnr);
362 }
363
364 if (chip->options & NAND_BUSWIDTH_16) {
365 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
366 page);
367 bad = cpu_to_le16(chip->read_word(mtd));
368 if (chip->badblockpos & 0x1)
369 bad >>= 8;
370 else
371 bad &= 0xFF;
372 } else {
373 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
374 bad = chip->read_byte(mtd);
375 }
376
377 if (likely(chip->badblockbits == 8))
378 res = bad != 0xFF;
379 else
380 res = hweight8(bad) < chip->badblockbits;
381
382 if (getchip)
383 nand_release_device(mtd);
384
385 return res;
386 }
387
388 /**
389 * nand_default_block_markbad - [DEFAULT] mark a block bad
390 * @mtd: MTD device structure
391 * @ofs: offset from device start
392 *
393 * This is the default implementation, which can be overridden by
394 * a hardware specific driver.
395 */
396 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
397 {
398 struct nand_chip *chip = mtd->priv;
399 uint8_t buf[2] = { 0, 0 };
400 int block, ret, i = 0;
401
402 if (chip->options & NAND_BBT_SCANLASTPAGE)
403 ofs += mtd->erasesize - mtd->writesize;
404
405 /* Get block number */
406 block = (int)(ofs >> chip->bbt_erase_shift);
407 if (chip->bbt)
408 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
409
410 /* Do we have a flash based bad block table ? */
411 if (chip->options & NAND_USE_FLASH_BBT)
412 ret = nand_update_bbt(mtd, ofs);
413 else {
414 nand_get_device(chip, mtd, FL_WRITING);
415
416 /* Write to first two pages and to byte 1 and 6 if necessary.
417 * If we write to more than one location, the first error
418 * encountered quits the procedure. We write two bytes per
419 * location, so we dont have to mess with 16 bit access.
420 */
421 do {
422 chip->ops.len = chip->ops.ooblen = 2;
423 chip->ops.datbuf = NULL;
424 chip->ops.oobbuf = buf;
425 chip->ops.ooboffs = chip->badblockpos & ~0x01;
426
427 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
428
429 if (!ret && (chip->options & NAND_BBT_SCANBYTE1AND6)) {
430 chip->ops.ooboffs = NAND_SMALL_BADBLOCK_POS
431 & ~0x01;
432 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
433 }
434 i++;
435 ofs += mtd->writesize;
436 } while (!ret && (chip->options & NAND_BBT_SCAN2NDPAGE) &&
437 i < 2);
438
439 nand_release_device(mtd);
440 }
441 if (!ret)
442 mtd->ecc_stats.badblocks++;
443
444 return ret;
445 }
446
447 /**
448 * nand_check_wp - [GENERIC] check if the chip is write protected
449 * @mtd: MTD device structure
450 * Check, if the device is write protected
451 *
452 * The function expects, that the device is already selected
453 */
454 static int nand_check_wp(struct mtd_info *mtd)
455 {
456 struct nand_chip *chip = mtd->priv;
457
458 /* broken xD cards report WP despite being writable */
459 if (chip->options & NAND_BROKEN_XD)
460 return 0;
461
462 /* Check the WP bit */
463 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
464 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
465 }
466
467 /**
468 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
469 * @mtd: MTD device structure
470 * @ofs: offset from device start
471 * @getchip: 0, if the chip is already selected
472 * @allowbbt: 1, if its allowed to access the bbt area
473 *
474 * Check, if the block is bad. Either by reading the bad block table or
475 * calling of the scan function.
476 */
477 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
478 int allowbbt)
479 {
480 struct nand_chip *chip = mtd->priv;
481
482 if (!(chip->options & NAND_BBT_SCANNED)) {
483 chip->options |= NAND_BBT_SCANNED;
484 chip->scan_bbt(mtd);
485 }
486
487 if (!chip->bbt)
488 return chip->block_bad(mtd, ofs, getchip);
489
490 /* Return info from the table */
491 return nand_isbad_bbt(mtd, ofs, allowbbt);
492 }
493
494 /*
495 * Wait for the ready pin, after a command
496 * The timeout is catched later.
497 */
498 void nand_wait_ready(struct mtd_info *mtd)
499 {
500 struct nand_chip *chip = mtd->priv;
501 u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
502 u32 time_start;
503
504 time_start = get_timer(0);
505
506 /* wait until command is processed or timeout occures */
507 while (get_timer(time_start) < timeo) {
508 if (chip->dev_ready)
509 if (chip->dev_ready(mtd))
510 break;
511 }
512 }
513
514 /**
515 * nand_command - [DEFAULT] Send command to NAND device
516 * @mtd: MTD device structure
517 * @command: the command to be sent
518 * @column: the column address for this command, -1 if none
519 * @page_addr: the page address for this command, -1 if none
520 *
521 * Send command to NAND device. This function is used for small page
522 * devices (256/512 Bytes per page)
523 */
524 static void nand_command(struct mtd_info *mtd, unsigned int command,
525 int column, int page_addr)
526 {
527 register struct nand_chip *chip = mtd->priv;
528 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
529 uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
530
531 /*
532 * Write out the command to the device.
533 */
534 if (command == NAND_CMD_SEQIN) {
535 int readcmd;
536
537 if (column >= mtd->writesize) {
538 /* OOB area */
539 column -= mtd->writesize;
540 readcmd = NAND_CMD_READOOB;
541 } else if (column < 256) {
542 /* First 256 bytes --> READ0 */
543 readcmd = NAND_CMD_READ0;
544 } else {
545 column -= 256;
546 readcmd = NAND_CMD_READ1;
547 }
548 chip->cmd_ctrl(mtd, readcmd, ctrl);
549 ctrl &= ~NAND_CTRL_CHANGE;
550 }
551 chip->cmd_ctrl(mtd, command, ctrl);
552
553 /*
554 * Address cycle, when necessary
555 */
556 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
557 /* Serially input address */
558 if (column != -1) {
559 /* Adjust columns for 16 bit buswidth */
560 if (chip->options & NAND_BUSWIDTH_16)
561 column >>= 1;
562 chip->cmd_ctrl(mtd, column, ctrl);
563 ctrl &= ~NAND_CTRL_CHANGE;
564 }
565 if (page_addr != -1) {
566 chip->cmd_ctrl(mtd, page_addr, ctrl);
567 ctrl &= ~NAND_CTRL_CHANGE;
568 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
569 /* One more address cycle for devices > 32MiB */
570 if (chip->chipsize > (32 << 20))
571 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
572 }
573 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
574
575 /*
576 * program and erase have their own busy handlers
577 * status and sequential in needs no delay
578 */
579 switch (command) {
580
581 case NAND_CMD_PAGEPROG:
582 case NAND_CMD_ERASE1:
583 case NAND_CMD_ERASE2:
584 case NAND_CMD_SEQIN:
585 case NAND_CMD_STATUS:
586 return;
587
588 case NAND_CMD_RESET:
589 if (chip->dev_ready)
590 break;
591 udelay(chip->chip_delay);
592 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
593 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
594 chip->cmd_ctrl(mtd,
595 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
596 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
597 (rst_sts_cnt--));
598 return;
599
600 /* This applies to read commands */
601 default:
602 /*
603 * If we don't have access to the busy pin, we apply the given
604 * command delay
605 */
606 if (!chip->dev_ready) {
607 udelay(chip->chip_delay);
608 return;
609 }
610 }
611 /* Apply this short delay always to ensure that we do wait tWB in
612 * any case on any machine. */
613 ndelay(100);
614
615 nand_wait_ready(mtd);
616 }
617
618 /**
619 * nand_command_lp - [DEFAULT] Send command to NAND large page device
620 * @mtd: MTD device structure
621 * @command: the command to be sent
622 * @column: the column address for this command, -1 if none
623 * @page_addr: the page address for this command, -1 if none
624 *
625 * Send command to NAND device. This is the version for the new large page
626 * devices We dont have the separate regions as we have in the small page
627 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
628 */
629 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
630 int column, int page_addr)
631 {
632 register struct nand_chip *chip = mtd->priv;
633 uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
634
635 /* Emulate NAND_CMD_READOOB */
636 if (command == NAND_CMD_READOOB) {
637 column += mtd->writesize;
638 command = NAND_CMD_READ0;
639 }
640
641 /* Command latch cycle */
642 chip->cmd_ctrl(mtd, command & 0xff,
643 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
644
645 if (column != -1 || page_addr != -1) {
646 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
647
648 /* Serially input address */
649 if (column != -1) {
650 /* Adjust columns for 16 bit buswidth */
651 if (chip->options & NAND_BUSWIDTH_16)
652 column >>= 1;
653 chip->cmd_ctrl(mtd, column, ctrl);
654 ctrl &= ~NAND_CTRL_CHANGE;
655 chip->cmd_ctrl(mtd, column >> 8, ctrl);
656 }
657 if (page_addr != -1) {
658 chip->cmd_ctrl(mtd, page_addr, ctrl);
659 chip->cmd_ctrl(mtd, page_addr >> 8,
660 NAND_NCE | NAND_ALE);
661 /* One more address cycle for devices > 128MiB */
662 if (chip->chipsize > (128 << 20))
663 chip->cmd_ctrl(mtd, page_addr >> 16,
664 NAND_NCE | NAND_ALE);
665 }
666 }
667 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
668
669 /*
670 * program and erase have their own busy handlers
671 * status, sequential in, and deplete1 need no delay
672 */
673 switch (command) {
674
675 case NAND_CMD_CACHEDPROG:
676 case NAND_CMD_PAGEPROG:
677 case NAND_CMD_ERASE1:
678 case NAND_CMD_ERASE2:
679 case NAND_CMD_SEQIN:
680 case NAND_CMD_RNDIN:
681 case NAND_CMD_STATUS:
682 case NAND_CMD_DEPLETE1:
683 return;
684
685 /*
686 * read error status commands require only a short delay
687 */
688 case NAND_CMD_STATUS_ERROR:
689 case NAND_CMD_STATUS_ERROR0:
690 case NAND_CMD_STATUS_ERROR1:
691 case NAND_CMD_STATUS_ERROR2:
692 case NAND_CMD_STATUS_ERROR3:
693 udelay(chip->chip_delay);
694 return;
695
696 case NAND_CMD_RESET:
697 if (chip->dev_ready)
698 break;
699 udelay(chip->chip_delay);
700 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
701 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
702 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
703 NAND_NCE | NAND_CTRL_CHANGE);
704 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
705 (rst_sts_cnt--));
706 return;
707
708 case NAND_CMD_RNDOUT:
709 /* No ready / busy check necessary */
710 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
711 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
712 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
713 NAND_NCE | NAND_CTRL_CHANGE);
714 return;
715
716 case NAND_CMD_READ0:
717 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
718 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
719 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
720 NAND_NCE | NAND_CTRL_CHANGE);
721
722 /* This applies to read commands */
723 default:
724 /*
725 * If we don't have access to the busy pin, we apply the given
726 * command delay
727 */
728 if (!chip->dev_ready) {
729 udelay(chip->chip_delay);
730 return;
731 }
732 }
733
734 /* Apply this short delay always to ensure that we do wait tWB in
735 * any case on any machine. */
736 ndelay(100);
737
738 nand_wait_ready(mtd);
739 }
740
741 /**
742 * nand_get_device - [GENERIC] Get chip for selected access
743 * @chip: the nand chip descriptor
744 * @mtd: MTD device structure
745 * @new_state: the state which is requested
746 *
747 * Get the device and lock it for exclusive access
748 */
749 static int
750 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
751 {
752 chip->state = new_state;
753 return 0;
754 }
755
756 /**
757 * nand_wait - [DEFAULT] wait until the command is done
758 * @mtd: MTD device structure
759 * @chip: NAND chip structure
760 *
761 * Wait for command done. This applies to erase and program only
762 * Erase can take up to 400ms and program up to 20ms according to
763 * general NAND and SmartMedia specs
764 */
765 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
766 {
767 unsigned long timeo;
768 int state = chip->state;
769 u32 time_start;
770
771 if (state == FL_ERASING)
772 timeo = (CONFIG_SYS_HZ * 400) / 1000;
773 else
774 timeo = (CONFIG_SYS_HZ * 20) / 1000;
775
776 if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
777 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
778 else
779 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
780
781 time_start = get_timer(0);
782
783 while (1) {
784 if (get_timer(time_start) > timeo) {
785 printf("Timeout!");
786 return 0x01;
787 }
788
789 if (chip->dev_ready) {
790 if (chip->dev_ready(mtd))
791 break;
792 } else {
793 if (chip->read_byte(mtd) & NAND_STATUS_READY)
794 break;
795 }
796 }
797 #ifdef PPCHAMELON_NAND_TIMER_HACK
798 time_start = get_timer(0);
799 while (get_timer(time_start) < 10)
800 ;
801 #endif /* PPCHAMELON_NAND_TIMER_HACK */
802
803 return (int)chip->read_byte(mtd);
804 }
805
806 /**
807 * nand_read_page_raw - [Intern] read raw page data without ecc
808 * @mtd: mtd info structure
809 * @chip: nand chip info structure
810 * @buf: buffer to store read data
811 * @page: page number to read
812 *
813 * Not for syndrome calculating ecc controllers, which use a special oob layout
814 */
815 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
816 uint8_t *buf, int page)
817 {
818 chip->read_buf(mtd, buf, mtd->writesize);
819 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
820 return 0;
821 }
822
823 /**
824 * nand_read_page_raw_syndrome - [Intern] read raw page data without ecc
825 * @mtd: mtd info structure
826 * @chip: nand chip info structure
827 * @buf: buffer to store read data
828 * @page: page number to read
829 *
830 * We need a special oob layout and handling even when OOB isn't used.
831 */
832 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
833 struct nand_chip *chip,
834 uint8_t *buf, int page)
835 {
836 int eccsize = chip->ecc.size;
837 int eccbytes = chip->ecc.bytes;
838 uint8_t *oob = chip->oob_poi;
839 int steps, size;
840
841 for (steps = chip->ecc.steps; steps > 0; steps--) {
842 chip->read_buf(mtd, buf, eccsize);
843 buf += eccsize;
844
845 if (chip->ecc.prepad) {
846 chip->read_buf(mtd, oob, chip->ecc.prepad);
847 oob += chip->ecc.prepad;
848 }
849
850 chip->read_buf(mtd, oob, eccbytes);
851 oob += eccbytes;
852
853 if (chip->ecc.postpad) {
854 chip->read_buf(mtd, oob, chip->ecc.postpad);
855 oob += chip->ecc.postpad;
856 }
857 }
858
859 size = mtd->oobsize - (oob - chip->oob_poi);
860 if (size)
861 chip->read_buf(mtd, oob, size);
862
863 return 0;
864 }
865
866 /**
867 * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
868 * @mtd: mtd info structure
869 * @chip: nand chip info structure
870 * @buf: buffer to store read data
871 * @page: page number to read
872 */
873 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
874 uint8_t *buf, int page)
875 {
876 int i, eccsize = chip->ecc.size;
877 int eccbytes = chip->ecc.bytes;
878 int eccsteps = chip->ecc.steps;
879 uint8_t *p = buf;
880 uint8_t *ecc_calc = chip->buffers->ecccalc;
881 uint8_t *ecc_code = chip->buffers->ecccode;
882 uint32_t *eccpos = chip->ecc.layout->eccpos;
883
884 chip->ecc.read_page_raw(mtd, chip, buf, page);
885
886 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
887 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
888
889 for (i = 0; i < chip->ecc.total; i++)
890 ecc_code[i] = chip->oob_poi[eccpos[i]];
891
892 eccsteps = chip->ecc.steps;
893 p = buf;
894
895 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
896 int stat;
897
898 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
899 if (stat < 0)
900 mtd->ecc_stats.failed++;
901 else
902 mtd->ecc_stats.corrected += stat;
903 }
904 return 0;
905 }
906
907 /**
908 * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
909 * @mtd: mtd info structure
910 * @chip: nand chip info structure
911 * @data_offs: offset of requested data within the page
912 * @readlen: data length
913 * @bufpoi: buffer to store read data
914 */
915 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
916 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
917 {
918 int start_step, end_step, num_steps;
919 uint32_t *eccpos = chip->ecc.layout->eccpos;
920 uint8_t *p;
921 int data_col_addr, i, gaps = 0;
922 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
923 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
924 int index = 0;
925
926 /* Column address wihin the page aligned to ECC size (256bytes). */
927 start_step = data_offs / chip->ecc.size;
928 end_step = (data_offs + readlen - 1) / chip->ecc.size;
929 num_steps = end_step - start_step + 1;
930
931 /* Data size aligned to ECC ecc.size*/
932 datafrag_len = num_steps * chip->ecc.size;
933 eccfrag_len = num_steps * chip->ecc.bytes;
934
935 data_col_addr = start_step * chip->ecc.size;
936 /* If we read not a page aligned data */
937 if (data_col_addr != 0)
938 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
939
940 p = bufpoi + data_col_addr;
941 chip->read_buf(mtd, p, datafrag_len);
942
943 /* Calculate ECC */
944 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
945 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
946
947 /* The performance is faster if to position offsets
948 according to ecc.pos. Let make sure here that
949 there are no gaps in ecc positions */
950 for (i = 0; i < eccfrag_len - 1; i++) {
951 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
952 eccpos[i + start_step * chip->ecc.bytes + 1]) {
953 gaps = 1;
954 break;
955 }
956 }
957 if (gaps) {
958 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
959 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
960 } else {
961 /* send the command to read the particular ecc bytes */
962 /* take care about buswidth alignment in read_buf */
963 index = start_step * chip->ecc.bytes;
964
965 aligned_pos = eccpos[index] & ~(busw - 1);
966 aligned_len = eccfrag_len;
967 if (eccpos[index] & (busw - 1))
968 aligned_len++;
969 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
970 aligned_len++;
971
972 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
973 mtd->writesize + aligned_pos, -1);
974 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
975 }
976
977 for (i = 0; i < eccfrag_len; i++)
978 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
979
980 p = bufpoi + data_col_addr;
981 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
982 int stat;
983
984 stat = chip->ecc.correct(mtd, p,
985 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
986 if (stat < 0)
987 mtd->ecc_stats.failed++;
988 else
989 mtd->ecc_stats.corrected += stat;
990 }
991 return 0;
992 }
993
994 /**
995 * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
996 * @mtd: mtd info structure
997 * @chip: nand chip info structure
998 * @buf: buffer to store read data
999 * @page: page number to read
1000 *
1001 * Not for syndrome calculating ecc controllers which need a special oob layout
1002 */
1003 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1004 uint8_t *buf, int page)
1005 {
1006 int i, eccsize = chip->ecc.size;
1007 int eccbytes = chip->ecc.bytes;
1008 int eccsteps = chip->ecc.steps;
1009 uint8_t *p = buf;
1010 uint8_t *ecc_calc = chip->buffers->ecccalc;
1011 uint8_t *ecc_code = chip->buffers->ecccode;
1012 uint32_t *eccpos = chip->ecc.layout->eccpos;
1013
1014 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1015 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1016 chip->read_buf(mtd, p, eccsize);
1017 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1018 }
1019 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1020
1021 for (i = 0; i < chip->ecc.total; i++)
1022 ecc_code[i] = chip->oob_poi[eccpos[i]];
1023
1024 eccsteps = chip->ecc.steps;
1025 p = buf;
1026
1027 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1028 int stat;
1029
1030 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1031 if (stat < 0)
1032 mtd->ecc_stats.failed++;
1033 else
1034 mtd->ecc_stats.corrected += stat;
1035 }
1036 return 0;
1037 }
1038
1039 /**
1040 * nand_read_page_hwecc_oob_first - [REPLACABLE] hw ecc, read oob first
1041 * @mtd: mtd info structure
1042 * @chip: nand chip info structure
1043 * @buf: buffer to store read data
1044 * @page: page number to read
1045 *
1046 * Hardware ECC for large page chips, require OOB to be read first.
1047 * For this ECC mode, the write_page method is re-used from ECC_HW.
1048 * These methods read/write ECC from the OOB area, unlike the
1049 * ECC_HW_SYNDROME support with multiple ECC steps, follows the
1050 * "infix ECC" scheme and reads/writes ECC from the data area, by
1051 * overwriting the NAND manufacturer bad block markings.
1052 */
1053 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1054 struct nand_chip *chip, uint8_t *buf, int page)
1055 {
1056 int i, eccsize = chip->ecc.size;
1057 int eccbytes = chip->ecc.bytes;
1058 int eccsteps = chip->ecc.steps;
1059 uint8_t *p = buf;
1060 uint8_t *ecc_code = chip->buffers->ecccode;
1061 uint32_t *eccpos = chip->ecc.layout->eccpos;
1062 uint8_t *ecc_calc = chip->buffers->ecccalc;
1063
1064 /* Read the OOB area first */
1065 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1066 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1067 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1068
1069 for (i = 0; i < chip->ecc.total; i++)
1070 ecc_code[i] = chip->oob_poi[eccpos[i]];
1071
1072 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1073 int stat;
1074
1075 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1076 chip->read_buf(mtd, p, eccsize);
1077 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1078
1079 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1080 if (stat < 0)
1081 mtd->ecc_stats.failed++;
1082 else
1083 mtd->ecc_stats.corrected += stat;
1084 }
1085 return 0;
1086 }
1087
1088 /**
1089 * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
1090 * @mtd: mtd info structure
1091 * @chip: nand chip info structure
1092 * @buf: buffer to store read data
1093 * @page: page number to read
1094 *
1095 * The hw generator calculates the error syndrome automatically. Therefor
1096 * we need a special oob layout and handling.
1097 */
1098 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1099 uint8_t *buf, int page)
1100 {
1101 int i, eccsize = chip->ecc.size;
1102 int eccbytes = chip->ecc.bytes;
1103 int eccsteps = chip->ecc.steps;
1104 uint8_t *p = buf;
1105 uint8_t *oob = chip->oob_poi;
1106
1107 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1108 int stat;
1109
1110 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1111 chip->read_buf(mtd, p, eccsize);
1112
1113 if (chip->ecc.prepad) {
1114 chip->read_buf(mtd, oob, chip->ecc.prepad);
1115 oob += chip->ecc.prepad;
1116 }
1117
1118 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1119 chip->read_buf(mtd, oob, eccbytes);
1120 stat = chip->ecc.correct(mtd, p, oob, NULL);
1121
1122 if (stat < 0)
1123 mtd->ecc_stats.failed++;
1124 else
1125 mtd->ecc_stats.corrected += stat;
1126
1127 oob += eccbytes;
1128
1129 if (chip->ecc.postpad) {
1130 chip->read_buf(mtd, oob, chip->ecc.postpad);
1131 oob += chip->ecc.postpad;
1132 }
1133 }
1134
1135 /* Calculate remaining oob bytes */
1136 i = mtd->oobsize - (oob - chip->oob_poi);
1137 if (i)
1138 chip->read_buf(mtd, oob, i);
1139
1140 return 0;
1141 }
1142
1143 /**
1144 * nand_transfer_oob - [Internal] Transfer oob to client buffer
1145 * @chip: nand chip structure
1146 * @oob: oob destination address
1147 * @ops: oob ops structure
1148 * @len: size of oob to transfer
1149 */
1150 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1151 struct mtd_oob_ops *ops, size_t len)
1152 {
1153 switch (ops->mode) {
1154
1155 case MTD_OOB_PLACE:
1156 case MTD_OOB_RAW:
1157 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1158 return oob + len;
1159
1160 case MTD_OOB_AUTO: {
1161 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1162 uint32_t boffs = 0, roffs = ops->ooboffs;
1163 size_t bytes = 0;
1164
1165 for (; free->length && len; free++, len -= bytes) {
1166 /* Read request not from offset 0 ? */
1167 if (unlikely(roffs)) {
1168 if (roffs >= free->length) {
1169 roffs -= free->length;
1170 continue;
1171 }
1172 boffs = free->offset + roffs;
1173 bytes = min_t(size_t, len,
1174 (free->length - roffs));
1175 roffs = 0;
1176 } else {
1177 bytes = min_t(size_t, len, free->length);
1178 boffs = free->offset;
1179 }
1180 memcpy(oob, chip->oob_poi + boffs, bytes);
1181 oob += bytes;
1182 }
1183 return oob;
1184 }
1185 default:
1186 BUG();
1187 }
1188 return NULL;
1189 }
1190
1191 /**
1192 * nand_do_read_ops - [Internal] Read data with ECC
1193 *
1194 * @mtd: MTD device structure
1195 * @from: offset to read from
1196 * @ops: oob ops structure
1197 *
1198 * Internal function. Called with chip held.
1199 */
1200 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1201 struct mtd_oob_ops *ops)
1202 {
1203 int chipnr, page, realpage, col, bytes, aligned;
1204 struct nand_chip *chip = mtd->priv;
1205 struct mtd_ecc_stats stats;
1206 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1207 int sndcmd = 1;
1208 int ret = 0;
1209 uint32_t readlen = ops->len;
1210 uint32_t oobreadlen = ops->ooblen;
1211 uint32_t max_oobsize = ops->mode == MTD_OOB_AUTO ?
1212 mtd->oobavail : mtd->oobsize;
1213
1214 uint8_t *bufpoi, *oob, *buf;
1215
1216 stats = mtd->ecc_stats;
1217
1218 chipnr = (int)(from >> chip->chip_shift);
1219 chip->select_chip(mtd, chipnr);
1220
1221 realpage = (int)(from >> chip->page_shift);
1222 page = realpage & chip->pagemask;
1223
1224 col = (int)(from & (mtd->writesize - 1));
1225
1226 buf = ops->datbuf;
1227 oob = ops->oobbuf;
1228
1229 while (1) {
1230 WATCHDOG_RESET();
1231
1232 bytes = min(mtd->writesize - col, readlen);
1233 aligned = (bytes == mtd->writesize);
1234
1235 /* Is the current page in the buffer ? */
1236 if (realpage != chip->pagebuf || oob) {
1237 bufpoi = aligned ? buf : chip->buffers->databuf;
1238
1239 if (likely(sndcmd)) {
1240 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1241 sndcmd = 0;
1242 }
1243
1244 /* Now read the page into the buffer */
1245 if (unlikely(ops->mode == MTD_OOB_RAW))
1246 ret = chip->ecc.read_page_raw(mtd, chip,
1247 bufpoi, page);
1248 else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
1249 !oob)
1250 ret = chip->ecc.read_subpage(mtd, chip,
1251 col, bytes, bufpoi);
1252 else
1253 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1254 page);
1255 if (ret < 0)
1256 break;
1257
1258 /* Transfer not aligned data */
1259 if (!aligned) {
1260 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
1261 !(mtd->ecc_stats.failed - stats.failed))
1262 chip->pagebuf = realpage;
1263 memcpy(buf, chip->buffers->databuf + col, bytes);
1264 }
1265
1266 buf += bytes;
1267
1268 if (unlikely(oob)) {
1269
1270 int toread = min(oobreadlen, max_oobsize);
1271
1272 if (toread) {
1273 oob = nand_transfer_oob(chip,
1274 oob, ops, toread);
1275 oobreadlen -= toread;
1276 }
1277 }
1278
1279 if (!(chip->options & NAND_NO_READRDY)) {
1280 /*
1281 * Apply delay or wait for ready/busy pin. Do
1282 * this before the AUTOINCR check, so no
1283 * problems arise if a chip which does auto
1284 * increment is marked as NOAUTOINCR by the
1285 * board driver.
1286 */
1287 if (!chip->dev_ready)
1288 udelay(chip->chip_delay);
1289 else
1290 nand_wait_ready(mtd);
1291 }
1292 } else {
1293 memcpy(buf, chip->buffers->databuf + col, bytes);
1294 buf += bytes;
1295 }
1296
1297 readlen -= bytes;
1298
1299 if (!readlen)
1300 break;
1301
1302 /* For subsequent reads align to page boundary. */
1303 col = 0;
1304 /* Increment page address */
1305 realpage++;
1306
1307 page = realpage & chip->pagemask;
1308 /* Check, if we cross a chip boundary */
1309 if (!page) {
1310 chipnr++;
1311 chip->select_chip(mtd, -1);
1312 chip->select_chip(mtd, chipnr);
1313 }
1314
1315 /* Check, if the chip supports auto page increment
1316 * or if we have hit a block boundary.
1317 */
1318 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1319 sndcmd = 1;
1320 }
1321
1322 ops->retlen = ops->len - (size_t) readlen;
1323 if (oob)
1324 ops->oobretlen = ops->ooblen - oobreadlen;
1325
1326 if (ret)
1327 return ret;
1328
1329 if (mtd->ecc_stats.failed - stats.failed)
1330 return -EBADMSG;
1331
1332 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1333 }
1334
1335 /**
1336 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1337 * @mtd: MTD device structure
1338 * @from: offset to read from
1339 * @len: number of bytes to read
1340 * @retlen: pointer to variable to store the number of read bytes
1341 * @buf: the databuffer to put data
1342 *
1343 * Get hold of the chip and call nand_do_read
1344 */
1345 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1346 size_t *retlen, uint8_t *buf)
1347 {
1348 struct nand_chip *chip = mtd->priv;
1349 int ret;
1350
1351 /* Do not allow reads past end of device */
1352 if ((from + len) > mtd->size)
1353 return -EINVAL;
1354 if (!len)
1355 return 0;
1356
1357 nand_get_device(chip, mtd, FL_READING);
1358
1359 chip->ops.len = len;
1360 chip->ops.datbuf = buf;
1361 chip->ops.oobbuf = NULL;
1362
1363 ret = nand_do_read_ops(mtd, from, &chip->ops);
1364
1365 *retlen = chip->ops.retlen;
1366
1367 nand_release_device(mtd);
1368
1369 return ret;
1370 }
1371
1372 /**
1373 * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1374 * @mtd: mtd info structure
1375 * @chip: nand chip info structure
1376 * @page: page number to read
1377 * @sndcmd: flag whether to issue read command or not
1378 */
1379 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1380 int page, int sndcmd)
1381 {
1382 if (sndcmd) {
1383 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1384 sndcmd = 0;
1385 }
1386 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1387 return sndcmd;
1388 }
1389
1390 /**
1391 * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1392 * with syndromes
1393 * @mtd: mtd info structure
1394 * @chip: nand chip info structure
1395 * @page: page number to read
1396 * @sndcmd: flag whether to issue read command or not
1397 */
1398 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1399 int page, int sndcmd)
1400 {
1401 uint8_t *buf = chip->oob_poi;
1402 int length = mtd->oobsize;
1403 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1404 int eccsize = chip->ecc.size;
1405 uint8_t *bufpoi = buf;
1406 int i, toread, sndrnd = 0, pos;
1407
1408 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1409 for (i = 0; i < chip->ecc.steps; i++) {
1410 if (sndrnd) {
1411 pos = eccsize + i * (eccsize + chunk);
1412 if (mtd->writesize > 512)
1413 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1414 else
1415 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1416 } else
1417 sndrnd = 1;
1418 toread = min_t(int, length, chunk);
1419 chip->read_buf(mtd, bufpoi, toread);
1420 bufpoi += toread;
1421 length -= toread;
1422 }
1423 if (length > 0)
1424 chip->read_buf(mtd, bufpoi, length);
1425
1426 return 1;
1427 }
1428
1429 /**
1430 * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1431 * @mtd: mtd info structure
1432 * @chip: nand chip info structure
1433 * @page: page number to write
1434 */
1435 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1436 int page)
1437 {
1438 int status = 0;
1439 const uint8_t *buf = chip->oob_poi;
1440 int length = mtd->oobsize;
1441
1442 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1443 chip->write_buf(mtd, buf, length);
1444 /* Send command to program the OOB data */
1445 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1446
1447 status = chip->waitfunc(mtd, chip);
1448
1449 return status & NAND_STATUS_FAIL ? -EIO : 0;
1450 }
1451
1452 /**
1453 * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1454 * with syndrome - only for large page flash !
1455 * @mtd: mtd info structure
1456 * @chip: nand chip info structure
1457 * @page: page number to write
1458 */
1459 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1460 struct nand_chip *chip, int page)
1461 {
1462 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1463 int eccsize = chip->ecc.size, length = mtd->oobsize;
1464 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1465 const uint8_t *bufpoi = chip->oob_poi;
1466
1467 /*
1468 * data-ecc-data-ecc ... ecc-oob
1469 * or
1470 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1471 */
1472 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1473 pos = steps * (eccsize + chunk);
1474 steps = 0;
1475 } else
1476 pos = eccsize;
1477
1478 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1479 for (i = 0; i < steps; i++) {
1480 if (sndcmd) {
1481 if (mtd->writesize <= 512) {
1482 uint32_t fill = 0xFFFFFFFF;
1483
1484 len = eccsize;
1485 while (len > 0) {
1486 int num = min_t(int, len, 4);
1487 chip->write_buf(mtd, (uint8_t *)&fill,
1488 num);
1489 len -= num;
1490 }
1491 } else {
1492 pos = eccsize + i * (eccsize + chunk);
1493 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1494 }
1495 } else
1496 sndcmd = 1;
1497 len = min_t(int, length, chunk);
1498 chip->write_buf(mtd, bufpoi, len);
1499 bufpoi += len;
1500 length -= len;
1501 }
1502 if (length > 0)
1503 chip->write_buf(mtd, bufpoi, length);
1504
1505 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1506 status = chip->waitfunc(mtd, chip);
1507
1508 return status & NAND_STATUS_FAIL ? -EIO : 0;
1509 }
1510
1511 /**
1512 * nand_do_read_oob - [Intern] NAND read out-of-band
1513 * @mtd: MTD device structure
1514 * @from: offset to read from
1515 * @ops: oob operations description structure
1516 *
1517 * NAND read out-of-band data from the spare area
1518 */
1519 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1520 struct mtd_oob_ops *ops)
1521 {
1522 int page, realpage, chipnr, sndcmd = 1;
1523 struct nand_chip *chip = mtd->priv;
1524 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1525 int readlen = ops->ooblen;
1526 int len;
1527 uint8_t *buf = ops->oobbuf;
1528
1529 MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08Lx, len = %i\n",
1530 __func__, (unsigned long long)from, readlen);
1531
1532 if (ops->mode == MTD_OOB_AUTO)
1533 len = chip->ecc.layout->oobavail;
1534 else
1535 len = mtd->oobsize;
1536
1537 if (unlikely(ops->ooboffs >= len)) {
1538 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start read "
1539 "outside oob\n", __func__);
1540 return -EINVAL;
1541 }
1542
1543 /* Do not allow reads past end of device */
1544 if (unlikely(from >= mtd->size ||
1545 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1546 (from >> chip->page_shift)) * len)) {
1547 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read beyond end "
1548 "of device\n", __func__);
1549 return -EINVAL;
1550 }
1551
1552 chipnr = (int)(from >> chip->chip_shift);
1553 chip->select_chip(mtd, chipnr);
1554
1555 /* Shift to get page */
1556 realpage = (int)(from >> chip->page_shift);
1557 page = realpage & chip->pagemask;
1558
1559 while (1) {
1560 WATCHDOG_RESET();
1561 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1562
1563 len = min(len, readlen);
1564 buf = nand_transfer_oob(chip, buf, ops, len);
1565
1566 if (!(chip->options & NAND_NO_READRDY)) {
1567 /*
1568 * Apply delay or wait for ready/busy pin. Do this
1569 * before the AUTOINCR check, so no problems arise if a
1570 * chip which does auto increment is marked as
1571 * NOAUTOINCR by the board driver.
1572 */
1573 if (!chip->dev_ready)
1574 udelay(chip->chip_delay);
1575 else
1576 nand_wait_ready(mtd);
1577 }
1578
1579 readlen -= len;
1580 if (!readlen)
1581 break;
1582
1583 /* Increment page address */
1584 realpage++;
1585
1586 page = realpage & chip->pagemask;
1587 /* Check, if we cross a chip boundary */
1588 if (!page) {
1589 chipnr++;
1590 chip->select_chip(mtd, -1);
1591 chip->select_chip(mtd, chipnr);
1592 }
1593
1594 /* Check, if the chip supports auto page increment
1595 * or if we have hit a block boundary.
1596 */
1597 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1598 sndcmd = 1;
1599 }
1600
1601 ops->oobretlen = ops->ooblen;
1602 return 0;
1603 }
1604
1605 /**
1606 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1607 * @mtd: MTD device structure
1608 * @from: offset to read from
1609 * @ops: oob operation description structure
1610 *
1611 * NAND read data and/or out-of-band data
1612 */
1613 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1614 struct mtd_oob_ops *ops)
1615 {
1616 struct nand_chip *chip = mtd->priv;
1617 int ret = -ENOTSUPP;
1618
1619 ops->retlen = 0;
1620
1621 /* Do not allow reads past end of device */
1622 if (ops->datbuf && (from + ops->len) > mtd->size) {
1623 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read "
1624 "beyond end of device\n", __func__);
1625 return -EINVAL;
1626 }
1627
1628 nand_get_device(chip, mtd, FL_READING);
1629
1630 switch (ops->mode) {
1631 case MTD_OOB_PLACE:
1632 case MTD_OOB_AUTO:
1633 case MTD_OOB_RAW:
1634 break;
1635
1636 default:
1637 goto out;
1638 }
1639
1640 if (!ops->datbuf)
1641 ret = nand_do_read_oob(mtd, from, ops);
1642 else
1643 ret = nand_do_read_ops(mtd, from, ops);
1644
1645 out:
1646 nand_release_device(mtd);
1647 return ret;
1648 }
1649
1650
1651 /**
1652 * nand_write_page_raw - [Intern] raw page write function
1653 * @mtd: mtd info structure
1654 * @chip: nand chip info structure
1655 * @buf: data buffer
1656 *
1657 * Not for syndrome calculating ecc controllers, which use a special oob layout
1658 */
1659 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1660 const uint8_t *buf)
1661 {
1662 chip->write_buf(mtd, buf, mtd->writesize);
1663 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1664 }
1665
1666 /**
1667 * nand_write_page_raw_syndrome - [Intern] raw page write function
1668 * @mtd: mtd info structure
1669 * @chip: nand chip info structure
1670 * @buf: data buffer
1671 *
1672 * We need a special oob layout and handling even when ECC isn't checked.
1673 */
1674 static void nand_write_page_raw_syndrome(struct mtd_info *mtd,
1675 struct nand_chip *chip,
1676 const uint8_t *buf)
1677 {
1678 int eccsize = chip->ecc.size;
1679 int eccbytes = chip->ecc.bytes;
1680 uint8_t *oob = chip->oob_poi;
1681 int steps, size;
1682
1683 for (steps = chip->ecc.steps; steps > 0; steps--) {
1684 chip->write_buf(mtd, buf, eccsize);
1685 buf += eccsize;
1686
1687 if (chip->ecc.prepad) {
1688 chip->write_buf(mtd, oob, chip->ecc.prepad);
1689 oob += chip->ecc.prepad;
1690 }
1691
1692 chip->read_buf(mtd, oob, eccbytes);
1693 oob += eccbytes;
1694
1695 if (chip->ecc.postpad) {
1696 chip->write_buf(mtd, oob, chip->ecc.postpad);
1697 oob += chip->ecc.postpad;
1698 }
1699 }
1700
1701 size = mtd->oobsize - (oob - chip->oob_poi);
1702 if (size)
1703 chip->write_buf(mtd, oob, size);
1704 }
1705 /**
1706 * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
1707 * @mtd: mtd info structure
1708 * @chip: nand chip info structure
1709 * @buf: data buffer
1710 */
1711 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1712 const uint8_t *buf)
1713 {
1714 int i, eccsize = chip->ecc.size;
1715 int eccbytes = chip->ecc.bytes;
1716 int eccsteps = chip->ecc.steps;
1717 uint8_t *ecc_calc = chip->buffers->ecccalc;
1718 const uint8_t *p = buf;
1719 uint32_t *eccpos = chip->ecc.layout->eccpos;
1720
1721 /* Software ecc calculation */
1722 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1723 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1724
1725 for (i = 0; i < chip->ecc.total; i++)
1726 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1727
1728 chip->ecc.write_page_raw(mtd, chip, buf);
1729 }
1730
1731 /**
1732 * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
1733 * @mtd: mtd info structure
1734 * @chip: nand chip info structure
1735 * @buf: data buffer
1736 */
1737 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1738 const uint8_t *buf)
1739 {
1740 int i, eccsize = chip->ecc.size;
1741 int eccbytes = chip->ecc.bytes;
1742 int eccsteps = chip->ecc.steps;
1743 uint8_t *ecc_calc = chip->buffers->ecccalc;
1744 const uint8_t *p = buf;
1745 uint32_t *eccpos = chip->ecc.layout->eccpos;
1746
1747 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1748 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1749 chip->write_buf(mtd, p, eccsize);
1750 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1751 }
1752
1753 for (i = 0; i < chip->ecc.total; i++)
1754 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1755
1756 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1757 }
1758
1759 /**
1760 * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
1761 * @mtd: mtd info structure
1762 * @chip: nand chip info structure
1763 * @buf: data buffer
1764 *
1765 * The hw generator calculates the error syndrome automatically. Therefor
1766 * we need a special oob layout and handling.
1767 */
1768 static void nand_write_page_syndrome(struct mtd_info *mtd,
1769 struct nand_chip *chip, const uint8_t *buf)
1770 {
1771 int i, eccsize = chip->ecc.size;
1772 int eccbytes = chip->ecc.bytes;
1773 int eccsteps = chip->ecc.steps;
1774 const uint8_t *p = buf;
1775 uint8_t *oob = chip->oob_poi;
1776
1777 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1778
1779 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1780 chip->write_buf(mtd, p, eccsize);
1781
1782 if (chip->ecc.prepad) {
1783 chip->write_buf(mtd, oob, chip->ecc.prepad);
1784 oob += chip->ecc.prepad;
1785 }
1786
1787 chip->ecc.calculate(mtd, p, oob);
1788 chip->write_buf(mtd, oob, eccbytes);
1789 oob += eccbytes;
1790
1791 if (chip->ecc.postpad) {
1792 chip->write_buf(mtd, oob, chip->ecc.postpad);
1793 oob += chip->ecc.postpad;
1794 }
1795 }
1796
1797 /* Calculate remaining oob bytes */
1798 i = mtd->oobsize - (oob - chip->oob_poi);
1799 if (i)
1800 chip->write_buf(mtd, oob, i);
1801 }
1802
1803 /**
1804 * nand_write_page - [REPLACEABLE] write one page
1805 * @mtd: MTD device structure
1806 * @chip: NAND chip descriptor
1807 * @buf: the data to write
1808 * @page: page number to write
1809 * @cached: cached programming
1810 * @raw: use _raw version of write_page
1811 */
1812 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1813 const uint8_t *buf, int page, int cached, int raw)
1814 {
1815 int status;
1816
1817 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1818
1819 if (unlikely(raw))
1820 chip->ecc.write_page_raw(mtd, chip, buf);
1821 else
1822 chip->ecc.write_page(mtd, chip, buf);
1823
1824 /*
1825 * Cached progamming disabled for now, Not sure if its worth the
1826 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
1827 */
1828 cached = 0;
1829
1830 if (!cached || !(chip->options & NAND_CACHEPRG)) {
1831
1832 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1833 status = chip->waitfunc(mtd, chip);
1834 /*
1835 * See if operation failed and additional status checks are
1836 * available
1837 */
1838 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1839 status = chip->errstat(mtd, chip, FL_WRITING, status,
1840 page);
1841
1842 if (status & NAND_STATUS_FAIL)
1843 return -EIO;
1844 } else {
1845 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
1846 status = chip->waitfunc(mtd, chip);
1847 }
1848
1849 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1850 /* Send command to read back the data */
1851 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1852
1853 if (chip->verify_buf(mtd, buf, mtd->writesize))
1854 return -EIO;
1855 #endif
1856 return 0;
1857 }
1858
1859 /**
1860 * nand_fill_oob - [Internal] Transfer client buffer to oob
1861 * @chip: nand chip structure
1862 * @oob: oob data buffer
1863 * @len: oob data write length
1864 * @ops: oob ops structure
1865 */
1866 static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob, size_t len,
1867 struct mtd_oob_ops *ops)
1868 {
1869 switch (ops->mode) {
1870
1871 case MTD_OOB_PLACE:
1872 case MTD_OOB_RAW:
1873 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
1874 return oob + len;
1875
1876 case MTD_OOB_AUTO: {
1877 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1878 uint32_t boffs = 0, woffs = ops->ooboffs;
1879 size_t bytes = 0;
1880
1881 for (; free->length && len; free++, len -= bytes) {
1882 /* Write request not from offset 0 ? */
1883 if (unlikely(woffs)) {
1884 if (woffs >= free->length) {
1885 woffs -= free->length;
1886 continue;
1887 }
1888 boffs = free->offset + woffs;
1889 bytes = min_t(size_t, len,
1890 (free->length - woffs));
1891 woffs = 0;
1892 } else {
1893 bytes = min_t(size_t, len, free->length);
1894 boffs = free->offset;
1895 }
1896 memcpy(chip->oob_poi + boffs, oob, bytes);
1897 oob += bytes;
1898 }
1899 return oob;
1900 }
1901 default:
1902 BUG();
1903 }
1904 return NULL;
1905 }
1906
1907 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
1908
1909 /**
1910 * nand_do_write_ops - [Internal] NAND write with ECC
1911 * @mtd: MTD device structure
1912 * @to: offset to write to
1913 * @ops: oob operations description structure
1914 *
1915 * NAND write with ECC
1916 */
1917 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
1918 struct mtd_oob_ops *ops)
1919 {
1920 int chipnr, realpage, page, blockmask, column;
1921 struct nand_chip *chip = mtd->priv;
1922 uint32_t writelen = ops->len;
1923
1924 uint32_t oobwritelen = ops->ooblen;
1925 uint32_t oobmaxlen = ops->mode == MTD_OOB_AUTO ?
1926 mtd->oobavail : mtd->oobsize;
1927
1928 uint8_t *oob = ops->oobbuf;
1929 uint8_t *buf = ops->datbuf;
1930 int ret, subpage;
1931
1932 ops->retlen = 0;
1933 if (!writelen)
1934 return 0;
1935
1936 column = to & (mtd->writesize - 1);
1937 subpage = column || (writelen & (mtd->writesize - 1));
1938
1939 if (subpage && oob)
1940 return -EINVAL;
1941
1942 chipnr = (int)(to >> chip->chip_shift);
1943 chip->select_chip(mtd, chipnr);
1944
1945 /* Check, if it is write protected */
1946 if (nand_check_wp(mtd)) {
1947 printk (KERN_NOTICE "nand_do_write_ops: Device is write protected\n");
1948 return -EIO;
1949 }
1950
1951 realpage = (int)(to >> chip->page_shift);
1952 page = realpage & chip->pagemask;
1953 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1954
1955 /* Invalidate the page cache, when we write to the cached page */
1956 if (to <= (chip->pagebuf << chip->page_shift) &&
1957 (chip->pagebuf << chip->page_shift) < (to + ops->len))
1958 chip->pagebuf = -1;
1959
1960 /* If we're not given explicit OOB data, let it be 0xFF */
1961 if (likely(!oob))
1962 memset(chip->oob_poi, 0xff, mtd->oobsize);
1963
1964 /* Don't allow multipage oob writes with offset */
1965 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen))
1966 return -EINVAL;
1967
1968 while (1) {
1969 WATCHDOG_RESET();
1970
1971 int bytes = mtd->writesize;
1972 int cached = writelen > bytes && page != blockmask;
1973 uint8_t *wbuf = buf;
1974
1975 /* Partial page write ? */
1976 if (unlikely(column || writelen < (mtd->writesize - 1))) {
1977 cached = 0;
1978 bytes = min_t(int, bytes - column, (int) writelen);
1979 chip->pagebuf = -1;
1980 memset(chip->buffers->databuf, 0xff, mtd->writesize);
1981 memcpy(&chip->buffers->databuf[column], buf, bytes);
1982 wbuf = chip->buffers->databuf;
1983 }
1984
1985 if (unlikely(oob)) {
1986 size_t len = min(oobwritelen, oobmaxlen);
1987 oob = nand_fill_oob(chip, oob, len, ops);
1988 oobwritelen -= len;
1989 }
1990
1991 ret = chip->write_page(mtd, chip, wbuf, page, cached,
1992 (ops->mode == MTD_OOB_RAW));
1993 if (ret)
1994 break;
1995
1996 writelen -= bytes;
1997 if (!writelen)
1998 break;
1999
2000 column = 0;
2001 buf += bytes;
2002 realpage++;
2003
2004 page = realpage & chip->pagemask;
2005 /* Check, if we cross a chip boundary */
2006 if (!page) {
2007 chipnr++;
2008 chip->select_chip(mtd, -1);
2009 chip->select_chip(mtd, chipnr);
2010 }
2011 }
2012
2013 ops->retlen = ops->len - writelen;
2014 if (unlikely(oob))
2015 ops->oobretlen = ops->ooblen;
2016 return ret;
2017 }
2018
2019 /**
2020 * nand_write - [MTD Interface] NAND write with ECC
2021 * @mtd: MTD device structure
2022 * @to: offset to write to
2023 * @len: number of bytes to write
2024 * @retlen: pointer to variable to store the number of written bytes
2025 * @buf: the data to write
2026 *
2027 * NAND write with ECC
2028 */
2029 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2030 size_t *retlen, const uint8_t *buf)
2031 {
2032 struct nand_chip *chip = mtd->priv;
2033 int ret;
2034
2035 /* Do not allow writes past end of device */
2036 if ((to + len) > mtd->size)
2037 return -EINVAL;
2038 if (!len)
2039 return 0;
2040
2041 nand_get_device(chip, mtd, FL_WRITING);
2042
2043 chip->ops.len = len;
2044 chip->ops.datbuf = (uint8_t *)buf;
2045 chip->ops.oobbuf = NULL;
2046
2047 ret = nand_do_write_ops(mtd, to, &chip->ops);
2048
2049 *retlen = chip->ops.retlen;
2050
2051 nand_release_device(mtd);
2052
2053 return ret;
2054 }
2055
2056 /**
2057 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2058 * @mtd: MTD device structure
2059 * @to: offset to write to
2060 * @ops: oob operation description structure
2061 *
2062 * NAND write out-of-band
2063 */
2064 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2065 struct mtd_oob_ops *ops)
2066 {
2067 int chipnr, page, status, len;
2068 struct nand_chip *chip = mtd->priv;
2069
2070 MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: to = 0x%08x, len = %i\n",
2071 __func__, (unsigned int)to, (int)ops->ooblen);
2072
2073 if (ops->mode == MTD_OOB_AUTO)
2074 len = chip->ecc.layout->oobavail;
2075 else
2076 len = mtd->oobsize;
2077
2078 /* Do not allow write past end of page */
2079 if ((ops->ooboffs + ops->ooblen) > len) {
2080 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to write "
2081 "past end of page\n", __func__);
2082 return -EINVAL;
2083 }
2084
2085 if (unlikely(ops->ooboffs >= len)) {
2086 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start "
2087 "write outside oob\n", __func__);
2088 return -EINVAL;
2089 }
2090
2091 /* Do not allow write past end of device */
2092 if (unlikely(to >= mtd->size ||
2093 ops->ooboffs + ops->ooblen >
2094 ((mtd->size >> chip->page_shift) -
2095 (to >> chip->page_shift)) * len)) {
2096 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2097 "end of device\n", __func__);
2098 return -EINVAL;
2099 }
2100
2101 chipnr = (int)(to >> chip->chip_shift);
2102 chip->select_chip(mtd, chipnr);
2103
2104 /* Shift to get page */
2105 page = (int)(to >> chip->page_shift);
2106
2107 /*
2108 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2109 * of my DiskOnChip 2000 test units) will clear the whole data page too
2110 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2111 * it in the doc2000 driver in August 1999. dwmw2.
2112 */
2113 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2114
2115 /* Check, if it is write protected */
2116 if (nand_check_wp(mtd))
2117 return -EROFS;
2118
2119 /* Invalidate the page cache, if we write to the cached page */
2120 if (page == chip->pagebuf)
2121 chip->pagebuf = -1;
2122
2123 memset(chip->oob_poi, 0xff, mtd->oobsize);
2124 nand_fill_oob(chip, ops->oobbuf, ops->ooblen, ops);
2125 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2126 memset(chip->oob_poi, 0xff, mtd->oobsize);
2127
2128 if (status)
2129 return status;
2130
2131 ops->oobretlen = ops->ooblen;
2132
2133 return 0;
2134 }
2135
2136 /**
2137 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2138 * @mtd: MTD device structure
2139 * @to: offset to write to
2140 * @ops: oob operation description structure
2141 */
2142 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2143 struct mtd_oob_ops *ops)
2144 {
2145 struct nand_chip *chip = mtd->priv;
2146 int ret = -ENOTSUPP;
2147
2148 ops->retlen = 0;
2149
2150 /* Do not allow writes past end of device */
2151 if (ops->datbuf && (to + ops->len) > mtd->size) {
2152 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2153 "end of device\n", __func__);
2154 return -EINVAL;
2155 }
2156
2157 nand_get_device(chip, mtd, FL_WRITING);
2158
2159 switch (ops->mode) {
2160 case MTD_OOB_PLACE:
2161 case MTD_OOB_AUTO:
2162 case MTD_OOB_RAW:
2163 break;
2164
2165 default:
2166 goto out;
2167 }
2168
2169 if (!ops->datbuf)
2170 ret = nand_do_write_oob(mtd, to, ops);
2171 else
2172 ret = nand_do_write_ops(mtd, to, ops);
2173
2174 out:
2175 nand_release_device(mtd);
2176 return ret;
2177 }
2178
2179 /**
2180 * single_erease_cmd - [GENERIC] NAND standard block erase command function
2181 * @mtd: MTD device structure
2182 * @page: the page address of the block which will be erased
2183 *
2184 * Standard erase command for NAND chips
2185 */
2186 static void single_erase_cmd(struct mtd_info *mtd, int page)
2187 {
2188 struct nand_chip *chip = mtd->priv;
2189 /* Send commands to erase a block */
2190 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2191 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2192 }
2193
2194 /**
2195 * multi_erease_cmd - [GENERIC] AND specific block erase command function
2196 * @mtd: MTD device structure
2197 * @page: the page address of the block which will be erased
2198 *
2199 * AND multi block erase command function
2200 * Erase 4 consecutive blocks
2201 */
2202 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2203 {
2204 struct nand_chip *chip = mtd->priv;
2205 /* Send commands to erase a block */
2206 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2207 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2208 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2209 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2210 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2211 }
2212
2213 /**
2214 * nand_erase - [MTD Interface] erase block(s)
2215 * @mtd: MTD device structure
2216 * @instr: erase instruction
2217 *
2218 * Erase one ore more blocks
2219 */
2220 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2221 {
2222 return nand_erase_nand(mtd, instr, 0);
2223 }
2224
2225 #define BBT_PAGE_MASK 0xffffff3f
2226 /**
2227 * nand_erase_nand - [Internal] erase block(s)
2228 * @mtd: MTD device structure
2229 * @instr: erase instruction
2230 * @allowbbt: allow erasing the bbt area
2231 *
2232 * Erase one ore more blocks
2233 */
2234 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2235 int allowbbt)
2236 {
2237 int page, status, pages_per_block, ret, chipnr;
2238 struct nand_chip *chip = mtd->priv;
2239 loff_t rewrite_bbt[CONFIG_SYS_NAND_MAX_CHIPS] = {0};
2240 unsigned int bbt_masked_page = 0xffffffff;
2241 loff_t len;
2242
2243 MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
2244 __func__, (unsigned long long)instr->addr,
2245 (unsigned long long)instr->len);
2246
2247 if (check_offs_len(mtd, instr->addr, instr->len))
2248 return -EINVAL;
2249
2250 instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
2251
2252 /* Grab the lock and see if the device is available */
2253 nand_get_device(chip, mtd, FL_ERASING);
2254
2255 /* Shift to get first page */
2256 page = (int)(instr->addr >> chip->page_shift);
2257 chipnr = (int)(instr->addr >> chip->chip_shift);
2258
2259 /* Calculate pages in each block */
2260 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2261
2262 /* Select the NAND device */
2263 chip->select_chip(mtd, chipnr);
2264
2265 /* Check, if it is write protected */
2266 if (nand_check_wp(mtd)) {
2267 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
2268 __func__);
2269 instr->state = MTD_ERASE_FAILED;
2270 goto erase_exit;
2271 }
2272
2273 /*
2274 * If BBT requires refresh, set the BBT page mask to see if the BBT
2275 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2276 * can not be matched. This is also done when the bbt is actually
2277 * erased to avoid recusrsive updates
2278 */
2279 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2280 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2281
2282 /* Loop through the pages */
2283 len = instr->len;
2284
2285 instr->state = MTD_ERASING;
2286
2287 while (len) {
2288 WATCHDOG_RESET();
2289 /*
2290 * heck if we have a bad block, we do not erase bad blocks !
2291 */
2292 if (!instr->scrub && nand_block_checkbad(mtd, ((loff_t) page) <<
2293 chip->page_shift, 0, allowbbt)) {
2294 printk(KERN_WARNING "%s: attempt to erase a bad block "
2295 "at page 0x%08x\n", __func__, page);
2296 instr->state = MTD_ERASE_FAILED;
2297 goto erase_exit;
2298 }
2299
2300 /*
2301 * Invalidate the page cache, if we erase the block which
2302 * contains the current cached page
2303 */
2304 if (page <= chip->pagebuf && chip->pagebuf <
2305 (page + pages_per_block))
2306 chip->pagebuf = -1;
2307
2308 chip->erase_cmd(mtd, page & chip->pagemask);
2309
2310 status = chip->waitfunc(mtd, chip);
2311
2312 /*
2313 * See if operation failed and additional status checks are
2314 * available
2315 */
2316 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2317 status = chip->errstat(mtd, chip, FL_ERASING,
2318 status, page);
2319
2320 /* See if block erase succeeded */
2321 if (status & NAND_STATUS_FAIL) {
2322 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Failed erase, "
2323 "page 0x%08x\n", __func__, page);
2324 instr->state = MTD_ERASE_FAILED;
2325 instr->fail_addr =
2326 ((loff_t)page << chip->page_shift);
2327 goto erase_exit;
2328 }
2329
2330 /*
2331 * If BBT requires refresh, set the BBT rewrite flag to the
2332 * page being erased
2333 */
2334 if (bbt_masked_page != 0xffffffff &&
2335 (page & BBT_PAGE_MASK) == bbt_masked_page)
2336 rewrite_bbt[chipnr] =
2337 ((loff_t)page << chip->page_shift);
2338
2339 /* Increment page address and decrement length */
2340 len -= (1 << chip->phys_erase_shift);
2341 page += pages_per_block;
2342
2343 /* Check, if we cross a chip boundary */
2344 if (len && !(page & chip->pagemask)) {
2345 chipnr++;
2346 chip->select_chip(mtd, -1);
2347 chip->select_chip(mtd, chipnr);
2348
2349 /*
2350 * If BBT requires refresh and BBT-PERCHIP, set the BBT
2351 * page mask to see if this BBT should be rewritten
2352 */
2353 if (bbt_masked_page != 0xffffffff &&
2354 (chip->bbt_td->options & NAND_BBT_PERCHIP))
2355 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2356 BBT_PAGE_MASK;
2357 }
2358 }
2359 instr->state = MTD_ERASE_DONE;
2360
2361 erase_exit:
2362
2363 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2364
2365 /* Deselect and wake up anyone waiting on the device */
2366 nand_release_device(mtd);
2367
2368 /* Do call back function */
2369 if (!ret)
2370 mtd_erase_callback(instr);
2371
2372 /*
2373 * If BBT requires refresh and erase was successful, rewrite any
2374 * selected bad block tables
2375 */
2376 if (bbt_masked_page == 0xffffffff || ret)
2377 return ret;
2378
2379 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2380 if (!rewrite_bbt[chipnr])
2381 continue;
2382 /* update the BBT for chip */
2383 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: nand_update_bbt "
2384 "(%d:0x%0llx 0x%0x)\n", __func__, chipnr,
2385 rewrite_bbt[chipnr], chip->bbt_td->pages[chipnr]);
2386 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2387 }
2388
2389 /* Return more or less happy */
2390 return ret;
2391 }
2392
2393 /**
2394 * nand_sync - [MTD Interface] sync
2395 * @mtd: MTD device structure
2396 *
2397 * Sync is actually a wait for chip ready function
2398 */
2399 static void nand_sync(struct mtd_info *mtd)
2400 {
2401 struct nand_chip *chip = mtd->priv;
2402
2403 MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: called\n", __func__);
2404
2405 /* Grab the lock and see if the device is available */
2406 nand_get_device(chip, mtd, FL_SYNCING);
2407 /* Release it and go back */
2408 nand_release_device(mtd);
2409 }
2410
2411 /**
2412 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2413 * @mtd: MTD device structure
2414 * @offs: offset relative to mtd start
2415 */
2416 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2417 {
2418 /* Check for invalid offset */
2419 if (offs > mtd->size)
2420 return -EINVAL;
2421
2422 return nand_block_checkbad(mtd, offs, 1, 0);
2423 }
2424
2425 /**
2426 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2427 * @mtd: MTD device structure
2428 * @ofs: offset relative to mtd start
2429 */
2430 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2431 {
2432 struct nand_chip *chip = mtd->priv;
2433 int ret;
2434
2435 ret = nand_block_isbad(mtd, ofs);
2436 if (ret) {
2437 /* If it was bad already, return success and do nothing. */
2438 if (ret > 0)
2439 return 0;
2440 return ret;
2441 }
2442
2443 return chip->block_markbad(mtd, ofs);
2444 }
2445
2446 /*
2447 * Set default functions
2448 */
2449 static void nand_set_defaults(struct nand_chip *chip, int busw)
2450 {
2451 /* check for proper chip_delay setup, set 20us if not */
2452 if (!chip->chip_delay)
2453 chip->chip_delay = 20;
2454
2455 /* check, if a user supplied command function given */
2456 if (chip->cmdfunc == NULL)
2457 chip->cmdfunc = nand_command;
2458
2459 /* check, if a user supplied wait function given */
2460 if (chip->waitfunc == NULL)
2461 chip->waitfunc = nand_wait;
2462
2463 if (!chip->select_chip)
2464 chip->select_chip = nand_select_chip;
2465 if (!chip->read_byte)
2466 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2467 if (!chip->read_word)
2468 chip->read_word = nand_read_word;
2469 if (!chip->block_bad)
2470 chip->block_bad = nand_block_bad;
2471 if (!chip->block_markbad)
2472 chip->block_markbad = nand_default_block_markbad;
2473 if (!chip->write_buf)
2474 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2475 if (!chip->read_buf)
2476 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2477 if (!chip->verify_buf)
2478 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2479 if (!chip->scan_bbt)
2480 chip->scan_bbt = nand_default_bbt;
2481 if (!chip->controller)
2482 chip->controller = &chip->hwcontrol;
2483 }
2484
2485 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
2486 /*
2487 * sanitize ONFI strings so we can safely print them
2488 */
2489 static void sanitize_string(char *s, size_t len)
2490 {
2491 ssize_t i;
2492
2493 /* null terminate */
2494 s[len - 1] = 0;
2495
2496 /* remove non printable chars */
2497 for (i = 0; i < len - 1; i++) {
2498 if (s[i] < ' ' || s[i] > 127)
2499 s[i] = '?';
2500 }
2501
2502 /* remove trailing spaces */
2503 strim(s);
2504 }
2505
2506 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2507 {
2508 int i;
2509 while (len--) {
2510 crc ^= *p++ << 8;
2511 for (i = 0; i < 8; i++)
2512 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2513 }
2514
2515 return crc;
2516 }
2517
2518 /*
2519 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise
2520 */
2521 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
2522 int *busw)
2523 {
2524 struct nand_onfi_params *p = &chip->onfi_params;
2525 int i;
2526 int val;
2527
2528 /* try ONFI for unknow chip or LP */
2529 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
2530 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
2531 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
2532 return 0;
2533
2534 MTDDEBUG(MTD_DEBUG_LEVEL0, "ONFI flash detected\n");
2535 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2536 for (i = 0; i < 3; i++) {
2537 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
2538 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
2539 le16_to_cpu(p->crc)) {
2540 MTDDEBUG(MTD_DEBUG_LEVEL0,
2541 "ONFI param page %d valid\n", i);
2542 break;
2543 }
2544 }
2545
2546 if (i == 3)
2547 return 0;
2548
2549 /* check version */
2550 val = le16_to_cpu(p->revision);
2551 if (val & (1 << 5))
2552 chip->onfi_version = 23;
2553 else if (val & (1 << 4))
2554 chip->onfi_version = 22;
2555 else if (val & (1 << 3))
2556 chip->onfi_version = 21;
2557 else if (val & (1 << 2))
2558 chip->onfi_version = 20;
2559 else if (val & (1 << 1))
2560 chip->onfi_version = 10;
2561 else
2562 chip->onfi_version = 0;
2563
2564 if (!chip->onfi_version) {
2565 printk(KERN_INFO "%s: unsupported ONFI version: %d\n",
2566 __func__, val);
2567 return 0;
2568 }
2569
2570 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
2571 sanitize_string(p->model, sizeof(p->model));
2572 if (!mtd->name)
2573 mtd->name = p->model;
2574 mtd->writesize = le32_to_cpu(p->byte_per_page);
2575 mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
2576 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
2577 chip->chipsize = le32_to_cpu(p->blocks_per_lun);
2578 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
2579 *busw = 0;
2580 if (le16_to_cpu(p->features) & 1)
2581 *busw = NAND_BUSWIDTH_16;
2582
2583 chip->options |= NAND_NO_READRDY | NAND_NO_AUTOINCR;
2584
2585 return 1;
2586 }
2587 #else
2588 static inline int nand_flash_detect_onfi(struct mtd_info *mtd,
2589 struct nand_chip *chip,
2590 int *busw)
2591 {
2592 return 0;
2593 }
2594 #endif
2595
2596 /*
2597 * Get the flash and manufacturer id and lookup if the type is supported
2598 */
2599 static const struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2600 struct nand_chip *chip,
2601 int busw,
2602 int *maf_id, int *dev_id,
2603 const struct nand_flash_dev *type)
2604 {
2605 const char *name;
2606 int i, maf_idx;
2607 u8 id_data[8];
2608 int ret;
2609
2610 /* Select the device */
2611 chip->select_chip(mtd, 0);
2612
2613 /*
2614 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2615 * after power-up
2616 */
2617 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2618
2619 /* Send the command for reading device ID */
2620 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2621
2622 /* Read manufacturer and device IDs */
2623 *maf_id = chip->read_byte(mtd);
2624 *dev_id = chip->read_byte(mtd);
2625
2626 /* Try again to make sure, as some systems the bus-hold or other
2627 * interface concerns can cause random data which looks like a
2628 * possibly credible NAND flash to appear. If the two results do
2629 * not match, ignore the device completely.
2630 */
2631
2632 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2633
2634 for (i = 0; i < 2; i++)
2635 id_data[i] = chip->read_byte(mtd);
2636
2637 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
2638 printk(KERN_INFO "%s: second ID read did not match "
2639 "%02x,%02x against %02x,%02x\n", __func__,
2640 *maf_id, *dev_id, id_data[0], id_data[1]);
2641 return ERR_PTR(-ENODEV);
2642 }
2643
2644 if (!type)
2645 type = nand_flash_ids;
2646
2647 for (; type->name != NULL; type++)
2648 if (*dev_id == type->id)
2649 break;
2650
2651 chip->onfi_version = 0;
2652 if (!type->name || !type->pagesize) {
2653 /* Check is chip is ONFI compliant */
2654 ret = nand_flash_detect_onfi(mtd, chip, &busw);
2655 if (ret)
2656 goto ident_done;
2657 }
2658
2659 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2660
2661 /* Read entire ID string */
2662
2663 for (i = 0; i < 8; i++)
2664 id_data[i] = chip->read_byte(mtd);
2665
2666 if (!type->name)
2667 return ERR_PTR(-ENODEV);
2668
2669 if (!mtd->name)
2670 mtd->name = type->name;
2671
2672 chip->chipsize = (uint64_t)type->chipsize << 20;
2673
2674 if (!type->pagesize && chip->init_size) {
2675 /* set the pagesize, oobsize, erasesize by the driver*/
2676 busw = chip->init_size(mtd, chip, id_data);
2677 } else if (!type->pagesize) {
2678 int extid;
2679 /* The 3rd id byte holds MLC / multichip data */
2680 chip->cellinfo = id_data[2];
2681 /* The 4th id byte is the important one */
2682 extid = id_data[3];
2683
2684 /*
2685 * Field definitions are in the following datasheets:
2686 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
2687 * New style (6 byte ID): Samsung K9GBG08U0M (p.40)
2688 *
2689 * Check for wraparound + Samsung ID + nonzero 6th byte
2690 * to decide what to do.
2691 */
2692 if (id_data[0] == id_data[6] && id_data[1] == id_data[7] &&
2693 id_data[0] == NAND_MFR_SAMSUNG &&
2694 (chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
2695 id_data[5] != 0x00) {
2696 /* Calc pagesize */
2697 mtd->writesize = 2048 << (extid & 0x03);
2698 extid >>= 2;
2699 /* Calc oobsize */
2700 switch (extid & 0x03) {
2701 case 1:
2702 mtd->oobsize = 128;
2703 break;
2704 case 2:
2705 mtd->oobsize = 218;
2706 break;
2707 case 3:
2708 mtd->oobsize = 400;
2709 break;
2710 default:
2711 mtd->oobsize = 436;
2712 break;
2713 }
2714 extid >>= 2;
2715 /* Calc blocksize */
2716 mtd->erasesize = (128 * 1024) <<
2717 (((extid >> 1) & 0x04) | (extid & 0x03));
2718 busw = 0;
2719 } else {
2720 /* Calc pagesize */
2721 mtd->writesize = 1024 << (extid & 0x03);
2722 extid >>= 2;
2723 /* Calc oobsize */
2724 mtd->oobsize = (8 << (extid & 0x01)) *
2725 (mtd->writesize >> 9);
2726 extid >>= 2;
2727 /* Calc blocksize. Blocksize is multiples of 64KiB */
2728 mtd->erasesize = (64 * 1024) << (extid & 0x03);
2729 extid >>= 2;
2730 /* Get buswidth information */
2731 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
2732 }
2733 } else {
2734 /*
2735 * Old devices have chip data hardcoded in the device id table
2736 */
2737 mtd->erasesize = type->erasesize;
2738 mtd->writesize = type->pagesize;
2739 mtd->oobsize = mtd->writesize / 32;
2740 busw = type->options & NAND_BUSWIDTH_16;
2741
2742 /*
2743 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
2744 * some Spansion chips have erasesize that conflicts with size
2745 * listed in nand_ids table
2746 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
2747 */
2748 if (*maf_id == NAND_MFR_AMD && id_data[4] != 0x00 &&
2749 id_data[5] == 0x00 && id_data[6] == 0x00 &&
2750 id_data[7] == 0x00 && mtd->writesize == 512) {
2751 mtd->erasesize = 128 * 1024;
2752 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
2753 }
2754 }
2755 /* Get chip options, preserve non chip based options */
2756 chip->options |= type->options;
2757
2758 /* Check if chip is a not a samsung device. Do not clear the
2759 * options for chips which are not having an extended id.
2760 */
2761 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
2762 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
2763 ident_done:
2764
2765 /*
2766 * Set chip as a default. Board drivers can override it, if necessary
2767 */
2768 chip->options |= NAND_NO_AUTOINCR;
2769
2770 /* Try to identify manufacturer */
2771 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
2772 if (nand_manuf_ids[maf_idx].id == *maf_id)
2773 break;
2774 }
2775
2776 /*
2777 * Check, if buswidth is correct. Hardware drivers should set
2778 * chip correct !
2779 */
2780 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
2781 printk(KERN_INFO "NAND device: Manufacturer ID:"
2782 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2783 *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2784 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
2785 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
2786 busw ? 16 : 8);
2787 return ERR_PTR(-EINVAL);
2788 }
2789
2790 /* Calculate the address shift from the page size */
2791 chip->page_shift = ffs(mtd->writesize) - 1;
2792 /* Convert chipsize to number of pages per chip -1. */
2793 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2794
2795 chip->bbt_erase_shift = chip->phys_erase_shift =
2796 ffs(mtd->erasesize) - 1;
2797 if (chip->chipsize & 0xffffffff)
2798 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
2799 else {
2800 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
2801 chip->chip_shift += 32 - 1;
2802 }
2803
2804 chip->badblockbits = 8;
2805
2806 /* Set the bad block position */
2807 if (mtd->writesize > 512 || (busw & NAND_BUSWIDTH_16))
2808 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
2809 else
2810 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
2811
2812 /*
2813 * Bad block marker is stored in the last page of each block
2814 * on Samsung and Hynix MLC devices; stored in first two pages
2815 * of each block on Micron devices with 2KiB pages and on
2816 * SLC Samsung, Hynix, Toshiba and AMD/Spansion. All others scan
2817 * only the first page.
2818 */
2819 if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
2820 (*maf_id == NAND_MFR_SAMSUNG ||
2821 *maf_id == NAND_MFR_HYNIX))
2822 chip->options |= NAND_BBT_SCANLASTPAGE;
2823 else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
2824 (*maf_id == NAND_MFR_SAMSUNG ||
2825 *maf_id == NAND_MFR_HYNIX ||
2826 *maf_id == NAND_MFR_TOSHIBA ||
2827 *maf_id == NAND_MFR_AMD)) ||
2828 (mtd->writesize == 2048 &&
2829 *maf_id == NAND_MFR_MICRON))
2830 chip->options |= NAND_BBT_SCAN2NDPAGE;
2831
2832 /*
2833 * Numonyx/ST 2K pages, x8 bus use BOTH byte 1 and 6
2834 */
2835 if (!(busw & NAND_BUSWIDTH_16) &&
2836 *maf_id == NAND_MFR_STMICRO &&
2837 mtd->writesize == 2048) {
2838 chip->options |= NAND_BBT_SCANBYTE1AND6;
2839 chip->badblockpos = 0;
2840 }
2841
2842 /* Check for AND chips with 4 page planes */
2843 if (chip->options & NAND_4PAGE_ARRAY)
2844 chip->erase_cmd = multi_erase_cmd;
2845 else
2846 chip->erase_cmd = single_erase_cmd;
2847
2848 /* Do not replace user supplied command function ! */
2849 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
2850 chip->cmdfunc = nand_command_lp;
2851
2852 /* TODO onfi flash name */
2853 name = type->name;
2854 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
2855 if (chip->onfi_version)
2856 name = chip->onfi_params.model;
2857 #endif
2858 MTDDEBUG(MTD_DEBUG_LEVEL0, "NAND device: Manufacturer ID:"
2859 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, *dev_id,
2860 nand_manuf_ids[maf_idx].name, name);
2861
2862 return type;
2863 }
2864
2865 /**
2866 * nand_scan_ident - [NAND Interface] Scan for the NAND device
2867 * @mtd: MTD device structure
2868 * @maxchips: Number of chips to scan for
2869 * @table: Alternative NAND ID table
2870 *
2871 * This is the first phase of the normal nand_scan() function. It
2872 * reads the flash ID and sets up MTD fields accordingly.
2873 *
2874 * The mtd->owner field must be set to the module of the caller.
2875 */
2876 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
2877 const struct nand_flash_dev *table)
2878 {
2879 int i, busw, nand_maf_id, nand_dev_id;
2880 struct nand_chip *chip = mtd->priv;
2881 const struct nand_flash_dev *type;
2882
2883 /* Get buswidth to select the correct functions */
2884 busw = chip->options & NAND_BUSWIDTH_16;
2885 /* Set the default functions */
2886 nand_set_defaults(chip, busw);
2887
2888 /* Read the flash type */
2889 type = nand_get_flash_type(mtd, chip, busw,
2890 &nand_maf_id, &nand_dev_id, table);
2891
2892 if (IS_ERR(type)) {
2893 #ifndef CONFIG_SYS_NAND_QUIET_TEST
2894 printk(KERN_WARNING "No NAND device found!!!\n");
2895 #endif
2896 chip->select_chip(mtd, -1);
2897 return PTR_ERR(type);
2898 }
2899
2900 /* Check for a chip array */
2901 for (i = 1; i < maxchips; i++) {
2902 chip->select_chip(mtd, i);
2903 /* See comment in nand_get_flash_type for reset */
2904 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2905 /* Send the command for reading device ID */
2906 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2907 /* Read manufacturer and device IDs */
2908 if (nand_maf_id != chip->read_byte(mtd) ||
2909 nand_dev_id != chip->read_byte(mtd))
2910 break;
2911 }
2912 #ifdef DEBUG
2913 if (i > 1)
2914 printk(KERN_INFO "%d NAND chips detected\n", i);
2915 #endif
2916
2917 /* Store the number of chips and calc total size for mtd */
2918 chip->numchips = i;
2919 mtd->size = i * chip->chipsize;
2920
2921 return 0;
2922 }
2923
2924
2925 /**
2926 * nand_scan_tail - [NAND Interface] Scan for the NAND device
2927 * @mtd: MTD device structure
2928 *
2929 * This is the second phase of the normal nand_scan() function. It
2930 * fills out all the uninitialized function pointers with the defaults
2931 * and scans for a bad block table if appropriate.
2932 */
2933 int nand_scan_tail(struct mtd_info *mtd)
2934 {
2935 int i;
2936 struct nand_chip *chip = mtd->priv;
2937
2938 if (!(chip->options & NAND_OWN_BUFFERS))
2939 chip->buffers = memalign(ARCH_DMA_MINALIGN,
2940 sizeof(*chip->buffers));
2941 if (!chip->buffers)
2942 return -ENOMEM;
2943
2944 /* Set the internal oob buffer location, just after the page data */
2945 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
2946
2947 /*
2948 * If no default placement scheme is given, select an appropriate one
2949 */
2950 if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) {
2951 switch (mtd->oobsize) {
2952 case 8:
2953 chip->ecc.layout = &nand_oob_8;
2954 break;
2955 case 16:
2956 chip->ecc.layout = &nand_oob_16;
2957 break;
2958 case 64:
2959 chip->ecc.layout = &nand_oob_64;
2960 break;
2961 case 128:
2962 chip->ecc.layout = &nand_oob_128;
2963 break;
2964 default:
2965 printk(KERN_WARNING "No oob scheme defined for "
2966 "oobsize %d\n", mtd->oobsize);
2967 }
2968 }
2969
2970 if (!chip->write_page)
2971 chip->write_page = nand_write_page;
2972
2973 /*
2974 * check ECC mode, default to software if 3byte/512byte hardware ECC is
2975 * selected and we have 256 byte pagesize fallback to software ECC
2976 */
2977
2978 switch (chip->ecc.mode) {
2979 case NAND_ECC_HW_OOB_FIRST:
2980 /* Similar to NAND_ECC_HW, but a separate read_page handle */
2981 if (!chip->ecc.calculate || !chip->ecc.correct ||
2982 !chip->ecc.hwctl) {
2983 printk(KERN_WARNING "No ECC functions supplied; "
2984 "Hardware ECC not possible\n");
2985 BUG();
2986 }
2987 if (!chip->ecc.read_page)
2988 chip->ecc.read_page = nand_read_page_hwecc_oob_first;
2989
2990 case NAND_ECC_HW:
2991 /* Use standard hwecc read page function ? */
2992 if (!chip->ecc.read_page)
2993 chip->ecc.read_page = nand_read_page_hwecc;
2994 if (!chip->ecc.write_page)
2995 chip->ecc.write_page = nand_write_page_hwecc;
2996 if (!chip->ecc.read_page_raw)
2997 chip->ecc.read_page_raw = nand_read_page_raw;
2998 if (!chip->ecc.write_page_raw)
2999 chip->ecc.write_page_raw = nand_write_page_raw;
3000 if (!chip->ecc.read_oob)
3001 chip->ecc.read_oob = nand_read_oob_std;
3002 if (!chip->ecc.write_oob)
3003 chip->ecc.write_oob = nand_write_oob_std;
3004
3005 case NAND_ECC_HW_SYNDROME:
3006 if ((!chip->ecc.calculate || !chip->ecc.correct ||
3007 !chip->ecc.hwctl) &&
3008 (!chip->ecc.read_page ||
3009 chip->ecc.read_page == nand_read_page_hwecc ||
3010 !chip->ecc.write_page ||
3011 chip->ecc.write_page == nand_write_page_hwecc)) {
3012 printk(KERN_WARNING "No ECC functions supplied; "
3013 "Hardware ECC not possible\n");
3014 BUG();
3015 }
3016 /* Use standard syndrome read/write page function ? */
3017 if (!chip->ecc.read_page)
3018 chip->ecc.read_page = nand_read_page_syndrome;
3019 if (!chip->ecc.write_page)
3020 chip->ecc.write_page = nand_write_page_syndrome;
3021 if (!chip->ecc.read_page_raw)
3022 chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
3023 if (!chip->ecc.write_page_raw)
3024 chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
3025 if (!chip->ecc.read_oob)
3026 chip->ecc.read_oob = nand_read_oob_syndrome;
3027 if (!chip->ecc.write_oob)
3028 chip->ecc.write_oob = nand_write_oob_syndrome;
3029
3030 if (mtd->writesize >= chip->ecc.size)
3031 break;
3032 printk(KERN_WARNING "%d byte HW ECC not possible on "
3033 "%d byte page size, fallback to SW ECC\n",
3034 chip->ecc.size, mtd->writesize);
3035 chip->ecc.mode = NAND_ECC_SOFT;
3036
3037 case NAND_ECC_SOFT:
3038 chip->ecc.calculate = nand_calculate_ecc;
3039 chip->ecc.correct = nand_correct_data;
3040 chip->ecc.read_page = nand_read_page_swecc;
3041 chip->ecc.read_subpage = nand_read_subpage;
3042 chip->ecc.write_page = nand_write_page_swecc;
3043 chip->ecc.read_page_raw = nand_read_page_raw;
3044 chip->ecc.write_page_raw = nand_write_page_raw;
3045 chip->ecc.read_oob = nand_read_oob_std;
3046 chip->ecc.write_oob = nand_write_oob_std;
3047 if (!chip->ecc.size)
3048 chip->ecc.size = 256;
3049 chip->ecc.bytes = 3;
3050 break;
3051
3052 case NAND_ECC_SOFT_BCH:
3053 if (!mtd_nand_has_bch()) {
3054 printk(KERN_WARNING "CONFIG_MTD_ECC_BCH not enabled\n");
3055 return -EINVAL;
3056 }
3057 chip->ecc.calculate = nand_bch_calculate_ecc;
3058 chip->ecc.correct = nand_bch_correct_data;
3059 chip->ecc.read_page = nand_read_page_swecc;
3060 chip->ecc.read_subpage = nand_read_subpage;
3061 chip->ecc.write_page = nand_write_page_swecc;
3062 chip->ecc.read_page_raw = nand_read_page_raw;
3063 chip->ecc.write_page_raw = nand_write_page_raw;
3064 chip->ecc.read_oob = nand_read_oob_std;
3065 chip->ecc.write_oob = nand_write_oob_std;
3066 /*
3067 * Board driver should supply ecc.size and ecc.bytes values to
3068 * select how many bits are correctable; see nand_bch_init()
3069 * for details.
3070 * Otherwise, default to 4 bits for large page devices
3071 */
3072 if (!chip->ecc.size && (mtd->oobsize >= 64)) {
3073 chip->ecc.size = 512;
3074 chip->ecc.bytes = 7;
3075 }
3076 chip->ecc.priv = nand_bch_init(mtd,
3077 chip->ecc.size,
3078 chip->ecc.bytes,
3079 &chip->ecc.layout);
3080 if (!chip->ecc.priv)
3081 printk(KERN_WARNING "BCH ECC initialization failed!\n");
3082
3083 break;
3084
3085 case NAND_ECC_NONE:
3086 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
3087 "This is not recommended !!\n");
3088 chip->ecc.read_page = nand_read_page_raw;
3089 chip->ecc.write_page = nand_write_page_raw;
3090 chip->ecc.read_oob = nand_read_oob_std;
3091 chip->ecc.read_page_raw = nand_read_page_raw;
3092 chip->ecc.write_page_raw = nand_write_page_raw;
3093 chip->ecc.write_oob = nand_write_oob_std;
3094 chip->ecc.size = mtd->writesize;
3095 chip->ecc.bytes = 0;
3096 break;
3097
3098 default:
3099 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
3100 chip->ecc.mode);
3101 BUG();
3102 }
3103
3104 /*
3105 * The number of bytes available for a client to place data into
3106 * the out of band area
3107 */
3108 chip->ecc.layout->oobavail = 0;
3109 for (i = 0; chip->ecc.layout->oobfree[i].length
3110 && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
3111 chip->ecc.layout->oobavail +=
3112 chip->ecc.layout->oobfree[i].length;
3113 mtd->oobavail = chip->ecc.layout->oobavail;
3114
3115 /*
3116 * Set the number of read / write steps for one page depending on ECC
3117 * mode
3118 */
3119 chip->ecc.steps = mtd->writesize / chip->ecc.size;
3120 if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
3121 printk(KERN_WARNING "Invalid ecc parameters\n");
3122 BUG();
3123 }
3124 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
3125
3126 /*
3127 * Allow subpage writes up to ecc.steps. Not possible for MLC
3128 * FLASH.
3129 */
3130 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
3131 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
3132 switch (chip->ecc.steps) {
3133 case 2:
3134 mtd->subpage_sft = 1;
3135 break;
3136 case 4:
3137 case 8:
3138 case 16:
3139 mtd->subpage_sft = 2;
3140 break;
3141 }
3142 }
3143 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3144
3145 /* Initialize state */
3146 chip->state = FL_READY;
3147
3148 /* De-select the device */
3149 chip->select_chip(mtd, -1);
3150
3151 /* Invalidate the pagebuffer reference */
3152 chip->pagebuf = -1;
3153
3154 /* Large page NAND with SOFT_ECC should support subpage reads */
3155 if ((chip->ecc.mode == NAND_ECC_SOFT) && (chip->page_shift > 9))
3156 chip->options |= NAND_SUBPAGE_READ;
3157
3158 /* Fill in remaining MTD driver data */
3159 mtd->type = MTD_NANDFLASH;
3160 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
3161 MTD_CAP_NANDFLASH;
3162 mtd->erase = nand_erase;
3163 mtd->point = NULL;
3164 mtd->unpoint = NULL;
3165 mtd->read = nand_read;
3166 mtd->write = nand_write;
3167 mtd->read_oob = nand_read_oob;
3168 mtd->write_oob = nand_write_oob;
3169 mtd->sync = nand_sync;
3170 mtd->lock = NULL;
3171 mtd->unlock = NULL;
3172 mtd->block_isbad = nand_block_isbad;
3173 mtd->block_markbad = nand_block_markbad;
3174
3175 /* propagate ecc.layout to mtd_info */
3176 mtd->ecclayout = chip->ecc.layout;
3177
3178 /* Check, if we should skip the bad block table scan */
3179 if (chip->options & NAND_SKIP_BBTSCAN)
3180 chip->options |= NAND_BBT_SCANNED;
3181
3182 return 0;
3183 }
3184
3185 /**
3186 * nand_scan - [NAND Interface] Scan for the NAND device
3187 * @mtd: MTD device structure
3188 * @maxchips: Number of chips to scan for
3189 *
3190 * This fills out all the uninitialized function pointers
3191 * with the defaults.
3192 * The flash ID is read and the mtd/chip structures are
3193 * filled with the appropriate values.
3194 * The mtd->owner field must be set to the module of the caller
3195 *
3196 */
3197 int nand_scan(struct mtd_info *mtd, int maxchips)
3198 {
3199 int ret;
3200
3201 ret = nand_scan_ident(mtd, maxchips, NULL);
3202 if (!ret)
3203 ret = nand_scan_tail(mtd);
3204 return ret;
3205 }
3206
3207 /**
3208 * nand_release - [NAND Interface] Free resources held by the NAND device
3209 * @mtd: MTD device structure
3210 */
3211 void nand_release(struct mtd_info *mtd)
3212 {
3213 struct nand_chip *chip = mtd->priv;
3214
3215 if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
3216 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
3217
3218 #ifdef CONFIG_MTD_PARTITIONS
3219 /* Deregister partitions */
3220 del_mtd_partitions(mtd);
3221 #endif
3222
3223 /* Free bad block table memory */
3224 kfree(chip->bbt);
3225 if (!(chip->options & NAND_OWN_BUFFERS))
3226 kfree(chip->buffers);
3227
3228 /* Free bad block descriptor memory */
3229 if (chip->badblock_pattern && chip->badblock_pattern->options
3230 & NAND_BBT_DYNAMICSTRUCT)
3231 kfree(chip->badblock_pattern);
3232 }
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