2 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
3 * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
4 * (C) Copyright 2008 Armadeus Systems nc
5 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
6 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
8 * SPDX-License-Identifier: GPL-2.0+
21 #include <linux/errno.h>
22 #include <linux/compiler.h>
24 #include <asm/arch/clock.h>
25 #include <asm/arch/imx-regs.h>
26 #include <asm/mach-imx/sys_proto.h>
28 DECLARE_GLOBAL_DATA_PTR
;
31 * Timeout the transfer after 5 mS. This is usually a bit more, since
32 * the code in the tightloops this timeout is used in adds some overhead.
34 #define FEC_XFER_TIMEOUT 5000
37 * The standard 32-byte DMA alignment does not work on mx6solox, which requires
38 * 64-byte alignment in the DMA RX FEC buffer.
39 * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also
40 * satisfies the alignment on other SoCs (32-bytes)
42 #define FEC_DMA_RX_MINALIGN 64
45 #error "CONFIG_MII has to be defined!"
48 #ifndef CONFIG_FEC_XCV_TYPE
49 #define CONFIG_FEC_XCV_TYPE MII100
53 * The i.MX28 operates with packets in big endian. We need to swap them before
54 * sending and after receiving.
57 #define CONFIG_FEC_MXC_SWAP_PACKET
60 #define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd))
62 /* Check various alignment issues at compile time */
63 #if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0))
64 #error "ARCH_DMA_MINALIGN must be multiple of 16!"
67 #if ((PKTALIGN < ARCH_DMA_MINALIGN) || \
68 (PKTALIGN % ARCH_DMA_MINALIGN != 0))
69 #error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!"
74 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
75 static void swap_packet(uint32_t *packet
, int length
)
79 for (i
= 0; i
< DIV_ROUND_UP(length
, 4); i
++)
80 packet
[i
] = __swab32(packet
[i
]);
84 /* MII-interface related functions */
85 static int fec_mdio_read(struct ethernet_regs
*eth
, uint8_t phyaddr
,
88 uint32_t reg
; /* convenient holder for the PHY register */
89 uint32_t phy
; /* convenient holder for the PHY */
94 * reading from any PHY's register is done by properly
95 * programming the FEC's MII data register.
97 writel(FEC_IEVENT_MII
, ð
->ievent
);
98 reg
= regaddr
<< FEC_MII_DATA_RA_SHIFT
;
99 phy
= phyaddr
<< FEC_MII_DATA_PA_SHIFT
;
101 writel(FEC_MII_DATA_ST
| FEC_MII_DATA_OP_RD
| FEC_MII_DATA_TA
|
102 phy
| reg
, ð
->mii_data
);
104 /* wait for the related interrupt */
105 start
= get_timer(0);
106 while (!(readl(ð
->ievent
) & FEC_IEVENT_MII
)) {
107 if (get_timer(start
) > (CONFIG_SYS_HZ
/ 1000)) {
108 printf("Read MDIO failed...\n");
113 /* clear mii interrupt bit */
114 writel(FEC_IEVENT_MII
, ð
->ievent
);
116 /* it's now safe to read the PHY's register */
117 val
= (unsigned short)readl(ð
->mii_data
);
118 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__
, phyaddr
,
123 static void fec_mii_setspeed(struct ethernet_regs
*eth
)
126 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
127 * and do not drop the Preamble.
129 * The i.MX28 and i.MX6 types have another field in the MSCR (aka
130 * MII_SPEED) register that defines the MDIO output hold time. Earlier
131 * versions are RAZ there, so just ignore the difference and write the
133 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
134 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
136 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
137 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
138 * holdtime cannot result in a value greater than 3.
140 u32 pclk
= imx_get_fecclk();
141 u32 speed
= DIV_ROUND_UP(pclk
, 5000000);
142 u32 hold
= DIV_ROUND_UP(pclk
, 100000000) - 1;
143 #ifdef FEC_QUIRK_ENET_MAC
146 writel(speed
<< 1 | hold
<< 8, ð
->mii_speed
);
147 debug("%s: mii_speed %08x\n", __func__
, readl(ð
->mii_speed
));
150 static int fec_mdio_write(struct ethernet_regs
*eth
, uint8_t phyaddr
,
151 uint8_t regaddr
, uint16_t data
)
153 uint32_t reg
; /* convenient holder for the PHY register */
154 uint32_t phy
; /* convenient holder for the PHY */
157 reg
= regaddr
<< FEC_MII_DATA_RA_SHIFT
;
158 phy
= phyaddr
<< FEC_MII_DATA_PA_SHIFT
;
160 writel(FEC_MII_DATA_ST
| FEC_MII_DATA_OP_WR
|
161 FEC_MII_DATA_TA
| phy
| reg
| data
, ð
->mii_data
);
163 /* wait for the MII interrupt */
164 start
= get_timer(0);
165 while (!(readl(ð
->ievent
) & FEC_IEVENT_MII
)) {
166 if (get_timer(start
) > (CONFIG_SYS_HZ
/ 1000)) {
167 printf("Write MDIO failed...\n");
172 /* clear MII interrupt bit */
173 writel(FEC_IEVENT_MII
, ð
->ievent
);
174 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__
, phyaddr
,
180 static int fec_phy_read(struct mii_dev
*bus
, int phyaddr
, int dev_addr
,
183 return fec_mdio_read(bus
->priv
, phyaddr
, regaddr
);
186 static int fec_phy_write(struct mii_dev
*bus
, int phyaddr
, int dev_addr
,
187 int regaddr
, u16 data
)
189 return fec_mdio_write(bus
->priv
, phyaddr
, regaddr
, data
);
192 #ifndef CONFIG_PHYLIB
193 static int miiphy_restart_aneg(struct eth_device
*dev
)
196 #if !defined(CONFIG_FEC_MXC_NO_ANEG)
197 struct fec_priv
*fec
= (struct fec_priv
*)dev
->priv
;
198 struct ethernet_regs
*eth
= fec
->bus
->priv
;
201 * Wake up from sleep if necessary
202 * Reset PHY, then delay 300ns
205 fec_mdio_write(eth
, fec
->phy_id
, MII_DCOUNTER
, 0x00FF);
207 fec_mdio_write(eth
, fec
->phy_id
, MII_BMCR
, BMCR_RESET
);
210 /* Set the auto-negotiation advertisement register bits */
211 fec_mdio_write(eth
, fec
->phy_id
, MII_ADVERTISE
,
212 LPA_100FULL
| LPA_100HALF
| LPA_10FULL
|
213 LPA_10HALF
| PHY_ANLPAR_PSB_802_3
);
214 fec_mdio_write(eth
, fec
->phy_id
, MII_BMCR
,
215 BMCR_ANENABLE
| BMCR_ANRESTART
);
217 if (fec
->mii_postcall
)
218 ret
= fec
->mii_postcall(fec
->phy_id
);
224 #ifndef CONFIG_FEC_FIXED_SPEED
225 static int miiphy_wait_aneg(struct eth_device
*dev
)
229 struct fec_priv
*fec
= (struct fec_priv
*)dev
->priv
;
230 struct ethernet_regs
*eth
= fec
->bus
->priv
;
232 /* Wait for AN completion */
233 start
= get_timer(0);
235 if (get_timer(start
) > (CONFIG_SYS_HZ
* 5)) {
236 printf("%s: Autonegotiation timeout\n", dev
->name
);
240 status
= fec_mdio_read(eth
, fec
->phy_id
, MII_BMSR
);
242 printf("%s: Autonegotiation failed. status: %d\n",
246 } while (!(status
& BMSR_LSTATUS
));
250 #endif /* CONFIG_FEC_FIXED_SPEED */
253 static int fec_rx_task_enable(struct fec_priv
*fec
)
255 writel(FEC_R_DES_ACTIVE_RDAR
, &fec
->eth
->r_des_active
);
259 static int fec_rx_task_disable(struct fec_priv
*fec
)
264 static int fec_tx_task_enable(struct fec_priv
*fec
)
266 writel(FEC_X_DES_ACTIVE_TDAR
, &fec
->eth
->x_des_active
);
270 static int fec_tx_task_disable(struct fec_priv
*fec
)
276 * Initialize receive task's buffer descriptors
277 * @param[in] fec all we know about the device yet
278 * @param[in] count receive buffer count to be allocated
279 * @param[in] dsize desired size of each receive buffer
280 * @return 0 on success
282 * Init all RX descriptors to default values.
284 static void fec_rbd_init(struct fec_priv
*fec
, int count
, int dsize
)
291 * Reload the RX descriptors with default values and wipe
294 size
= roundup(dsize
, ARCH_DMA_MINALIGN
);
295 for (i
= 0; i
< count
; i
++) {
296 data
= fec
->rbd_base
[i
].data_pointer
;
297 memset((void *)data
, 0, dsize
);
298 flush_dcache_range(data
, data
+ size
);
300 fec
->rbd_base
[i
].status
= FEC_RBD_EMPTY
;
301 fec
->rbd_base
[i
].data_length
= 0;
304 /* Mark the last RBD to close the ring. */
305 fec
->rbd_base
[i
- 1].status
= FEC_RBD_WRAP
| FEC_RBD_EMPTY
;
308 flush_dcache_range((ulong
)fec
->rbd_base
,
309 (ulong
)fec
->rbd_base
+ size
);
313 * Initialize transmit task's buffer descriptors
314 * @param[in] fec all we know about the device yet
316 * Transmit buffers are created externally. We only have to init the BDs here.\n
317 * Note: There is a race condition in the hardware. When only one BD is in
318 * use it must be marked with the WRAP bit to use it for every transmitt.
319 * This bit in combination with the READY bit results into double transmit
320 * of each data buffer. It seems the state machine checks READY earlier then
321 * resetting it after the first transfer.
322 * Using two BDs solves this issue.
324 static void fec_tbd_init(struct fec_priv
*fec
)
326 ulong addr
= (ulong
)fec
->tbd_base
;
327 unsigned size
= roundup(2 * sizeof(struct fec_bd
),
330 memset(fec
->tbd_base
, 0, size
);
331 fec
->tbd_base
[0].status
= 0;
332 fec
->tbd_base
[1].status
= FEC_TBD_WRAP
;
334 flush_dcache_range(addr
, addr
+ size
);
338 * Mark the given read buffer descriptor as free
339 * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
340 * @param[in] prbd buffer descriptor to mark free again
342 static void fec_rbd_clean(int last
, struct fec_bd
*prbd
)
344 unsigned short flags
= FEC_RBD_EMPTY
;
346 flags
|= FEC_RBD_WRAP
;
347 writew(flags
, &prbd
->status
);
348 writew(0, &prbd
->data_length
);
351 static int fec_get_hwaddr(int dev_id
, unsigned char *mac
)
353 imx_get_mac_from_fuse(dev_id
, mac
);
354 return !is_valid_ethaddr(mac
);
358 static int fecmxc_set_hwaddr(struct udevice
*dev
)
360 static int fec_set_hwaddr(struct eth_device
*dev
)
364 struct fec_priv
*fec
= dev_get_priv(dev
);
365 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
366 uchar
*mac
= pdata
->enetaddr
;
368 uchar
*mac
= dev
->enetaddr
;
369 struct fec_priv
*fec
= (struct fec_priv
*)dev
->priv
;
372 writel(0, &fec
->eth
->iaddr1
);
373 writel(0, &fec
->eth
->iaddr2
);
374 writel(0, &fec
->eth
->gaddr1
);
375 writel(0, &fec
->eth
->gaddr2
);
377 /* Set physical address */
378 writel((mac
[0] << 24) + (mac
[1] << 16) + (mac
[2] << 8) + mac
[3],
380 writel((mac
[4] << 24) + (mac
[5] << 16) + 0x8808, &fec
->eth
->paddr2
);
385 /* Do initial configuration of the FEC registers */
386 static void fec_reg_setup(struct fec_priv
*fec
)
390 /* Set interrupt mask register */
391 writel(0x00000000, &fec
->eth
->imask
);
393 /* Clear FEC-Lite interrupt event register(IEVENT) */
394 writel(0xffffffff, &fec
->eth
->ievent
);
396 /* Set FEC-Lite receive control register(R_CNTRL): */
398 /* Start with frame length = 1518, common for all modes. */
399 rcntrl
= PKTSIZE
<< FEC_RCNTRL_MAX_FL_SHIFT
;
400 if (fec
->xcv_type
!= SEVENWIRE
) /* xMII modes */
401 rcntrl
|= FEC_RCNTRL_FCE
| FEC_RCNTRL_MII_MODE
;
402 if (fec
->xcv_type
== RGMII
)
403 rcntrl
|= FEC_RCNTRL_RGMII
;
404 else if (fec
->xcv_type
== RMII
)
405 rcntrl
|= FEC_RCNTRL_RMII
;
407 writel(rcntrl
, &fec
->eth
->r_cntrl
);
411 * Start the FEC engine
412 * @param[in] dev Our device to handle
415 static int fec_open(struct udevice
*dev
)
417 static int fec_open(struct eth_device
*edev
)
421 struct fec_priv
*fec
= dev_get_priv(dev
);
423 struct fec_priv
*fec
= (struct fec_priv
*)edev
->priv
;
429 debug("fec_open: fec_open(dev)\n");
430 /* full-duplex, heartbeat disabled */
431 writel(1 << 2, &fec
->eth
->x_cntrl
);
434 /* Invalidate all descriptors */
435 for (i
= 0; i
< FEC_RBD_NUM
- 1; i
++)
436 fec_rbd_clean(0, &fec
->rbd_base
[i
]);
437 fec_rbd_clean(1, &fec
->rbd_base
[i
]);
439 /* Flush the descriptors into RAM */
440 size
= roundup(FEC_RBD_NUM
* sizeof(struct fec_bd
),
442 addr
= (ulong
)fec
->rbd_base
;
443 flush_dcache_range(addr
, addr
+ size
);
445 #ifdef FEC_QUIRK_ENET_MAC
446 /* Enable ENET HW endian SWAP */
447 writel(readl(&fec
->eth
->ecntrl
) | FEC_ECNTRL_DBSWAP
,
449 /* Enable ENET store and forward mode */
450 writel(readl(&fec
->eth
->x_wmrk
) | FEC_X_WMRK_STRFWD
,
453 /* Enable FEC-Lite controller */
454 writel(readl(&fec
->eth
->ecntrl
) | FEC_ECNTRL_ETHER_EN
,
457 #if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
460 /* setup the MII gasket for RMII mode */
461 /* disable the gasket */
462 writew(0, &fec
->eth
->miigsk_enr
);
464 /* wait for the gasket to be disabled */
465 while (readw(&fec
->eth
->miigsk_enr
) & MIIGSK_ENR_READY
)
468 /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
469 writew(MIIGSK_CFGR_IF_MODE_RMII
, &fec
->eth
->miigsk_cfgr
);
471 /* re-enable the gasket */
472 writew(MIIGSK_ENR_EN
, &fec
->eth
->miigsk_enr
);
474 /* wait until MII gasket is ready */
476 while ((readw(&fec
->eth
->miigsk_enr
) & MIIGSK_ENR_READY
) == 0) {
477 if (--max_loops
<= 0) {
478 printf("WAIT for MII Gasket ready timed out\n");
486 /* Start up the PHY */
487 int ret
= phy_startup(fec
->phydev
);
490 printf("Could not initialize PHY %s\n",
491 fec
->phydev
->dev
->name
);
494 speed
= fec
->phydev
->speed
;
496 #elif CONFIG_FEC_FIXED_SPEED
497 speed
= CONFIG_FEC_FIXED_SPEED
;
499 miiphy_wait_aneg(edev
);
500 speed
= miiphy_speed(edev
->name
, fec
->phy_id
);
501 miiphy_duplex(edev
->name
, fec
->phy_id
);
504 #ifdef FEC_QUIRK_ENET_MAC
506 u32 ecr
= readl(&fec
->eth
->ecntrl
) & ~FEC_ECNTRL_SPEED
;
507 u32 rcr
= readl(&fec
->eth
->r_cntrl
) & ~FEC_RCNTRL_RMII_10T
;
508 if (speed
== _1000BASET
)
509 ecr
|= FEC_ECNTRL_SPEED
;
510 else if (speed
!= _100BASET
)
511 rcr
|= FEC_RCNTRL_RMII_10T
;
512 writel(ecr
, &fec
->eth
->ecntrl
);
513 writel(rcr
, &fec
->eth
->r_cntrl
);
516 debug("%s:Speed=%i\n", __func__
, speed
);
518 /* Enable SmartDMA receive task */
519 fec_rx_task_enable(fec
);
526 static int fecmxc_init(struct udevice
*dev
)
528 static int fec_init(struct eth_device
*dev
, bd_t
*bd
)
532 struct fec_priv
*fec
= dev_get_priv(dev
);
534 struct fec_priv
*fec
= (struct fec_priv
*)dev
->priv
;
536 u8
*mib_ptr
= (uint8_t *)&fec
->eth
->rmon_t_drop
;
540 /* Initialize MAC address */
542 fecmxc_set_hwaddr(dev
);
547 /* Setup transmit descriptors, there are two in total. */
550 /* Setup receive descriptors. */
551 fec_rbd_init(fec
, FEC_RBD_NUM
, FEC_MAX_PKT_SIZE
);
555 if (fec
->xcv_type
!= SEVENWIRE
)
556 fec_mii_setspeed(fec
->bus
->priv
);
558 /* Set Opcode/Pause Duration Register */
559 writel(0x00010020, &fec
->eth
->op_pause
); /* FIXME 0xffff0020; */
560 writel(0x2, &fec
->eth
->x_wmrk
);
562 /* Set multicast address filter */
563 writel(0x00000000, &fec
->eth
->gaddr1
);
564 writel(0x00000000, &fec
->eth
->gaddr2
);
566 /* Do not access reserved register */
567 if (!is_mx6ul() && !is_mx6ull() && !is_mx8m()) {
569 for (i
= mib_ptr
; i
<= mib_ptr
+ 0xfc; i
+= 4)
572 /* FIFO receive start register */
573 writel(0x520, &fec
->eth
->r_fstart
);
576 /* size and address of each buffer */
577 writel(FEC_MAX_PKT_SIZE
, &fec
->eth
->emrbr
);
579 addr
= (ulong
)fec
->tbd_base
;
580 writel((uint32_t)addr
, &fec
->eth
->etdsr
);
582 addr
= (ulong
)fec
->rbd_base
;
583 writel((uint32_t)addr
, &fec
->eth
->erdsr
);
585 #ifndef CONFIG_PHYLIB
586 if (fec
->xcv_type
!= SEVENWIRE
)
587 miiphy_restart_aneg(dev
);
594 * Halt the FEC engine
595 * @param[in] dev Our device to handle
598 static void fecmxc_halt(struct udevice
*dev
)
600 static void fec_halt(struct eth_device
*dev
)
604 struct fec_priv
*fec
= dev_get_priv(dev
);
606 struct fec_priv
*fec
= (struct fec_priv
*)dev
->priv
;
608 int counter
= 0xffff;
610 /* issue graceful stop command to the FEC transmitter if necessary */
611 writel(FEC_TCNTRL_GTS
| readl(&fec
->eth
->x_cntrl
),
614 debug("eth_halt: wait for stop regs\n");
615 /* wait for graceful stop to register */
616 while ((counter
--) && (!(readl(&fec
->eth
->ievent
) & FEC_IEVENT_GRA
)))
619 /* Disable SmartDMA tasks */
620 fec_tx_task_disable(fec
);
621 fec_rx_task_disable(fec
);
624 * Disable the Ethernet Controller
625 * Note: this will also reset the BD index counter!
627 writel(readl(&fec
->eth
->ecntrl
) & ~FEC_ECNTRL_ETHER_EN
,
631 debug("eth_halt: done\n");
636 * @param[in] dev Our ethernet device to handle
637 * @param[in] packet Pointer to the data to be transmitted
638 * @param[in] length Data count in bytes
639 * @return 0 on success
642 static int fecmxc_send(struct udevice
*dev
, void *packet
, int length
)
644 static int fec_send(struct eth_device
*dev
, void *packet
, int length
)
650 int timeout
= FEC_XFER_TIMEOUT
;
654 * This routine transmits one frame. This routine only accepts
655 * 6-byte Ethernet addresses.
658 struct fec_priv
*fec
= dev_get_priv(dev
);
660 struct fec_priv
*fec
= (struct fec_priv
*)dev
->priv
;
664 * Check for valid length of data.
666 if ((length
> 1500) || (length
<= 0)) {
667 printf("Payload (%d) too large\n", length
);
672 * Setup the transmit buffer. We are always using the first buffer for
673 * transmission, the second will be empty and only used to stop the DMA
674 * engine. We also flush the packet to RAM here to avoid cache trouble.
676 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
677 swap_packet((uint32_t *)packet
, length
);
680 addr
= (ulong
)packet
;
681 end
= roundup(addr
+ length
, ARCH_DMA_MINALIGN
);
682 addr
&= ~(ARCH_DMA_MINALIGN
- 1);
683 flush_dcache_range(addr
, end
);
685 writew(length
, &fec
->tbd_base
[fec
->tbd_index
].data_length
);
686 writel((uint32_t)addr
, &fec
->tbd_base
[fec
->tbd_index
].data_pointer
);
689 * update BD's status now
691 * - is always the last in a chain (means no chain)
692 * - should transmitt the CRC
693 * - might be the last BD in the list, so the address counter should
694 * wrap (-> keep the WRAP flag)
696 status
= readw(&fec
->tbd_base
[fec
->tbd_index
].status
) & FEC_TBD_WRAP
;
697 status
|= FEC_TBD_LAST
| FEC_TBD_TC
| FEC_TBD_READY
;
698 writew(status
, &fec
->tbd_base
[fec
->tbd_index
].status
);
701 * Flush data cache. This code flushes both TX descriptors to RAM.
702 * After this code, the descriptors will be safely in RAM and we
705 size
= roundup(2 * sizeof(struct fec_bd
), ARCH_DMA_MINALIGN
);
706 addr
= (ulong
)fec
->tbd_base
;
707 flush_dcache_range(addr
, addr
+ size
);
710 * Below we read the DMA descriptor's last four bytes back from the
711 * DRAM. This is important in order to make sure that all WRITE
712 * operations on the bus that were triggered by previous cache FLUSH
715 * Otherwise, on MX28, it is possible to observe a corruption of the
716 * DMA descriptors. Please refer to schematic "Figure 1-2" in MX28RM
717 * for the bus structure of MX28. The scenario is as follows:
719 * 1) ARM core triggers a series of WRITEs on the AHB_ARB2 bus going
720 * to DRAM due to flush_dcache_range()
721 * 2) ARM core writes the FEC registers via AHB_ARB2
722 * 3) FEC DMA starts reading/writing from/to DRAM via AHB_ARB3
724 * Note that 2) does sometimes finish before 1) due to reordering of
725 * WRITE accesses on the AHB bus, therefore triggering 3) before the
726 * DMA descriptor is fully written into DRAM. This results in occasional
727 * corruption of the DMA descriptor.
729 readl(addr
+ size
- 4);
731 /* Enable SmartDMA transmit task */
732 fec_tx_task_enable(fec
);
735 * Wait until frame is sent. On each turn of the wait cycle, we must
736 * invalidate data cache to see what's really in RAM. Also, we need
740 if (!(readl(&fec
->eth
->x_des_active
) & FEC_X_DES_ACTIVE_TDAR
))
750 * The TDAR bit is cleared when the descriptors are all out from TX
751 * but on mx6solox we noticed that the READY bit is still not cleared
753 * These are two distinct signals, and in IC simulation, we found that
754 * TDAR always gets cleared prior than the READY bit of last BD becomes
756 * In mx6solox, we use a later version of FEC IP. It looks like that
757 * this intrinsic behaviour of TDAR bit has changed in this newer FEC
760 * Fix this by polling the READY bit of BD after the TDAR polling,
761 * which covers the mx6solox case and does not harm the other SoCs.
763 timeout
= FEC_XFER_TIMEOUT
;
765 invalidate_dcache_range(addr
, addr
+ size
);
766 if (!(readw(&fec
->tbd_base
[fec
->tbd_index
].status
) &
775 debug("fec_send: status 0x%x index %d ret %i\n",
776 readw(&fec
->tbd_base
[fec
->tbd_index
].status
),
777 fec
->tbd_index
, ret
);
778 /* for next transmission use the other buffer */
788 * Pull one frame from the card
789 * @param[in] dev Our ethernet device to handle
790 * @return Length of packet read
793 static int fecmxc_recv(struct udevice
*dev
, int flags
, uchar
**packetp
)
795 static int fec_recv(struct eth_device
*dev
)
799 struct fec_priv
*fec
= dev_get_priv(dev
);
801 struct fec_priv
*fec
= (struct fec_priv
*)dev
->priv
;
803 struct fec_bd
*rbd
= &fec
->rbd_base
[fec
->rbd_index
];
804 unsigned long ievent
;
805 int frame_length
, len
= 0;
807 ulong addr
, size
, end
;
809 ALLOC_CACHE_ALIGN_BUFFER(uchar
, buff
, FEC_MAX_PKT_SIZE
);
811 /* Check if any critical events have happened */
812 ievent
= readl(&fec
->eth
->ievent
);
813 writel(ievent
, &fec
->eth
->ievent
);
814 debug("fec_recv: ievent 0x%lx\n", ievent
);
815 if (ievent
& FEC_IEVENT_BABR
) {
821 fec_init(dev
, fec
->bd
);
823 printf("some error: 0x%08lx\n", ievent
);
826 if (ievent
& FEC_IEVENT_HBERR
) {
827 /* Heartbeat error */
828 writel(0x00000001 | readl(&fec
->eth
->x_cntrl
),
831 if (ievent
& FEC_IEVENT_GRA
) {
832 /* Graceful stop complete */
833 if (readl(&fec
->eth
->x_cntrl
) & 0x00000001) {
839 writel(~0x00000001 & readl(&fec
->eth
->x_cntrl
),
844 fec_init(dev
, fec
->bd
);
850 * Read the buffer status. Before the status can be read, the data cache
851 * must be invalidated, because the data in RAM might have been changed
852 * by DMA. The descriptors are properly aligned to cachelines so there's
853 * no need to worry they'd overlap.
855 * WARNING: By invalidating the descriptor here, we also invalidate
856 * the descriptors surrounding this one. Therefore we can NOT change the
857 * contents of this descriptor nor the surrounding ones. The problem is
858 * that in order to mark the descriptor as processed, we need to change
859 * the descriptor. The solution is to mark the whole cache line when all
860 * descriptors in the cache line are processed.
863 addr
&= ~(ARCH_DMA_MINALIGN
- 1);
864 size
= roundup(sizeof(struct fec_bd
), ARCH_DMA_MINALIGN
);
865 invalidate_dcache_range(addr
, addr
+ size
);
867 bd_status
= readw(&rbd
->status
);
868 debug("fec_recv: status 0x%x\n", bd_status
);
870 if (!(bd_status
& FEC_RBD_EMPTY
)) {
871 if ((bd_status
& FEC_RBD_LAST
) && !(bd_status
& FEC_RBD_ERR
) &&
872 ((readw(&rbd
->data_length
) - 4) > 14)) {
873 /* Get buffer address and size */
874 addr
= readl(&rbd
->data_pointer
);
875 frame_length
= readw(&rbd
->data_length
) - 4;
876 /* Invalidate data cache over the buffer */
877 end
= roundup(addr
+ frame_length
, ARCH_DMA_MINALIGN
);
878 addr
&= ~(ARCH_DMA_MINALIGN
- 1);
879 invalidate_dcache_range(addr
, end
);
881 /* Fill the buffer and pass it to upper layers */
882 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
883 swap_packet((uint32_t *)addr
, frame_length
);
885 memcpy(buff
, (char *)addr
, frame_length
);
886 net_process_received_packet(buff
, frame_length
);
889 if (bd_status
& FEC_RBD_ERR
)
890 debug("error frame: 0x%08lx 0x%08x\n",
895 * Free the current buffer, restart the engine and move forward
896 * to the next buffer. Here we check if the whole cacheline of
897 * descriptors was already processed and if so, we mark it free
900 size
= RXDESC_PER_CACHELINE
- 1;
901 if ((fec
->rbd_index
& size
) == size
) {
902 i
= fec
->rbd_index
- size
;
903 addr
= (ulong
)&fec
->rbd_base
[i
];
904 for (; i
<= fec
->rbd_index
; i
++) {
905 fec_rbd_clean(i
== (FEC_RBD_NUM
- 1),
908 flush_dcache_range(addr
,
909 addr
+ ARCH_DMA_MINALIGN
);
912 fec_rx_task_enable(fec
);
913 fec
->rbd_index
= (fec
->rbd_index
+ 1) % FEC_RBD_NUM
;
915 debug("fec_recv: stop\n");
920 static void fec_set_dev_name(char *dest
, int dev_id
)
922 sprintf(dest
, (dev_id
== -1) ? "FEC" : "FEC%i", dev_id
);
925 static int fec_alloc_descs(struct fec_priv
*fec
)
932 /* Allocate TX descriptors. */
933 size
= roundup(2 * sizeof(struct fec_bd
), ARCH_DMA_MINALIGN
);
934 fec
->tbd_base
= memalign(ARCH_DMA_MINALIGN
, size
);
938 /* Allocate RX descriptors. */
939 size
= roundup(FEC_RBD_NUM
* sizeof(struct fec_bd
), ARCH_DMA_MINALIGN
);
940 fec
->rbd_base
= memalign(ARCH_DMA_MINALIGN
, size
);
944 memset(fec
->rbd_base
, 0, size
);
946 /* Allocate RX buffers. */
948 /* Maximum RX buffer size. */
949 size
= roundup(FEC_MAX_PKT_SIZE
, FEC_DMA_RX_MINALIGN
);
950 for (i
= 0; i
< FEC_RBD_NUM
; i
++) {
951 data
= memalign(FEC_DMA_RX_MINALIGN
, size
);
953 printf("%s: error allocating rxbuf %d\n", __func__
, i
);
957 memset(data
, 0, size
);
960 fec
->rbd_base
[i
].data_pointer
= (uint32_t)addr
;
961 fec
->rbd_base
[i
].status
= FEC_RBD_EMPTY
;
962 fec
->rbd_base
[i
].data_length
= 0;
963 /* Flush the buffer to memory. */
964 flush_dcache_range(addr
, addr
+ size
);
967 /* Mark the last RBD to close the ring. */
968 fec
->rbd_base
[i
- 1].status
= FEC_RBD_WRAP
| FEC_RBD_EMPTY
;
976 for (; i
>= 0; i
--) {
977 addr
= fec
->rbd_base
[i
].data_pointer
;
987 static void fec_free_descs(struct fec_priv
*fec
)
992 for (i
= 0; i
< FEC_RBD_NUM
; i
++) {
993 addr
= fec
->rbd_base
[i
].data_pointer
;
1000 #ifdef CONFIG_DM_ETH
1001 struct mii_dev
*fec_get_miibus(struct udevice
*dev
, int dev_id
)
1003 struct mii_dev
*fec_get_miibus(uint32_t base_addr
, int dev_id
)
1006 #ifdef CONFIG_DM_ETH
1007 struct fec_priv
*priv
= dev_get_priv(dev
);
1008 struct ethernet_regs
*eth
= priv
->eth
;
1010 struct ethernet_regs
*eth
= (struct ethernet_regs
*)(ulong
)base_addr
;
1012 struct mii_dev
*bus
;
1017 printf("mdio_alloc failed\n");
1020 bus
->read
= fec_phy_read
;
1021 bus
->write
= fec_phy_write
;
1023 fec_set_dev_name(bus
->name
, dev_id
);
1025 ret
= mdio_register(bus
);
1027 printf("mdio_register failed\n");
1031 fec_mii_setspeed(eth
);
1035 #ifndef CONFIG_DM_ETH
1036 #ifdef CONFIG_PHYLIB
1037 int fec_probe(bd_t
*bd
, int dev_id
, uint32_t base_addr
,
1038 struct mii_dev
*bus
, struct phy_device
*phydev
)
1040 static int fec_probe(bd_t
*bd
, int dev_id
, uint32_t base_addr
,
1041 struct mii_dev
*bus
, int phy_id
)
1044 struct eth_device
*edev
;
1045 struct fec_priv
*fec
;
1046 unsigned char ethaddr
[6];
1051 /* create and fill edev struct */
1052 edev
= (struct eth_device
*)malloc(sizeof(struct eth_device
));
1054 puts("fec_mxc: not enough malloc memory for eth_device\n");
1059 fec
= (struct fec_priv
*)malloc(sizeof(struct fec_priv
));
1061 puts("fec_mxc: not enough malloc memory for fec_priv\n");
1066 memset(edev
, 0, sizeof(*edev
));
1067 memset(fec
, 0, sizeof(*fec
));
1069 ret
= fec_alloc_descs(fec
);
1074 edev
->init
= fec_init
;
1075 edev
->send
= fec_send
;
1076 edev
->recv
= fec_recv
;
1077 edev
->halt
= fec_halt
;
1078 edev
->write_hwaddr
= fec_set_hwaddr
;
1080 fec
->eth
= (struct ethernet_regs
*)(ulong
)base_addr
;
1083 fec
->xcv_type
= CONFIG_FEC_XCV_TYPE
;
1086 writel(readl(&fec
->eth
->ecntrl
) | FEC_ECNTRL_RESET
, &fec
->eth
->ecntrl
);
1087 start
= get_timer(0);
1088 while (readl(&fec
->eth
->ecntrl
) & FEC_ECNTRL_RESET
) {
1089 if (get_timer(start
) > (CONFIG_SYS_HZ
* 5)) {
1090 printf("FEC MXC: Timeout resetting chip\n");
1097 fec_set_dev_name(edev
->name
, dev_id
);
1098 fec
->dev_id
= (dev_id
== -1) ? 0 : dev_id
;
1100 fec_mii_setspeed(bus
->priv
);
1101 #ifdef CONFIG_PHYLIB
1102 fec
->phydev
= phydev
;
1103 phy_connect_dev(phydev
, edev
);
1107 fec
->phy_id
= phy_id
;
1110 /* only support one eth device, the index number pointed by dev_id */
1111 edev
->index
= fec
->dev_id
;
1113 if (fec_get_hwaddr(fec
->dev_id
, ethaddr
) == 0) {
1114 debug("got MAC%d address from fuse: %pM\n", fec
->dev_id
, ethaddr
);
1115 memcpy(edev
->enetaddr
, ethaddr
, 6);
1117 sprintf(mac
, "eth%daddr", fec
->dev_id
);
1119 strcpy(mac
, "ethaddr");
1121 eth_env_set_enetaddr(mac
, ethaddr
);
1125 fec_free_descs(fec
);
1134 int fecmxc_initialize_multi(bd_t
*bd
, int dev_id
, int phy_id
, uint32_t addr
)
1137 struct mii_dev
*bus
= NULL
;
1138 #ifdef CONFIG_PHYLIB
1139 struct phy_device
*phydev
= NULL
;
1145 * The i.MX28 has two ethernet interfaces, but they are not equal.
1146 * Only the first one can access the MDIO bus.
1148 base_mii
= MXS_ENET0_BASE
;
1152 debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id
, phy_id
, addr
);
1153 bus
= fec_get_miibus(base_mii
, dev_id
);
1156 #ifdef CONFIG_PHYLIB
1157 phydev
= phy_find_by_mask(bus
, 1 << phy_id
, PHY_INTERFACE_MODE_RGMII
);
1159 mdio_unregister(bus
);
1163 ret
= fec_probe(bd
, dev_id
, addr
, bus
, phydev
);
1165 ret
= fec_probe(bd
, dev_id
, addr
, bus
, phy_id
);
1168 #ifdef CONFIG_PHYLIB
1171 mdio_unregister(bus
);
1177 #ifdef CONFIG_FEC_MXC_PHYADDR
1178 int fecmxc_initialize(bd_t
*bd
)
1180 return fecmxc_initialize_multi(bd
, -1, CONFIG_FEC_MXC_PHYADDR
,
1185 #ifndef CONFIG_PHYLIB
1186 int fecmxc_register_mii_postcall(struct eth_device
*dev
, int (*cb
)(int))
1188 struct fec_priv
*fec
= (struct fec_priv
*)dev
->priv
;
1189 fec
->mii_postcall
= cb
;
1196 static int fecmxc_read_rom_hwaddr(struct udevice
*dev
)
1198 struct fec_priv
*priv
= dev_get_priv(dev
);
1199 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
1201 return fec_get_hwaddr(priv
->dev_id
, pdata
->enetaddr
);
1204 static const struct eth_ops fecmxc_ops
= {
1205 .start
= fecmxc_init
,
1206 .send
= fecmxc_send
,
1207 .recv
= fecmxc_recv
,
1208 .stop
= fecmxc_halt
,
1209 .write_hwaddr
= fecmxc_set_hwaddr
,
1210 .read_rom_hwaddr
= fecmxc_read_rom_hwaddr
,
1213 static int fec_phy_init(struct fec_priv
*priv
, struct udevice
*dev
)
1215 struct phy_device
*phydev
;
1216 int mask
= 0xffffffff;
1218 #ifdef CONFIG_PHYLIB
1219 mask
= 1 << CONFIG_FEC_MXC_PHYADDR
;
1222 phydev
= phy_find_by_mask(priv
->bus
, mask
, priv
->interface
);
1226 phy_connect_dev(phydev
, dev
);
1228 priv
->phydev
= phydev
;
1234 static int fecmxc_probe(struct udevice
*dev
)
1236 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
1237 struct fec_priv
*priv
= dev_get_priv(dev
);
1238 struct mii_dev
*bus
= NULL
;
1243 ret
= fec_alloc_descs(priv
);
1248 writel(readl(&priv
->eth
->ecntrl
) | FEC_ECNTRL_RESET
,
1249 &priv
->eth
->ecntrl
);
1250 start
= get_timer(0);
1251 while (readl(&priv
->eth
->ecntrl
) & FEC_ECNTRL_RESET
) {
1252 if (get_timer(start
) > (CONFIG_SYS_HZ
* 5)) {
1253 printf("FEC MXC: Timeout reseting chip\n");
1259 fec_reg_setup(priv
);
1260 priv
->dev_id
= (dev_id
== -1) ? 0 : dev_id
;
1262 bus
= fec_get_miibus(dev
, dev_id
);
1269 priv
->xcv_type
= CONFIG_FEC_XCV_TYPE
;
1270 priv
->interface
= pdata
->phy_interface
;
1271 ret
= fec_phy_init(priv
, dev
);
1280 mdio_unregister(bus
);
1283 fec_free_descs(priv
);
1287 static int fecmxc_remove(struct udevice
*dev
)
1289 struct fec_priv
*priv
= dev_get_priv(dev
);
1292 fec_free_descs(priv
);
1293 mdio_unregister(priv
->bus
);
1294 mdio_free(priv
->bus
);
1299 static int fecmxc_ofdata_to_platdata(struct udevice
*dev
)
1301 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
1302 struct fec_priv
*priv
= dev_get_priv(dev
);
1303 const char *phy_mode
;
1305 pdata
->iobase
= (phys_addr_t
)devfdt_get_addr(dev
);
1306 priv
->eth
= (struct ethernet_regs
*)pdata
->iobase
;
1308 pdata
->phy_interface
= -1;
1309 phy_mode
= fdt_getprop(gd
->fdt_blob
, dev_of_offset(dev
), "phy-mode",
1312 pdata
->phy_interface
= phy_get_interface_by_name(phy_mode
);
1313 if (pdata
->phy_interface
== -1) {
1314 debug("%s: Invalid PHY interface '%s'\n", __func__
, phy_mode
);
1319 * Need to get the reset-gpio and related properties from DT
1320 * and implemet the enet reset code on .probe call
1326 static const struct udevice_id fecmxc_ids
[] = {
1327 { .compatible
= "fsl,imx6q-fec" },
1331 U_BOOT_DRIVER(fecmxc_gem
) = {
1334 .of_match
= fecmxc_ids
,
1335 .ofdata_to_platdata
= fecmxc_ofdata_to_platdata
,
1336 .probe
= fecmxc_probe
,
1337 .remove
= fecmxc_remove
,
1339 .priv_auto_alloc_size
= sizeof(struct fec_priv
),
1340 .platdata_auto_alloc_size
= sizeof(struct eth_pdata
),