drivers/net/fsl-mc/mc.c

   1 /*
   2  * Copyright (C) 2014 Freescale Semiconductor
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #include <common.h>
   7 #include <errno.h>
   8 #include <asm/io.h>
   9 #include <libfdt.h>
  10 #include <fdt_support.h>
  11 #include <fsl-mc/fsl_mc.h>
  12 #include <fsl-mc/fsl_mc_sys.h>
  13 #include <fsl-mc/fsl_mc_private.h>
  14 #include <fsl-mc/fsl_dpmng.h>
  15 #include <fsl-mc/fsl_dprc.h>
  16 #include <fsl-mc/fsl_dpio.h>
  17 #include <fsl-mc/fsl_dpni.h>
  18 #include <fsl-mc/fsl_qbman_portal.h>
  19 #include <fsl-mc/ldpaa_wriop.h>
  20
  21 #define MC_RAM_BASE_ADDR_ALIGNMENT  (512UL * 1024 * 1024)
  22 #define MC_RAM_BASE_ADDR_ALIGNMENT_MASK (~(MC_RAM_BASE_ADDR_ALIGNMENT - 1))
  23 #define MC_RAM_SIZE_ALIGNMENT       (256UL * 1024 * 1024)
  24
  25 #define MC_MEM_SIZE_ENV_VAR     "mcmemsize"
  26 #define MC_BOOT_TIMEOUT_ENV_VAR "mcboottimeout"
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29 static int mc_boot_status = -1;
  30 static int mc_dpl_applied = -1;
  31 #ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
  32 static int mc_aiop_applied = -1;
  33 #endif
  34 struct fsl_mc_io *dflt_mc_io = NULL;
  35 uint16_t dflt_dprc_handle = 0;
  36 struct fsl_dpbp_obj *dflt_dpbp = NULL;
  37 struct fsl_dpio_obj *dflt_dpio = NULL;
  38 uint16_t dflt_dpio_handle = 0;
  39
  40 #ifdef DEBUG
  41 void dump_ram_words(const char *title, void *addr)
  42 {
  43         int i;
  44         uint32_t *words = addr;
  45
  46         printf("Dumping beginning of %s (%p):\n", title, addr);
  47         for (i = 0; i < 16; i++)
  48                 printf("%#x ", words[i]);
  49
  50         printf("\n");
  51 }
  52
  53 void dump_mc_ccsr_regs(struct mc_ccsr_registers __iomem *mc_ccsr_regs)
  54 {
  55         printf("MC CCSR registers:\n"
  56                 "reg_gcr1 %#x\n"
  57                 "reg_gsr %#x\n"
  58                 "reg_sicbalr %#x\n"
  59                 "reg_sicbahr %#x\n"
  60                 "reg_sicapr %#x\n"
  61                 "reg_mcfbalr %#x\n"
  62                 "reg_mcfbahr %#x\n"
  63                 "reg_mcfapr %#x\n"
  64                 "reg_psr %#x\n",
  65                 mc_ccsr_regs->reg_gcr1,
  66                 mc_ccsr_regs->reg_gsr,
  67                 mc_ccsr_regs->reg_sicbalr,
  68                 mc_ccsr_regs->reg_sicbahr,
  69                 mc_ccsr_regs->reg_sicapr,
  70                 mc_ccsr_regs->reg_mcfbalr,
  71                 mc_ccsr_regs->reg_mcfbahr,
  72                 mc_ccsr_regs->reg_mcfapr,
  73                 mc_ccsr_regs->reg_psr);
  74 }
  75 #else
  76
  77 #define dump_ram_words(title, addr)
  78 #define dump_mc_ccsr_regs(mc_ccsr_regs)
  79
  80 #endif /* DEBUG */
  81
  82 #ifndef CONFIG_SYS_LS_MC_FW_IN_DDR
  83 /**
  84  * Copying MC firmware or DPL image to DDR
  85  */
  86 static int mc_copy_image(const char *title,
  87                          u64 image_addr, u32 image_size, u64 mc_ram_addr)
  88 {
  89         debug("%s copied to address %p\n", title, (void *)mc_ram_addr);
  90         memcpy((void *)mc_ram_addr, (void *)image_addr, image_size);
  91         flush_dcache_range(mc_ram_addr, mc_ram_addr + image_size);
  92         return 0;
  93 }
  94
  95 /**
  96  * MC firmware FIT image parser checks if the image is in FIT
  97  * format, verifies integrity of the image and calculates
  98  * raw image address and size values.
  99  * Returns 0 on success and a negative errno on error.
 100  * task fail.
 101  **/
 102 int parse_mc_firmware_fit_image(u64 mc_fw_addr,
 103                                 const void **raw_image_addr,
 104                                 size_t *raw_image_size)
 105 {
 106         int format;
 107         void *fit_hdr;
 108         int node_offset;
 109         const void *data;
 110         size_t size;
 111         const char *uname = "firmware";
 112
 113         fit_hdr = (void *)mc_fw_addr;
 114
 115         /* Check if Image is in FIT format */
 116         format = genimg_get_format(fit_hdr);
 117
 118         if (format != IMAGE_FORMAT_FIT) {
 119                 printf("fsl-mc: ERR: Bad firmware image (not a FIT image)\n");
 120                 return -EINVAL;
 121         }
 122
 123         if (!fit_check_format(fit_hdr)) {
 124                 printf("fsl-mc: ERR: Bad firmware image (bad FIT header)\n");
 125                 return -EINVAL;
 126         }
 127
 128         node_offset = fit_image_get_node(fit_hdr, uname);
 129
 130         if (node_offset < 0) {
 131                 printf("fsl-mc: ERR: Bad firmware image (missing subimage)\n");
 132                 return -ENOENT;
 133         }
 134
 135         /* Verify MC firmware image */
 136         if (!(fit_image_verify(fit_hdr, node_offset))) {
 137                 printf("fsl-mc: ERR: Bad firmware image (bad CRC)\n");
 138                 return -EINVAL;
 139         }
 140
 141         /* Get address and size of raw image */
 142         fit_image_get_data(fit_hdr, node_offset, &data, &size);
 143
 144         *raw_image_addr = data;
 145         *raw_image_size = size;
 146
 147         return 0;
 148 }
 149 #endif
 150
 151 /*
 152  * Calculates the values to be used to specify the address range
 153  * for the MC private DRAM block, in the MCFBALR/MCFBAHR registers.
 154  * It returns the highest 512MB-aligned address within the given
 155  * address range, in '*aligned_base_addr', and the number of 256 MiB
 156  * blocks in it, in 'num_256mb_blocks'.
 157  */
 158 static int calculate_mc_private_ram_params(u64 mc_private_ram_start_addr,
 159                                            size_t mc_ram_size,
 160                                            u64 *aligned_base_addr,
 161                                            u8 *num_256mb_blocks)
 162 {
 163         u64 addr;
 164         u16 num_blocks;
 165
 166         if (mc_ram_size % MC_RAM_SIZE_ALIGNMENT != 0) {
 167                 printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n",
 168                        mc_ram_size);
 169                 return -EINVAL;
 170         }
 171
 172         num_blocks = mc_ram_size / MC_RAM_SIZE_ALIGNMENT;
 173         if (num_blocks < 1 || num_blocks > 0xff) {
 174                 printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n",
 175                        mc_ram_size);
 176                 return -EINVAL;
 177         }
 178
 179         addr = (mc_private_ram_start_addr + mc_ram_size - 1) &
 180                 MC_RAM_BASE_ADDR_ALIGNMENT_MASK;
 181
 182         if (addr < mc_private_ram_start_addr) {
 183                 printf("fsl-mc: ERROR: bad start address %#llx\n",
 184                        mc_private_ram_start_addr);
 185                 return -EFAULT;
 186         }
 187
 188         *aligned_base_addr = addr;
 189         *num_256mb_blocks = num_blocks;
 190         return 0;
 191 }
 192
 193 static int mc_fixup_dpc(u64 dpc_addr)
 194 {
 195         void *blob = (void *)dpc_addr;
 196         int nodeoffset;
 197
 198         /* delete any existing ICID pools */
 199         nodeoffset = fdt_path_offset(blob, "/resources/icid_pools");
 200         if (fdt_del_node(blob, nodeoffset) < 0)
 201                 printf("\nfsl-mc: WARNING: could not delete ICID pool\n");
 202
 203         /* add a new pool */
 204         nodeoffset = fdt_path_offset(blob, "/resources");
 205         if (nodeoffset < 0) {
 206                 printf("\nfsl-mc: ERROR: DPC is missing /resources\n");
 207                 return -EINVAL;
 208         }
 209         nodeoffset = fdt_add_subnode(blob, nodeoffset, "icid_pools");
 210         nodeoffset = fdt_add_subnode(blob, nodeoffset, "icid_pool@0");
 211         do_fixup_by_path_u32(blob, "/resources/icid_pools/icid_pool@0",
 212                              "base_icid", FSL_DPAA2_STREAM_ID_START, 1);
 213         do_fixup_by_path_u32(blob, "/resources/icid_pools/icid_pool@0",
 214                              "num",
 215                              FSL_DPAA2_STREAM_ID_END -
 216                              FSL_DPAA2_STREAM_ID_START + 1, 1);
 217
 218         flush_dcache_range(dpc_addr, dpc_addr + fdt_totalsize(blob));
 219
 220         return 0;
 221 }
 222
 223 static int load_mc_dpc(u64 mc_ram_addr, size_t mc_ram_size, u64 mc_dpc_addr)
 224 {
 225         u64 mc_dpc_offset;
 226 #ifndef CONFIG_SYS_LS_MC_DPC_IN_DDR
 227         int error;
 228         void *dpc_fdt_hdr;
 229         int dpc_size;
 230 #endif
 231
 232 #ifdef CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET
 233         BUILD_BUG_ON((CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET & 0x3) != 0 ||
 234                      CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET > 0xffffffff);
 235
 236         mc_dpc_offset = CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET;
 237 #else
 238 #error "CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET not defined"
 239 #endif
 240
 241         /*
 242          * Load the MC DPC blob in the MC private DRAM block:
 243          */
 244 #ifdef CONFIG_SYS_LS_MC_DPC_IN_DDR
 245         printf("MC DPC is preloaded to %#llx\n", mc_ram_addr + mc_dpc_offset);
 246 #else
 247         /*
 248          * Get address and size of the DPC blob stored in flash:
 249          */
 250         dpc_fdt_hdr = (void *)mc_dpc_addr;
 251
 252         error = fdt_check_header(dpc_fdt_hdr);
 253         if (error != 0) {
 254                 /*
 255                  * Don't return with error here, since the MC firmware can
 256                  * still boot without a DPC
 257                  */
 258                 printf("\nfsl-mc: WARNING: No DPC image found");
 259                 return 0;
 260         }
 261
 262         dpc_size = fdt_totalsize(dpc_fdt_hdr);
 263         if (dpc_size > CONFIG_SYS_LS_MC_DPC_MAX_LENGTH) {
 264                 printf("\nfsl-mc: ERROR: Bad DPC image (too large: %d)\n",
 265                        dpc_size);
 266                 return -EINVAL;
 267         }
 268
 269         mc_copy_image("MC DPC blob",
 270                       (u64)dpc_fdt_hdr, dpc_size, mc_ram_addr + mc_dpc_offset);
 271 #endif /* not defined CONFIG_SYS_LS_MC_DPC_IN_DDR */
 272
 273         if (mc_fixup_dpc(mc_ram_addr + mc_dpc_offset))
 274                 return -EINVAL;
 275
 276         dump_ram_words("DPC", (void *)(mc_ram_addr + mc_dpc_offset));
 277         return 0;
 278 }
 279
 280 static int load_mc_dpl(u64 mc_ram_addr, size_t mc_ram_size, u64 mc_dpl_addr)
 281 {
 282         u64 mc_dpl_offset;
 283 #ifndef CONFIG_SYS_LS_MC_DPL_IN_DDR
 284         int error;
 285         void *dpl_fdt_hdr;
 286         int dpl_size;
 287 #endif
 288
 289 #ifdef CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET
 290         BUILD_BUG_ON((CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET & 0x3) != 0 ||
 291                      CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET > 0xffffffff);
 292
 293         mc_dpl_offset = CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET;
 294 #else
 295 #error "CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET not defined"
 296 #endif
 297
 298         /*
 299          * Load the MC DPL blob in the MC private DRAM block:
 300          */
 301 #ifdef CONFIG_SYS_LS_MC_DPL_IN_DDR
 302         printf("MC DPL is preloaded to %#llx\n", mc_ram_addr + mc_dpl_offset);
 303 #else
 304         /*
 305          * Get address and size of the DPL blob stored in flash:
 306          */
 307         dpl_fdt_hdr = (void *)mc_dpl_addr;
 308
 309         error = fdt_check_header(dpl_fdt_hdr);
 310         if (error != 0) {
 311                 printf("\nfsl-mc: ERROR: Bad DPL image (bad header)\n");
 312                 return error;
 313         }
 314
 315         dpl_size = fdt_totalsize(dpl_fdt_hdr);
 316         if (dpl_size > CONFIG_SYS_LS_MC_DPL_MAX_LENGTH) {
 317                 printf("\nfsl-mc: ERROR: Bad DPL image (too large: %d)\n",
 318                        dpl_size);
 319                 return -EINVAL;
 320         }
 321
 322         mc_copy_image("MC DPL blob",
 323                       (u64)dpl_fdt_hdr, dpl_size, mc_ram_addr + mc_dpl_offset);
 324 #endif /* not defined CONFIG_SYS_LS_MC_DPL_IN_DDR */
 325
 326         dump_ram_words("DPL", (void *)(mc_ram_addr + mc_dpl_offset));
 327         return 0;
 328 }
 329
 330 /**
 331  * Return the MC boot timeout value in milliseconds
 332  */
 333 static unsigned long get_mc_boot_timeout_ms(void)
 334 {
 335         unsigned long timeout_ms = CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS;
 336
 337         char *timeout_ms_env_var = getenv(MC_BOOT_TIMEOUT_ENV_VAR);
 338
 339         if (timeout_ms_env_var) {
 340                 timeout_ms = simple_strtoul(timeout_ms_env_var, NULL, 10);
 341                 if (timeout_ms == 0) {
 342                         printf("fsl-mc: WARNING: Invalid value for \'"
 343                                MC_BOOT_TIMEOUT_ENV_VAR
 344                                "\' environment variable: %lu\n",
 345                                timeout_ms);
 346
 347                         timeout_ms = CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS;
 348                 }
 349         }
 350
 351         return timeout_ms;
 352 }
 353
 354 #ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
 355 static int load_mc_aiop_img(u64 aiop_fw_addr)
 356 {
 357         u64 mc_ram_addr = mc_get_dram_addr();
 358 #ifndef CONFIG_SYS_LS_MC_DPC_IN_DDR
 359         void *aiop_img;
 360 #endif
 361
 362         /*
 363          * Load the MC AIOP image in the MC private DRAM block:
 364          */
 365
 366 #ifdef CONFIG_SYS_LS_MC_DPC_IN_DDR
 367         printf("MC AIOP is preloaded to %#llx\n", mc_ram_addr +
 368                CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET);
 369 #else
 370         aiop_img = (void *)aiop_fw_addr;
 371         mc_copy_image("MC AIOP image",
 372                       (u64)aiop_img, CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH,
 373                       mc_ram_addr + CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET);
 374 #endif
 375         mc_aiop_applied = 0;
 376
 377         return 0;
 378 }
 379 #endif
 380
 381 static int wait_for_mc(bool booting_mc, u32 *final_reg_gsr)
 382 {
 383         u32 reg_gsr;
 384         u32 mc_fw_boot_status;
 385         unsigned long timeout_ms = get_mc_boot_timeout_ms();
 386         struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR;
 387
 388         dmb();
 389         assert(timeout_ms > 0);
 390         for (;;) {
 391                 udelay(1000);   /* throttle polling */
 392                 reg_gsr = in_le32(&mc_ccsr_regs->reg_gsr);
 393                 mc_fw_boot_status = (reg_gsr & GSR_FS_MASK);
 394                 if (mc_fw_boot_status & 0x1)
 395                         break;
 396
 397                 timeout_ms--;
 398                 if (timeout_ms == 0)
 399                         break;
 400         }
 401
 402         if (timeout_ms == 0) {
 403                 printf("ERROR: timeout\n");
 404
 405                 /* TODO: Get an error status from an MC CCSR register */
 406                 return -ETIMEDOUT;
 407         }
 408
 409         if (mc_fw_boot_status != 0x1) {
 410                 /*
 411                  * TODO: Identify critical errors from the GSR register's FS
 412                  * field and for those errors, set error to -ENODEV or other
 413                  * appropriate errno, so that the status property is set to
 414                  * failure in the fsl,dprc device tree node.
 415                  */
 416                 printf("WARNING: Firmware returned an error (GSR: %#x)\n",
 417                        reg_gsr);
 418         } else {
 419                 printf("SUCCESS\n");
 420         }
 421
 422
 423         *final_reg_gsr = reg_gsr;
 424         return 0;
 425 }
 426
 427 int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr)
 428 {
 429         int error = 0;
 430         int portal_id = 0;
 431         struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR;
 432         u64 mc_ram_addr = mc_get_dram_addr();
 433         u32 reg_gsr;
 434         u32 reg_mcfbalr;
 435 #ifndef CONFIG_SYS_LS_MC_FW_IN_DDR
 436         const void *raw_image_addr;
 437         size_t raw_image_size = 0;
 438 #endif
 439         struct mc_version mc_ver_info;
 440         u64 mc_ram_aligned_base_addr;
 441         u8 mc_ram_num_256mb_blocks;
 442         size_t mc_ram_size = mc_get_dram_block_size();
 443
 444
 445         error = calculate_mc_private_ram_params(mc_ram_addr,
 446                                                 mc_ram_size,
 447                                                 &mc_ram_aligned_base_addr,
 448                                                 &mc_ram_num_256mb_blocks);
 449         if (error != 0)
 450                 goto out;
 451
 452         /*
 453          * Management Complex cores should be held at reset out of POR.
 454          * U-boot should be the first software to touch MC. To be safe,
 455          * we reset all cores again by setting GCR1 to 0. It doesn't do
 456          * anything if they are held at reset. After we setup the firmware
 457          * we kick off MC by deasserting the reset bit for core 0, and
 458          * deasserting the reset bits for Command Portal Managers.
 459          * The stop bits are not touched here. They are used to stop the
 460          * cores when they are active. Setting stop bits doesn't stop the
 461          * cores from fetching instructions when they are released from
 462          * reset.
 463          */
 464         out_le32(&mc_ccsr_regs->reg_gcr1, 0);
 465         dmb();
 466
 467 #ifdef CONFIG_SYS_LS_MC_FW_IN_DDR
 468         printf("MC firmware is preloaded to %#llx\n", mc_ram_addr);
 469 #else
 470         error = parse_mc_firmware_fit_image(mc_fw_addr, &raw_image_addr,
 471                                             &raw_image_size);
 472         if (error != 0)
 473                 goto out;
 474         /*
 475          * Load the MC FW at the beginning of the MC private DRAM block:
 476          */
 477         mc_copy_image("MC Firmware",
 478                       (u64)raw_image_addr, raw_image_size, mc_ram_addr);
 479 #endif
 480         dump_ram_words("firmware", (void *)mc_ram_addr);
 481
 482         error = load_mc_dpc(mc_ram_addr, mc_ram_size, mc_dpc_addr);
 483         if (error != 0)
 484                 goto out;
 485
 486         debug("mc_ccsr_regs %p\n", mc_ccsr_regs);
 487         dump_mc_ccsr_regs(mc_ccsr_regs);
 488
 489         /*
 490          * Tell MC what is the address range of the DRAM block assigned to it:
 491          */
 492         reg_mcfbalr = (u32)mc_ram_aligned_base_addr |
 493                       (mc_ram_num_256mb_blocks - 1);
 494         out_le32(&mc_ccsr_regs->reg_mcfbalr, reg_mcfbalr);
 495         out_le32(&mc_ccsr_regs->reg_mcfbahr,
 496                  (u32)(mc_ram_aligned_base_addr >> 32));
 497         out_le32(&mc_ccsr_regs->reg_mcfapr, FSL_BYPASS_AMQ);
 498
 499         /*
 500          * Tell the MC that we want delayed DPL deployment.
 501          */
 502         out_le32(&mc_ccsr_regs->reg_gsr, 0xDD00);
 503
 504         printf("\nfsl-mc: Booting Management Complex ... ");
 505
 506         /*
 507          * Deassert reset and release MC core 0 to run
 508          */
 509         out_le32(&mc_ccsr_regs->reg_gcr1, GCR1_P1_DE_RST | GCR1_M_ALL_DE_RST);
 510         error = wait_for_mc(true, &reg_gsr);
 511         if (error != 0)
 512                 goto out;
 513
 514         /*
 515          * TODO: need to obtain the portal_id for the root container from the
 516          * DPL
 517          */
 518         portal_id = 0;
 519
 520         /*
 521          * Initialize the global default MC portal
 522          * And check that the MC firmware is responding portal commands:
 523          */
 524         dflt_mc_io = (struct fsl_mc_io *)malloc(sizeof(struct fsl_mc_io));
 525         if (!dflt_mc_io) {
 526                 printf(" No memory: malloc() failed\n");
 527                 return -ENOMEM;
 528         }
 529
 530         dflt_mc_io->mmio_regs = SOC_MC_PORTAL_ADDR(portal_id);
 531         debug("Checking access to MC portal of root DPRC container (portal_id %d, portal physical addr %p)\n",
 532               portal_id, dflt_mc_io->mmio_regs);
 533
 534         error = mc_get_version(dflt_mc_io, MC_CMD_NO_FLAGS, &mc_ver_info);
 535         if (error != 0) {
 536                 printf("fsl-mc: ERROR: Firmware version check failed (error: %d)\n",
 537                        error);
 538                 goto out;
 539         }
 540
 541         if (MC_VER_MAJOR != mc_ver_info.major) {
 542                 printf("fsl-mc: ERROR: Firmware major version mismatch (found: %d, expected: %d)\n",
 543                        mc_ver_info.major, MC_VER_MAJOR);
 544                 printf("fsl-mc: Update the Management Complex firmware\n");
 545
 546                 error = -ENODEV;
 547                 goto out;
 548         }
 549
 550         if (MC_VER_MINOR != mc_ver_info.minor)
 551                 printf("fsl-mc: WARNING: Firmware minor version mismatch (found: %d, expected: %d)\n",
 552                        mc_ver_info.minor, MC_VER_MINOR);
 553
 554         printf("fsl-mc: Management Complex booted (version: %d.%d.%d, boot status: %#x)\n",
 555                mc_ver_info.major, mc_ver_info.minor, mc_ver_info.revision,
 556                reg_gsr & GSR_FS_MASK);
 557
 558 out:
 559         if (error != 0)
 560                 mc_boot_status = error;
 561         else
 562                 mc_boot_status = 0;
 563
 564         return error;
 565 }
 566
 567 int mc_apply_dpl(u64 mc_dpl_addr)
 568 {
 569         struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR;
 570         int error = 0;
 571         u32 reg_gsr;
 572         u64 mc_ram_addr = mc_get_dram_addr();
 573         size_t mc_ram_size = mc_get_dram_block_size();
 574
 575         error = load_mc_dpl(mc_ram_addr, mc_ram_size, mc_dpl_addr);
 576         if (error != 0)
 577                 return error;
 578
 579         /*
 580          * Tell the MC to deploy the DPL:
 581          */
 582         out_le32(&mc_ccsr_regs->reg_gsr, 0x0);
 583         printf("fsl-mc: Deploying data path layout ... ");
 584         error = wait_for_mc(false, &reg_gsr);
 585
 586         if (!error)
 587                 mc_dpl_applied = 0;
 588
 589         return error;
 590 }
 591
 592 int get_mc_boot_status(void)
 593 {
 594         return mc_boot_status;
 595 }
 596
 597 #ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
 598 int get_aiop_apply_status(void)
 599 {
 600         return mc_aiop_applied;
 601 }
 602 #endif
 603
 604 int get_dpl_apply_status(void)
 605 {
 606         return mc_dpl_applied;
 607 }
 608
 609 /**
 610  * Return the MC address of private DRAM block.
 611  */
 612 u64 mc_get_dram_addr(void)
 613 {
 614         u64 mc_ram_addr;
 615
 616         /*
 617          * The MC private DRAM block was already carved at the end of DRAM
 618          * by board_init_f() using CONFIG_SYS_MEM_TOP_HIDE:
 619          */
 620         if (gd->bd->bi_dram[1].start) {
 621                 mc_ram_addr =
 622                         gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size;
 623         } else {
 624                 mc_ram_addr =
 625                         gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;
 626         }
 627
 628         return mc_ram_addr;
 629 }
 630
 631 /**
 632  * Return the actual size of the MC private DRAM block.
 633  */
 634 unsigned long mc_get_dram_block_size(void)
 635 {
 636         unsigned long dram_block_size = CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE;
 637
 638         char *dram_block_size_env_var = getenv(MC_MEM_SIZE_ENV_VAR);
 639
 640         if (dram_block_size_env_var) {
 641                 dram_block_size = simple_strtoul(dram_block_size_env_var, NULL,
 642                                                  10);
 643
 644                 if (dram_block_size < CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE) {
 645                         printf("fsl-mc: WARNING: Invalid value for \'"
 646                                MC_MEM_SIZE_ENV_VAR
 647                                "\' environment variable: %lu\n",
 648                                dram_block_size);
 649
 650                         dram_block_size = CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE;
 651                 }
 652         }
 653
 654         return dram_block_size;
 655 }
 656
 657 int dpio_init(struct dprc_obj_desc obj_desc)
 658 {
 659         struct qbman_swp_desc p_des;
 660         struct dpio_attr attr;
 661         int err = 0;
 662
 663         dflt_dpio = (struct fsl_dpio_obj *)malloc(sizeof(struct fsl_dpio_obj));
 664         if (!dflt_dpio) {
 665                 printf(" No memory: malloc() failed\n");
 666                 return -ENOMEM;
 667         }
 668
 669         dflt_dpio->dpio_id = obj_desc.id;
 670
 671         err = dpio_open(dflt_mc_io, MC_CMD_NO_FLAGS, obj_desc.id,
 672                         &dflt_dpio_handle);
 673         if (err) {
 674                 printf("dpio_open() failed\n");
 675                 goto err_open;
 676         }
 677
 678         err = dpio_get_attributes(dflt_mc_io, MC_CMD_NO_FLAGS,
 679                                   dflt_dpio_handle, &attr);
 680         if (err) {
 681                 printf("dpio_get_attributes() failed %d\n", err);
 682                 goto err_get_attr;
 683         }
 684
 685         err = dpio_enable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio_handle);
 686         if (err) {
 687                 printf("dpio_enable() failed %d\n", err);
 688                 goto err_get_enable;
 689         }
 690         debug("ce_offset=0x%llx, ci_offset=0x%llx, portalid=%d, prios=%d\n",
 691               attr.qbman_portal_ce_offset,
 692               attr.qbman_portal_ci_offset,
 693               attr.qbman_portal_id,
 694               attr.num_priorities);
 695
 696         p_des.cena_bar = (void *)(SOC_QBMAN_PORTALS_BASE_ADDR
 697                                         + attr.qbman_portal_ce_offset);
 698         p_des.cinh_bar = (void *)(SOC_QBMAN_PORTALS_BASE_ADDR
 699                                         + attr.qbman_portal_ci_offset);
 700
 701         dflt_dpio->sw_portal = qbman_swp_init(&p_des);
 702         if (dflt_dpio->sw_portal == NULL) {
 703                 printf("qbman_swp_init() failed\n");
 704                 goto err_get_swp_init;
 705         }
 706         return 0;
 707
 708 err_get_swp_init:
 709 err_get_enable:
 710         dpio_disable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio_handle);
 711 err_get_attr:
 712         dpio_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio_handle);
 713 err_open:
 714         free(dflt_dpio);
 715         return err;
 716 }
 717
 718 int dpbp_init(struct dprc_obj_desc obj_desc)
 719 {
 720         dflt_dpbp = (struct fsl_dpbp_obj *)malloc(sizeof(struct fsl_dpbp_obj));
 721         if (!dflt_dpbp) {
 722                 printf(" No memory: malloc() failed\n");
 723                 return -ENOMEM;
 724         }
 725         dflt_dpbp->dpbp_attr.id = obj_desc.id;
 726
 727         return 0;
 728 }
 729
 730 int fsl_mc_ldpaa_init(bd_t *bis)
 731 {
 732
 733         return 0;
 734 }
 735
 736 void fsl_mc_ldpaa_exit(bd_t *bis)
 737 {
 738         return;
 739 }
 740
 741 static int do_fsl_mc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 742 {
 743         int err = 0;
 744         if (argc < 3)
 745                 goto usage;
 746
 747         switch (argv[1][0]) {
 748         case 's': {
 749                         char sub_cmd;
 750                         u64 mc_fw_addr, mc_dpc_addr, aiop_fw_addr;
 751
 752                         sub_cmd = argv[2][0];
 753                         switch (sub_cmd) {
 754                         case 'm':
 755                                 if (argc < 5)
 756                                         goto usage;
 757
 758                                 if (get_mc_boot_status() == 0) {
 759                                         printf("fsl-mc: MC is already booted");
 760                                         printf("\n");
 761                                         return err;
 762                                 }
 763                                 mc_fw_addr = simple_strtoull(argv[3], NULL, 16);
 764                                 mc_dpc_addr = simple_strtoull(argv[4], NULL,
 765                                                               16);
 766                                 err = mc_init(mc_fw_addr, mc_dpc_addr);
 767                                 break;
 768
 769 #ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
 770                         case 'a':
 771                                 if (argc < 4)
 772                                         goto usage;
 773                                 if (get_aiop_apply_status() == 0) {
 774                                         printf("fsl-mc: AIOP FW is already");
 775                                         printf(" applied\n");
 776                                         return err;
 777                                 }
 778
 779                                 aiop_fw_addr = simple_strtoull(argv[3], NULL,
 780                                                                16);
 781
 782                                 err = load_mc_aiop_img(aiop_fw_addr);
 783                                 if (!err)
 784                                         printf("fsl-mc: AIOP FW applied\n");
 785                                 break;
 786 #endif
 787                         default:
 788                                 printf("Invalid option: %s\n", argv[2]);
 789                                 goto usage;
 790
 791                                 break;
 792                         }
 793                 }
 794                 break;
 795
 796         case 'a': {
 797                         u64 mc_dpl_addr;
 798
 799                         if (argc < 4)
 800                                 goto usage;
 801
 802                         if (get_dpl_apply_status() == 0) {
 803                                 printf("fsl-mc: DPL already applied\n");
 804                                 return err;
 805                         }
 806
 807                         mc_dpl_addr = simple_strtoull(argv[3], NULL,
 808                                                               16);
 809                         if (get_mc_boot_status() != 0) {
 810                                 printf("fsl-mc: Deploying data path layout ..");
 811                                 printf("ERROR (MC is not booted)\n");
 812                                 return -ENODEV;
 813                         }
 814                         err = mc_apply_dpl(mc_dpl_addr);
 815                         break;
 816                 }
 817         default:
 818                 printf("Invalid option: %s\n", argv[1]);
 819                 goto usage;
 820                 break;
 821         }
 822         return err;
 823  usage:
 824         return CMD_RET_USAGE;
 825 }
 826
 827 U_BOOT_CMD(
 828         fsl_mc,  CONFIG_SYS_MAXARGS,  1,   do_fsl_mc,
 829         "DPAA2 command to manage Management Complex (MC)",
 830         "start mc [FW_addr] [DPC_addr] - Start Management Complex\n"
 831         "fsl_mc apply DPL [DPL_addr] - Apply DPL file\n"
 832         "fsl_mc start aiop [FW_addr] - Start AIOP\n"
 833 );