]> git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/usb/host/ehci-hcd.c
projects / people / ms / u-boot.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
usb: hub: Change USB hub descriptor to match USB 3.0 hubs
[people/ms/u-boot.git] / drivers / usb / host / ehci-hcd.c
1 /*-
2 * Copyright (c) 2007-2008, Juniper Networks, Inc.
3 * Copyright (c) 2008, Excito Elektronik i Skåne AB
4 * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
5 *
6 * All rights reserved.
7 *
8 * SPDX-License-Identifier: GPL-2.0
9 */
10 #include <common.h>
11 #include <dm.h>
12 #include <errno.h>
13 #include <asm/byteorder.h>
14 #include <asm/unaligned.h>
15 #include <usb.h>
16 #include <asm/io.h>
17 #include <malloc.h>
18 #include <memalign.h>
19 #include <watchdog.h>
20 #include <linux/compiler.h>
21
22 #include "ehci.h"
23
24 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
25 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
26 #endif
27
28 /*
29 * EHCI spec page 20 says that the HC may take up to 16 uFrames (= 4ms) to halt.
30 * Let's time out after 8 to have a little safety margin on top of that.
31 */
32 #define HCHALT_TIMEOUT (8 * 1000)
33
34 #ifndef CONFIG_DM_USB
35 static struct ehci_ctrl ehcic[CONFIG_USB_MAX_CONTROLLER_COUNT];
36 #endif
37
38 #define ALIGN_END_ADDR(type, ptr, size) \
39 ((unsigned long)(ptr) + roundup((size) * sizeof(type), USB_DMA_MINALIGN))
40
41 static struct descriptor {
42 struct usb_hub_descriptor hub;
43 struct usb_device_descriptor device;
44 struct usb_linux_config_descriptor config;
45 struct usb_linux_interface_descriptor interface;
46 struct usb_endpoint_descriptor endpoint;
47 } __attribute__ ((packed)) descriptor = {
48 {
49 0x8, /* bDescLength */
50 0x29, /* bDescriptorType: hub descriptor */
51 2, /* bNrPorts -- runtime modified */
52 0, /* wHubCharacteristics */
53 10, /* bPwrOn2PwrGood */
54 0, /* bHubCntrCurrent */
55 { /* Device removable */
56 } /* at most 7 ports! XXX */
57 },
58 {
59 0x12, /* bLength */
60 1, /* bDescriptorType: UDESC_DEVICE */
61 cpu_to_le16(0x0200), /* bcdUSB: v2.0 */
62 9, /* bDeviceClass: UDCLASS_HUB */
63 0, /* bDeviceSubClass: UDSUBCLASS_HUB */
64 1, /* bDeviceProtocol: UDPROTO_HSHUBSTT */
65 64, /* bMaxPacketSize: 64 bytes */
66 0x0000, /* idVendor */
67 0x0000, /* idProduct */
68 cpu_to_le16(0x0100), /* bcdDevice */
69 1, /* iManufacturer */
70 2, /* iProduct */
71 0, /* iSerialNumber */
72 1 /* bNumConfigurations: 1 */
73 },
74 {
75 0x9,
76 2, /* bDescriptorType: UDESC_CONFIG */
77 cpu_to_le16(0x19),
78 1, /* bNumInterface */
79 1, /* bConfigurationValue */
80 0, /* iConfiguration */
81 0x40, /* bmAttributes: UC_SELF_POWER */
82 0 /* bMaxPower */
83 },
84 {
85 0x9, /* bLength */
86 4, /* bDescriptorType: UDESC_INTERFACE */
87 0, /* bInterfaceNumber */
88 0, /* bAlternateSetting */
89 1, /* bNumEndpoints */
90 9, /* bInterfaceClass: UICLASS_HUB */
91 0, /* bInterfaceSubClass: UISUBCLASS_HUB */
92 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */
93 0 /* iInterface */
94 },
95 {
96 0x7, /* bLength */
97 5, /* bDescriptorType: UDESC_ENDPOINT */
98 0x81, /* bEndpointAddress:
99 * UE_DIR_IN | EHCI_INTR_ENDPT
100 */
101 3, /* bmAttributes: UE_INTERRUPT */
102 8, /* wMaxPacketSize */
103 255 /* bInterval */
104 },
105 };
106
107 #if defined(CONFIG_EHCI_IS_TDI)
108 #define ehci_is_TDI() (1)
109 #else
110 #define ehci_is_TDI() (0)
111 #endif
112
113 static struct ehci_ctrl *ehci_get_ctrl(struct usb_device *udev)
114 {
115 #ifdef CONFIG_DM_USB
116 return dev_get_priv(usb_get_bus(udev->dev));
117 #else
118 return udev->controller;
119 #endif
120 }
121
122 static int ehci_get_port_speed(struct ehci_ctrl *ctrl, uint32_t reg)
123 {
124 return PORTSC_PSPD(reg);
125 }
126
127 static void ehci_set_usbmode(struct ehci_ctrl *ctrl)
128 {
129 uint32_t tmp;
130 uint32_t *reg_ptr;
131
132 reg_ptr = (uint32_t *)((u8 *)&ctrl->hcor->or_usbcmd + USBMODE);
133 tmp = ehci_readl(reg_ptr);
134 tmp |= USBMODE_CM_HC;
135 #if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN)
136 tmp |= USBMODE_BE;
137 #else
138 tmp &= ~USBMODE_BE;
139 #endif
140 ehci_writel(reg_ptr, tmp);
141 }
142
143 static void ehci_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg,
144 uint32_t *reg)
145 {
146 mdelay(50);
147 }
148
149 static uint32_t *ehci_get_portsc_register(struct ehci_ctrl *ctrl, int port)
150 {
151 if (port < 0 || port >= CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) {
152 /* Printing the message would cause a scan failure! */
153 debug("The request port(%u) is not configured\n", port);
154 return NULL;
155 }
156
157 return (uint32_t *)&ctrl->hcor->or_portsc[port];
158 }
159
160 static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec)
161 {
162 uint32_t result;
163 do {
164 result = ehci_readl(ptr);
165 udelay(5);
166 if (result == ~(uint32_t)0)
167 return -1;
168 result &= mask;
169 if (result == done)
170 return 0;
171 usec--;
172 } while (usec > 0);
173 return -1;
174 }
175
176 static int ehci_reset(struct ehci_ctrl *ctrl)
177 {
178 uint32_t cmd;
179 int ret = 0;
180
181 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
182 cmd = (cmd & ~CMD_RUN) | CMD_RESET;
183 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
184 ret = handshake((uint32_t *)&ctrl->hcor->or_usbcmd,
185 CMD_RESET, 0, 250 * 1000);
186 if (ret < 0) {
187 printf("EHCI fail to reset\n");
188 goto out;
189 }
190
191 if (ehci_is_TDI())
192 ctrl->ops.set_usb_mode(ctrl);
193
194 #ifdef CONFIG_USB_EHCI_TXFIFO_THRESH
195 cmd = ehci_readl(&ctrl->hcor->or_txfilltuning);
196 cmd &= ~TXFIFO_THRESH_MASK;
197 cmd |= TXFIFO_THRESH(CONFIG_USB_EHCI_TXFIFO_THRESH);
198 ehci_writel(&ctrl->hcor->or_txfilltuning, cmd);
199 #endif
200 out:
201 return ret;
202 }
203
204 static int ehci_shutdown(struct ehci_ctrl *ctrl)
205 {
206 int i, ret = 0;
207 uint32_t cmd, reg;
208
209 if (!ctrl || !ctrl->hcor)
210 return -EINVAL;
211
212 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
213 /* If not run, directly return */
214 if (!(cmd & CMD_RUN))
215 return 0;
216 cmd &= ~(CMD_PSE | CMD_ASE);
217 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
218 ret = handshake(&ctrl->hcor->or_usbsts, STS_ASS | STS_PSS, 0,
219 100 * 1000);
220
221 if (!ret) {
222 for (i = 0; i < CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS; i++) {
223 reg = ehci_readl(&ctrl->hcor->or_portsc[i]);
224 reg |= EHCI_PS_SUSP;
225 ehci_writel(&ctrl->hcor->or_portsc[i], reg);
226 }
227
228 cmd &= ~CMD_RUN;
229 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
230 ret = handshake(&ctrl->hcor->or_usbsts, STS_HALT, STS_HALT,
231 HCHALT_TIMEOUT);
232 }
233
234 if (ret)
235 puts("EHCI failed to shut down host controller.\n");
236
237 return ret;
238 }
239
240 static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz)
241 {
242 uint32_t delta, next;
243 unsigned long addr = (unsigned long)buf;
244 int idx;
245
246 if (addr != ALIGN(addr, ARCH_DMA_MINALIGN))
247 debug("EHCI-HCD: Misaligned buffer address (%p)\n", buf);
248
249 flush_dcache_range(addr, ALIGN(addr + sz, ARCH_DMA_MINALIGN));
250
251 idx = 0;
252 while (idx < QT_BUFFER_CNT) {
253 td->qt_buffer[idx] = cpu_to_hc32(virt_to_phys((void *)addr));
254 td->qt_buffer_hi[idx] = 0;
255 next = (addr + EHCI_PAGE_SIZE) & ~(EHCI_PAGE_SIZE - 1);
256 delta = next - addr;
257 if (delta >= sz)
258 break;
259 sz -= delta;
260 addr = next;
261 idx++;
262 }
263
264 if (idx == QT_BUFFER_CNT) {
265 printf("out of buffer pointers (%zu bytes left)\n", sz);
266 return -1;
267 }
268
269 return 0;
270 }
271
272 static inline u8 ehci_encode_speed(enum usb_device_speed speed)
273 {
274 #define QH_HIGH_SPEED 2
275 #define QH_FULL_SPEED 0
276 #define QH_LOW_SPEED 1
277 if (speed == USB_SPEED_HIGH)
278 return QH_HIGH_SPEED;
279 if (speed == USB_SPEED_LOW)
280 return QH_LOW_SPEED;
281 return QH_FULL_SPEED;
282 }
283
284 static void ehci_update_endpt2_dev_n_port(struct usb_device *udev,
285 struct QH *qh)
286 {
287 uint8_t portnr = 0;
288 uint8_t hubaddr = 0;
289
290 if (udev->speed != USB_SPEED_LOW && udev->speed != USB_SPEED_FULL)
291 return;
292
293 usb_find_usb2_hub_address_port(udev, &hubaddr, &portnr);
294
295 qh->qh_endpt2 |= cpu_to_hc32(QH_ENDPT2_PORTNUM(portnr) |
296 QH_ENDPT2_HUBADDR(hubaddr));
297 }
298
299 static int
300 ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
301 int length, struct devrequest *req)
302 {
303 ALLOC_ALIGN_BUFFER(struct QH, qh, 1, USB_DMA_MINALIGN);
304 struct qTD *qtd;
305 int qtd_count = 0;
306 int qtd_counter = 0;
307 volatile struct qTD *vtd;
308 unsigned long ts;
309 uint32_t *tdp;
310 uint32_t endpt, maxpacket, token, usbsts;
311 uint32_t c, toggle;
312 uint32_t cmd;
313 int timeout;
314 int ret = 0;
315 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
316
317 debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe,
318 buffer, length, req);
319 if (req != NULL)
320 debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n",
321 req->request, req->request,
322 req->requesttype, req->requesttype,
323 le16_to_cpu(req->value), le16_to_cpu(req->value),
324 le16_to_cpu(req->index));
325
326 #define PKT_ALIGN 512
327 /*
328 * The USB transfer is split into qTD transfers. Eeach qTD transfer is
329 * described by a transfer descriptor (the qTD). The qTDs form a linked
330 * list with a queue head (QH).
331 *
332 * Each qTD transfer starts with a new USB packet, i.e. a packet cannot
333 * have its beginning in a qTD transfer and its end in the following
334 * one, so the qTD transfer lengths have to be chosen accordingly.
335 *
336 * Each qTD transfer uses up to QT_BUFFER_CNT data buffers, mapped to
337 * single pages. The first data buffer can start at any offset within a
338 * page (not considering the cache-line alignment issues), while the
339 * following buffers must be page-aligned. There is no alignment
340 * constraint on the size of a qTD transfer.
341 */
342 if (req != NULL)
343 /* 1 qTD will be needed for SETUP, and 1 for ACK. */
344 qtd_count += 1 + 1;
345 if (length > 0 || req == NULL) {
346 /*
347 * Determine the qTD transfer size that will be used for the
348 * data payload (not considering the first qTD transfer, which
349 * may be longer or shorter, and the final one, which may be
350 * shorter).
351 *
352 * In order to keep each packet within a qTD transfer, the qTD
353 * transfer size is aligned to PKT_ALIGN, which is a multiple of
354 * wMaxPacketSize (except in some cases for interrupt transfers,
355 * see comment in submit_int_msg()).
356 *
357 * By default, i.e. if the input buffer is aligned to PKT_ALIGN,
358 * QT_BUFFER_CNT full pages will be used.
359 */
360 int xfr_sz = QT_BUFFER_CNT;
361 /*
362 * However, if the input buffer is not aligned to PKT_ALIGN, the
363 * qTD transfer size will be one page shorter, and the first qTD
364 * data buffer of each transfer will be page-unaligned.
365 */
366 if ((unsigned long)buffer & (PKT_ALIGN - 1))
367 xfr_sz--;
368 /* Convert the qTD transfer size to bytes. */
369 xfr_sz *= EHCI_PAGE_SIZE;
370 /*
371 * Approximate by excess the number of qTDs that will be
372 * required for the data payload. The exact formula is way more
373 * complicated and saves at most 2 qTDs, i.e. a total of 128
374 * bytes.
375 */
376 qtd_count += 2 + length / xfr_sz;
377 }
378 /*
379 * Threshold value based on the worst-case total size of the allocated qTDs for
380 * a mass-storage transfer of 65535 blocks of 512 bytes.
381 */
382 #if CONFIG_SYS_MALLOC_LEN <= 64 + 128 * 1024
383 #warning CONFIG_SYS_MALLOC_LEN may be too small for EHCI
384 #endif
385 qtd = memalign(USB_DMA_MINALIGN, qtd_count * sizeof(struct qTD));
386 if (qtd == NULL) {
387 printf("unable to allocate TDs\n");
388 return -1;
389 }
390
391 memset(qh, 0, sizeof(struct QH));
392 memset(qtd, 0, qtd_count * sizeof(*qtd));
393
394 toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
395
396 /*
397 * Setup QH (3.6 in ehci-r10.pdf)
398 *
399 * qh_link ................. 03-00 H
400 * qh_endpt1 ............... 07-04 H
401 * qh_endpt2 ............... 0B-08 H
402 * - qh_curtd
403 * qh_overlay.qt_next ...... 13-10 H
404 * - qh_overlay.qt_altnext
405 */
406 qh->qh_link = cpu_to_hc32(virt_to_phys(&ctrl->qh_list) | QH_LINK_TYPE_QH);
407 c = (dev->speed != USB_SPEED_HIGH) && !usb_pipeendpoint(pipe);
408 maxpacket = usb_maxpacket(dev, pipe);
409 endpt = QH_ENDPT1_RL(8) | QH_ENDPT1_C(c) |
410 QH_ENDPT1_MAXPKTLEN(maxpacket) | QH_ENDPT1_H(0) |
411 QH_ENDPT1_DTC(QH_ENDPT1_DTC_DT_FROM_QTD) |
412 QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) |
413 QH_ENDPT1_ENDPT(usb_pipeendpoint(pipe)) | QH_ENDPT1_I(0) |
414 QH_ENDPT1_DEVADDR(usb_pipedevice(pipe));
415 qh->qh_endpt1 = cpu_to_hc32(endpt);
416 endpt = QH_ENDPT2_MULT(1) | QH_ENDPT2_UFCMASK(0) | QH_ENDPT2_UFSMASK(0);
417 qh->qh_endpt2 = cpu_to_hc32(endpt);
418 ehci_update_endpt2_dev_n_port(dev, qh);
419 qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
420 qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
421
422 tdp = &qh->qh_overlay.qt_next;
423 if (req != NULL) {
424 /*
425 * Setup request qTD (3.5 in ehci-r10.pdf)
426 *
427 * qt_next ................ 03-00 H
428 * qt_altnext ............. 07-04 H
429 * qt_token ............... 0B-08 H
430 *
431 * [ buffer, buffer_hi ] loaded with "req".
432 */
433 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
434 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
435 token = QT_TOKEN_DT(0) | QT_TOKEN_TOTALBYTES(sizeof(*req)) |
436 QT_TOKEN_IOC(0) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
437 QT_TOKEN_PID(QT_TOKEN_PID_SETUP) |
438 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
439 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
440 if (ehci_td_buffer(&qtd[qtd_counter], req, sizeof(*req))) {
441 printf("unable to construct SETUP TD\n");
442 goto fail;
443 }
444 /* Update previous qTD! */
445 *tdp = cpu_to_hc32(virt_to_phys(&qtd[qtd_counter]));
446 tdp = &qtd[qtd_counter++].qt_next;
447 toggle = 1;
448 }
449
450 if (length > 0 || req == NULL) {
451 uint8_t *buf_ptr = buffer;
452 int left_length = length;
453
454 do {
455 /*
456 * Determine the size of this qTD transfer. By default,
457 * QT_BUFFER_CNT full pages can be used.
458 */
459 int xfr_bytes = QT_BUFFER_CNT * EHCI_PAGE_SIZE;
460 /*
461 * However, if the input buffer is not page-aligned, the
462 * portion of the first page before the buffer start
463 * offset within that page is unusable.
464 */
465 xfr_bytes -= (unsigned long)buf_ptr & (EHCI_PAGE_SIZE - 1);
466 /*
467 * In order to keep each packet within a qTD transfer,
468 * align the qTD transfer size to PKT_ALIGN.
469 */
470 xfr_bytes &= ~(PKT_ALIGN - 1);
471 /*
472 * This transfer may be shorter than the available qTD
473 * transfer size that has just been computed.
474 */
475 xfr_bytes = min(xfr_bytes, left_length);
476
477 /*
478 * Setup request qTD (3.5 in ehci-r10.pdf)
479 *
480 * qt_next ................ 03-00 H
481 * qt_altnext ............. 07-04 H
482 * qt_token ............... 0B-08 H
483 *
484 * [ buffer, buffer_hi ] loaded with "buffer".
485 */
486 qtd[qtd_counter].qt_next =
487 cpu_to_hc32(QT_NEXT_TERMINATE);
488 qtd[qtd_counter].qt_altnext =
489 cpu_to_hc32(QT_NEXT_TERMINATE);
490 token = QT_TOKEN_DT(toggle) |
491 QT_TOKEN_TOTALBYTES(xfr_bytes) |
492 QT_TOKEN_IOC(req == NULL) | QT_TOKEN_CPAGE(0) |
493 QT_TOKEN_CERR(3) |
494 QT_TOKEN_PID(usb_pipein(pipe) ?
495 QT_TOKEN_PID_IN : QT_TOKEN_PID_OUT) |
496 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
497 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
498 if (ehci_td_buffer(&qtd[qtd_counter], buf_ptr,
499 xfr_bytes)) {
500 printf("unable to construct DATA TD\n");
501 goto fail;
502 }
503 /* Update previous qTD! */
504 *tdp = cpu_to_hc32(virt_to_phys(&qtd[qtd_counter]));
505 tdp = &qtd[qtd_counter++].qt_next;
506 /*
507 * Data toggle has to be adjusted since the qTD transfer
508 * size is not always an even multiple of
509 * wMaxPacketSize.
510 */
511 if ((xfr_bytes / maxpacket) & 1)
512 toggle ^= 1;
513 buf_ptr += xfr_bytes;
514 left_length -= xfr_bytes;
515 } while (left_length > 0);
516 }
517
518 if (req != NULL) {
519 /*
520 * Setup request qTD (3.5 in ehci-r10.pdf)
521 *
522 * qt_next ................ 03-00 H
523 * qt_altnext ............. 07-04 H
524 * qt_token ............... 0B-08 H
525 */
526 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
527 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
528 token = QT_TOKEN_DT(1) | QT_TOKEN_TOTALBYTES(0) |
529 QT_TOKEN_IOC(1) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
530 QT_TOKEN_PID(usb_pipein(pipe) ?
531 QT_TOKEN_PID_OUT : QT_TOKEN_PID_IN) |
532 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
533 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
534 /* Update previous qTD! */
535 *tdp = cpu_to_hc32(virt_to_phys(&qtd[qtd_counter]));
536 tdp = &qtd[qtd_counter++].qt_next;
537 }
538
539 ctrl->qh_list.qh_link = cpu_to_hc32(virt_to_phys(qh) | QH_LINK_TYPE_QH);
540
541 /* Flush dcache */
542 flush_dcache_range((unsigned long)&ctrl->qh_list,
543 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
544 flush_dcache_range((unsigned long)qh, ALIGN_END_ADDR(struct QH, qh, 1));
545 flush_dcache_range((unsigned long)qtd,
546 ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
547
548 /* Set async. queue head pointer. */
549 ehci_writel(&ctrl->hcor->or_asynclistaddr, virt_to_phys(&ctrl->qh_list));
550
551 usbsts = ehci_readl(&ctrl->hcor->or_usbsts);
552 ehci_writel(&ctrl->hcor->or_usbsts, (usbsts & 0x3f));
553
554 /* Enable async. schedule. */
555 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
556 cmd |= CMD_ASE;
557 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
558
559 ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, STS_ASS,
560 100 * 1000);
561 if (ret < 0) {
562 printf("EHCI fail timeout STS_ASS set\n");
563 goto fail;
564 }
565
566 /* Wait for TDs to be processed. */
567 ts = get_timer(0);
568 vtd = &qtd[qtd_counter - 1];
569 timeout = USB_TIMEOUT_MS(pipe);
570 do {
571 /* Invalidate dcache */
572 invalidate_dcache_range((unsigned long)&ctrl->qh_list,
573 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
574 invalidate_dcache_range((unsigned long)qh,
575 ALIGN_END_ADDR(struct QH, qh, 1));
576 invalidate_dcache_range((unsigned long)qtd,
577 ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
578
579 token = hc32_to_cpu(vtd->qt_token);
580 if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE))
581 break;
582 WATCHDOG_RESET();
583 } while (get_timer(ts) < timeout);
584
585 /*
586 * Invalidate the memory area occupied by buffer
587 * Don't try to fix the buffer alignment, if it isn't properly
588 * aligned it's upper layer's fault so let invalidate_dcache_range()
589 * vow about it. But we have to fix the length as it's actual
590 * transfer length and can be unaligned. This is potentially
591 * dangerous operation, it's responsibility of the calling
592 * code to make sure enough space is reserved.
593 */
594 invalidate_dcache_range((unsigned long)buffer,
595 ALIGN((unsigned long)buffer + length, ARCH_DMA_MINALIGN));
596
597 /* Check that the TD processing happened */
598 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)
599 printf("EHCI timed out on TD - token=%#x\n", token);
600
601 /* Disable async schedule. */
602 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
603 cmd &= ~CMD_ASE;
604 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
605
606 ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, 0,
607 100 * 1000);
608 if (ret < 0) {
609 printf("EHCI fail timeout STS_ASS reset\n");
610 goto fail;
611 }
612
613 token = hc32_to_cpu(qh->qh_overlay.qt_token);
614 if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)) {
615 debug("TOKEN=%#x\n", token);
616 switch (QT_TOKEN_GET_STATUS(token) &
617 ~(QT_TOKEN_STATUS_SPLITXSTATE | QT_TOKEN_STATUS_PERR)) {
618 case 0:
619 toggle = QT_TOKEN_GET_DT(token);
620 usb_settoggle(dev, usb_pipeendpoint(pipe),
621 usb_pipeout(pipe), toggle);
622 dev->status = 0;
623 break;
624 case QT_TOKEN_STATUS_HALTED:
625 dev->status = USB_ST_STALLED;
626 break;
627 case QT_TOKEN_STATUS_ACTIVE | QT_TOKEN_STATUS_DATBUFERR:
628 case QT_TOKEN_STATUS_DATBUFERR:
629 dev->status = USB_ST_BUF_ERR;
630 break;
631 case QT_TOKEN_STATUS_HALTED | QT_TOKEN_STATUS_BABBLEDET:
632 case QT_TOKEN_STATUS_BABBLEDET:
633 dev->status = USB_ST_BABBLE_DET;
634 break;
635 default:
636 dev->status = USB_ST_CRC_ERR;
637 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_HALTED)
638 dev->status |= USB_ST_STALLED;
639 break;
640 }
641 dev->act_len = length - QT_TOKEN_GET_TOTALBYTES(token);
642 } else {
643 dev->act_len = 0;
644 #ifndef CONFIG_USB_EHCI_FARADAY
645 debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n",
646 dev->devnum, ehci_readl(&ctrl->hcor->or_usbsts),
647 ehci_readl(&ctrl->hcor->or_portsc[0]),
648 ehci_readl(&ctrl->hcor->or_portsc[1]));
649 #endif
650 }
651
652 free(qtd);
653 return (dev->status != USB_ST_NOT_PROC) ? 0 : -1;
654
655 fail:
656 free(qtd);
657 return -1;
658 }
659
660 static int ehci_submit_root(struct usb_device *dev, unsigned long pipe,
661 void *buffer, int length, struct devrequest *req)
662 {
663 uint8_t tmpbuf[4];
664 u16 typeReq;
665 void *srcptr = NULL;
666 int len, srclen;
667 uint32_t reg;
668 uint32_t *status_reg;
669 int port = le16_to_cpu(req->index) & 0xff;
670 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
671
672 srclen = 0;
673
674 debug("req=%u (%#x), type=%u (%#x), value=%u, index=%u\n",
675 req->request, req->request,
676 req->requesttype, req->requesttype,
677 le16_to_cpu(req->value), le16_to_cpu(req->index));
678
679 typeReq = req->request | req->requesttype << 8;
680
681 switch (typeReq) {
682 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
683 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
684 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
685 status_reg = ctrl->ops.get_portsc_register(ctrl, port - 1);
686 if (!status_reg)
687 return -1;
688 break;
689 default:
690 status_reg = NULL;
691 break;
692 }
693
694 switch (typeReq) {
695 case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
696 switch (le16_to_cpu(req->value) >> 8) {
697 case USB_DT_DEVICE:
698 debug("USB_DT_DEVICE request\n");
699 srcptr = &descriptor.device;
700 srclen = descriptor.device.bLength;
701 break;
702 case USB_DT_CONFIG:
703 debug("USB_DT_CONFIG config\n");
704 srcptr = &descriptor.config;
705 srclen = descriptor.config.bLength +
706 descriptor.interface.bLength +
707 descriptor.endpoint.bLength;
708 break;
709 case USB_DT_STRING:
710 debug("USB_DT_STRING config\n");
711 switch (le16_to_cpu(req->value) & 0xff) {
712 case 0: /* Language */
713 srcptr = "\4\3\1\0";
714 srclen = 4;
715 break;
716 case 1: /* Vendor */
717 srcptr = "\16\3u\0-\0b\0o\0o\0t\0";
718 srclen = 14;
719 break;
720 case 2: /* Product */
721 srcptr = "\52\3E\0H\0C\0I\0 "
722 "\0H\0o\0s\0t\0 "
723 "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0";
724 srclen = 42;
725 break;
726 default:
727 debug("unknown value DT_STRING %x\n",
728 le16_to_cpu(req->value));
729 goto unknown;
730 }
731 break;
732 default:
733 debug("unknown value %x\n", le16_to_cpu(req->value));
734 goto unknown;
735 }
736 break;
737 case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
738 switch (le16_to_cpu(req->value) >> 8) {
739 case USB_DT_HUB:
740 debug("USB_DT_HUB config\n");
741 srcptr = &descriptor.hub;
742 srclen = descriptor.hub.bLength;
743 break;
744 default:
745 debug("unknown value %x\n", le16_to_cpu(req->value));
746 goto unknown;
747 }
748 break;
749 case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
750 debug("USB_REQ_SET_ADDRESS\n");
751 ctrl->rootdev = le16_to_cpu(req->value);
752 break;
753 case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
754 debug("USB_REQ_SET_CONFIGURATION\n");
755 /* Nothing to do */
756 break;
757 case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8):
758 tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */
759 tmpbuf[1] = 0;
760 srcptr = tmpbuf;
761 srclen = 2;
762 break;
763 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
764 memset(tmpbuf, 0, 4);
765 reg = ehci_readl(status_reg);
766 if (reg & EHCI_PS_CS)
767 tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
768 if (reg & EHCI_PS_PE)
769 tmpbuf[0] |= USB_PORT_STAT_ENABLE;
770 if (reg & EHCI_PS_SUSP)
771 tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
772 if (reg & EHCI_PS_OCA)
773 tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
774 if (reg & EHCI_PS_PR)
775 tmpbuf[0] |= USB_PORT_STAT_RESET;
776 if (reg & EHCI_PS_PP)
777 tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
778
779 if (ehci_is_TDI()) {
780 switch (ctrl->ops.get_port_speed(ctrl, reg)) {
781 case PORTSC_PSPD_FS:
782 break;
783 case PORTSC_PSPD_LS:
784 tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8;
785 break;
786 case PORTSC_PSPD_HS:
787 default:
788 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
789 break;
790 }
791 } else {
792 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
793 }
794
795 if (reg & EHCI_PS_CSC)
796 tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
797 if (reg & EHCI_PS_PEC)
798 tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
799 if (reg & EHCI_PS_OCC)
800 tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
801 if (ctrl->portreset & (1 << port))
802 tmpbuf[2] |= USB_PORT_STAT_C_RESET;
803
804 srcptr = tmpbuf;
805 srclen = 4;
806 break;
807 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
808 reg = ehci_readl(status_reg);
809 reg &= ~EHCI_PS_CLEAR;
810 switch (le16_to_cpu(req->value)) {
811 case USB_PORT_FEAT_ENABLE:
812 reg |= EHCI_PS_PE;
813 ehci_writel(status_reg, reg);
814 break;
815 case USB_PORT_FEAT_POWER:
816 if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams))) {
817 reg |= EHCI_PS_PP;
818 ehci_writel(status_reg, reg);
819 }
820 break;
821 case USB_PORT_FEAT_RESET:
822 if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) == EHCI_PS_CS &&
823 !ehci_is_TDI() &&
824 EHCI_PS_IS_LOWSPEED(reg)) {
825 /* Low speed device, give up ownership. */
826 debug("port %d low speed --> companion\n",
827 port - 1);
828 reg |= EHCI_PS_PO;
829 ehci_writel(status_reg, reg);
830 return -ENXIO;
831 } else {
832 int ret;
833
834 reg |= EHCI_PS_PR;
835 reg &= ~EHCI_PS_PE;
836 ehci_writel(status_reg, reg);
837 /*
838 * caller must wait, then call GetPortStatus
839 * usb 2.0 specification say 50 ms resets on
840 * root
841 */
842 ctrl->ops.powerup_fixup(ctrl, status_reg, &reg);
843
844 ehci_writel(status_reg, reg & ~EHCI_PS_PR);
845 /*
846 * A host controller must terminate the reset
847 * and stabilize the state of the port within
848 * 2 milliseconds
849 */
850 ret = handshake(status_reg, EHCI_PS_PR, 0,
851 2 * 1000);
852 if (!ret) {
853 reg = ehci_readl(status_reg);
854 if ((reg & (EHCI_PS_PE | EHCI_PS_CS))
855 == EHCI_PS_CS && !ehci_is_TDI()) {
856 debug("port %d full speed --> companion\n", port - 1);
857 reg &= ~EHCI_PS_CLEAR;
858 reg |= EHCI_PS_PO;
859 ehci_writel(status_reg, reg);
860 return -ENXIO;
861 } else {
862 ctrl->portreset |= 1 << port;
863 }
864 } else {
865 printf("port(%d) reset error\n",
866 port - 1);
867 }
868 }
869 break;
870 case USB_PORT_FEAT_TEST:
871 ehci_shutdown(ctrl);
872 reg &= ~(0xf << 16);
873 reg |= ((le16_to_cpu(req->index) >> 8) & 0xf) << 16;
874 ehci_writel(status_reg, reg);
875 break;
876 default:
877 debug("unknown feature %x\n", le16_to_cpu(req->value));
878 goto unknown;
879 }
880 /* unblock posted writes */
881 (void) ehci_readl(&ctrl->hcor->or_usbcmd);
882 break;
883 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
884 reg = ehci_readl(status_reg);
885 reg &= ~EHCI_PS_CLEAR;
886 switch (le16_to_cpu(req->value)) {
887 case USB_PORT_FEAT_ENABLE:
888 reg &= ~EHCI_PS_PE;
889 break;
890 case USB_PORT_FEAT_C_ENABLE:
891 reg |= EHCI_PS_PE;
892 break;
893 case USB_PORT_FEAT_POWER:
894 if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams)))
895 reg &= ~EHCI_PS_PP;
896 break;
897 case USB_PORT_FEAT_C_CONNECTION:
898 reg |= EHCI_PS_CSC;
899 break;
900 case USB_PORT_FEAT_OVER_CURRENT:
901 reg |= EHCI_PS_OCC;
902 break;
903 case USB_PORT_FEAT_C_RESET:
904 ctrl->portreset &= ~(1 << port);
905 break;
906 default:
907 debug("unknown feature %x\n", le16_to_cpu(req->value));
908 goto unknown;
909 }
910 ehci_writel(status_reg, reg);
911 /* unblock posted write */
912 (void) ehci_readl(&ctrl->hcor->or_usbcmd);
913 break;
914 default:
915 debug("Unknown request\n");
916 goto unknown;
917 }
918
919 mdelay(1);
920 len = min3(srclen, (int)le16_to_cpu(req->length), length);
921 if (srcptr != NULL && len > 0)
922 memcpy(buffer, srcptr, len);
923 else
924 debug("Len is 0\n");
925
926 dev->act_len = len;
927 dev->status = 0;
928 return 0;
929
930 unknown:
931 debug("requesttype=%x, request=%x, value=%x, index=%x, length=%x\n",
932 req->requesttype, req->request, le16_to_cpu(req->value),
933 le16_to_cpu(req->index), le16_to_cpu(req->length));
934
935 dev->act_len = 0;
936 dev->status = USB_ST_STALLED;
937 return -1;
938 }
939
940 static const struct ehci_ops default_ehci_ops = {
941 .set_usb_mode = ehci_set_usbmode,
942 .get_port_speed = ehci_get_port_speed,
943 .powerup_fixup = ehci_powerup_fixup,
944 .get_portsc_register = ehci_get_portsc_register,
945 };
946
947 static void ehci_setup_ops(struct ehci_ctrl *ctrl, const struct ehci_ops *ops)
948 {
949 if (!ops) {
950 ctrl->ops = default_ehci_ops;
951 } else {
952 ctrl->ops = *ops;
953 if (!ctrl->ops.set_usb_mode)
954 ctrl->ops.set_usb_mode = ehci_set_usbmode;
955 if (!ctrl->ops.get_port_speed)
956 ctrl->ops.get_port_speed = ehci_get_port_speed;
957 if (!ctrl->ops.powerup_fixup)
958 ctrl->ops.powerup_fixup = ehci_powerup_fixup;
959 if (!ctrl->ops.get_portsc_register)
960 ctrl->ops.get_portsc_register =
961 ehci_get_portsc_register;
962 }
963 }
964
965 #ifndef CONFIG_DM_USB
966 void ehci_set_controller_priv(int index, void *priv, const struct ehci_ops *ops)
967 {
968 struct ehci_ctrl *ctrl = &ehcic[index];
969
970 ctrl->priv = priv;
971 ehci_setup_ops(ctrl, ops);
972 }
973
974 void *ehci_get_controller_priv(int index)
975 {
976 return ehcic[index].priv;
977 }
978 #endif
979
980 static int ehci_common_init(struct ehci_ctrl *ctrl, uint tweaks)
981 {
982 struct QH *qh_list;
983 struct QH *periodic;
984 uint32_t reg;
985 uint32_t cmd;
986 int i;
987
988 /* Set the high address word (aka segment) for 64-bit controller */
989 if (ehci_readl(&ctrl->hccr->cr_hccparams) & 1)
990 ehci_writel(&ctrl->hcor->or_ctrldssegment, 0);
991
992 qh_list = &ctrl->qh_list;
993
994 /* Set head of reclaim list */
995 memset(qh_list, 0, sizeof(*qh_list));
996 qh_list->qh_link = cpu_to_hc32(virt_to_phys(qh_list) | QH_LINK_TYPE_QH);
997 qh_list->qh_endpt1 = cpu_to_hc32(QH_ENDPT1_H(1) |
998 QH_ENDPT1_EPS(USB_SPEED_HIGH));
999 qh_list->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
1000 qh_list->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1001 qh_list->qh_overlay.qt_token =
1002 cpu_to_hc32(QT_TOKEN_STATUS(QT_TOKEN_STATUS_HALTED));
1003
1004 flush_dcache_range((unsigned long)qh_list,
1005 ALIGN_END_ADDR(struct QH, qh_list, 1));
1006
1007 /* Set async. queue head pointer. */
1008 ehci_writel(&ctrl->hcor->or_asynclistaddr, virt_to_phys(qh_list));
1009
1010 /*
1011 * Set up periodic list
1012 * Step 1: Parent QH for all periodic transfers.
1013 */
1014 ctrl->periodic_schedules = 0;
1015 periodic = &ctrl->periodic_queue;
1016 memset(periodic, 0, sizeof(*periodic));
1017 periodic->qh_link = cpu_to_hc32(QH_LINK_TERMINATE);
1018 periodic->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
1019 periodic->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1020
1021 flush_dcache_range((unsigned long)periodic,
1022 ALIGN_END_ADDR(struct QH, periodic, 1));
1023
1024 /*
1025 * Step 2: Setup frame-list: Every microframe, USB tries the same list.
1026 * In particular, device specifications on polling frequency
1027 * are disregarded. Keyboards seem to send NAK/NYet reliably
1028 * when polled with an empty buffer.
1029 *
1030 * Split Transactions will be spread across microframes using
1031 * S-mask and C-mask.
1032 */
1033 if (ctrl->periodic_list == NULL)
1034 ctrl->periodic_list = memalign(4096, 1024 * 4);
1035
1036 if (!ctrl->periodic_list)
1037 return -ENOMEM;
1038 for (i = 0; i < 1024; i++) {
1039 ctrl->periodic_list[i] = cpu_to_hc32((unsigned long)periodic
1040 | QH_LINK_TYPE_QH);
1041 }
1042
1043 flush_dcache_range((unsigned long)ctrl->periodic_list,
1044 ALIGN_END_ADDR(uint32_t, ctrl->periodic_list,
1045 1024));
1046
1047 /* Set periodic list base address */
1048 ehci_writel(&ctrl->hcor->or_periodiclistbase,
1049 (unsigned long)ctrl->periodic_list);
1050
1051 reg = ehci_readl(&ctrl->hccr->cr_hcsparams);
1052 descriptor.hub.bNbrPorts = HCS_N_PORTS(reg);
1053 debug("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
1054 /* Port Indicators */
1055 if (HCS_INDICATOR(reg))
1056 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
1057 | 0x80, &descriptor.hub.wHubCharacteristics);
1058 /* Port Power Control */
1059 if (HCS_PPC(reg))
1060 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
1061 | 0x01, &descriptor.hub.wHubCharacteristics);
1062
1063 /* Start the host controller. */
1064 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
1065 /*
1066 * Philips, Intel, and maybe others need CMD_RUN before the
1067 * root hub will detect new devices (why?); NEC doesn't
1068 */
1069 cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
1070 cmd |= CMD_RUN;
1071 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
1072
1073 if (!(tweaks & EHCI_TWEAK_NO_INIT_CF)) {
1074 /* take control over the ports */
1075 cmd = ehci_readl(&ctrl->hcor->or_configflag);
1076 cmd |= FLAG_CF;
1077 ehci_writel(&ctrl->hcor->or_configflag, cmd);
1078 }
1079
1080 /* unblock posted write */
1081 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
1082 mdelay(5);
1083 reg = HC_VERSION(ehci_readl(&ctrl->hccr->cr_capbase));
1084 printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff);
1085
1086 return 0;
1087 }
1088
1089 #ifndef CONFIG_DM_USB
1090 int usb_lowlevel_stop(int index)
1091 {
1092 ehci_shutdown(&ehcic[index]);
1093 return ehci_hcd_stop(index);
1094 }
1095
1096 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1097 {
1098 struct ehci_ctrl *ctrl = &ehcic[index];
1099 uint tweaks = 0;
1100 int rc;
1101
1102 /**
1103 * Set ops to default_ehci_ops, ehci_hcd_init should call
1104 * ehci_set_controller_priv to change any of these function pointers.
1105 */
1106 ctrl->ops = default_ehci_ops;
1107
1108 rc = ehci_hcd_init(index, init, &ctrl->hccr, &ctrl->hcor);
1109 if (rc)
1110 return rc;
1111 if (init == USB_INIT_DEVICE)
1112 goto done;
1113
1114 /* EHCI spec section 4.1 */
1115 if (ehci_reset(ctrl))
1116 return -1;
1117
1118 #if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET)
1119 rc = ehci_hcd_init(index, init, &ctrl->hccr, &ctrl->hcor);
1120 if (rc)
1121 return rc;
1122 #endif
1123 #ifdef CONFIG_USB_EHCI_FARADAY
1124 tweaks |= EHCI_TWEAK_NO_INIT_CF;
1125 #endif
1126 rc = ehci_common_init(ctrl, tweaks);
1127 if (rc)
1128 return rc;
1129
1130 ctrl->rootdev = 0;
1131 done:
1132 *controller = &ehcic[index];
1133 return 0;
1134 }
1135 #endif
1136
1137 static int _ehci_submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
1138 void *buffer, int length)
1139 {
1140
1141 if (usb_pipetype(pipe) != PIPE_BULK) {
1142 debug("non-bulk pipe (type=%lu)", usb_pipetype(pipe));
1143 return -1;
1144 }
1145 return ehci_submit_async(dev, pipe, buffer, length, NULL);
1146 }
1147
1148 static int _ehci_submit_control_msg(struct usb_device *dev, unsigned long pipe,
1149 void *buffer, int length,
1150 struct devrequest *setup)
1151 {
1152 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
1153
1154 if (usb_pipetype(pipe) != PIPE_CONTROL) {
1155 debug("non-control pipe (type=%lu)", usb_pipetype(pipe));
1156 return -1;
1157 }
1158
1159 if (usb_pipedevice(pipe) == ctrl->rootdev) {
1160 if (!ctrl->rootdev)
1161 dev->speed = USB_SPEED_HIGH;
1162 return ehci_submit_root(dev, pipe, buffer, length, setup);
1163 }
1164 return ehci_submit_async(dev, pipe, buffer, length, setup);
1165 }
1166
1167 struct int_queue {
1168 int elementsize;
1169 unsigned long pipe;
1170 struct QH *first;
1171 struct QH *current;
1172 struct QH *last;
1173 struct qTD *tds;
1174 };
1175
1176 #define NEXT_QH(qh) (struct QH *)((unsigned long)hc32_to_cpu((qh)->qh_link) & ~0x1f)
1177
1178 static int
1179 enable_periodic(struct ehci_ctrl *ctrl)
1180 {
1181 uint32_t cmd;
1182 struct ehci_hcor *hcor = ctrl->hcor;
1183 int ret;
1184
1185 cmd = ehci_readl(&hcor->or_usbcmd);
1186 cmd |= CMD_PSE;
1187 ehci_writel(&hcor->or_usbcmd, cmd);
1188
1189 ret = handshake((uint32_t *)&hcor->or_usbsts,
1190 STS_PSS, STS_PSS, 100 * 1000);
1191 if (ret < 0) {
1192 printf("EHCI failed: timeout when enabling periodic list\n");
1193 return -ETIMEDOUT;
1194 }
1195 udelay(1000);
1196 return 0;
1197 }
1198
1199 static int
1200 disable_periodic(struct ehci_ctrl *ctrl)
1201 {
1202 uint32_t cmd;
1203 struct ehci_hcor *hcor = ctrl->hcor;
1204 int ret;
1205
1206 cmd = ehci_readl(&hcor->or_usbcmd);
1207 cmd &= ~CMD_PSE;
1208 ehci_writel(&hcor->or_usbcmd, cmd);
1209
1210 ret = handshake((uint32_t *)&hcor->or_usbsts,
1211 STS_PSS, 0, 100 * 1000);
1212 if (ret < 0) {
1213 printf("EHCI failed: timeout when disabling periodic list\n");
1214 return -ETIMEDOUT;
1215 }
1216 return 0;
1217 }
1218
1219 static struct int_queue *_ehci_create_int_queue(struct usb_device *dev,
1220 unsigned long pipe, int queuesize, int elementsize,
1221 void *buffer, int interval)
1222 {
1223 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
1224 struct int_queue *result = NULL;
1225 uint32_t i, toggle;
1226
1227 /*
1228 * Interrupt transfers requiring several transactions are not supported
1229 * because bInterval is ignored.
1230 *
1231 * Also, ehci_submit_async() relies on wMaxPacketSize being a power of 2
1232 * <= PKT_ALIGN if several qTDs are required, while the USB
1233 * specification does not constrain this for interrupt transfers. That
1234 * means that ehci_submit_async() would support interrupt transfers
1235 * requiring several transactions only as long as the transfer size does
1236 * not require more than a single qTD.
1237 */
1238 if (elementsize > usb_maxpacket(dev, pipe)) {
1239 printf("%s: xfers requiring several transactions are not supported.\n",
1240 __func__);
1241 return NULL;
1242 }
1243
1244 debug("Enter create_int_queue\n");
1245 if (usb_pipetype(pipe) != PIPE_INTERRUPT) {
1246 debug("non-interrupt pipe (type=%lu)", usb_pipetype(pipe));
1247 return NULL;
1248 }
1249
1250 /* limit to 4 full pages worth of data -
1251 * we can safely fit them in a single TD,
1252 * no matter the alignment
1253 */
1254 if (elementsize >= 16384) {
1255 debug("too large elements for interrupt transfers\n");
1256 return NULL;
1257 }
1258
1259 result = malloc(sizeof(*result));
1260 if (!result) {
1261 debug("ehci intr queue: out of memory\n");
1262 goto fail1;
1263 }
1264 result->elementsize = elementsize;
1265 result->pipe = pipe;
1266 result->first = memalign(USB_DMA_MINALIGN,
1267 sizeof(struct QH) * queuesize);
1268 if (!result->first) {
1269 debug("ehci intr queue: out of memory\n");
1270 goto fail2;
1271 }
1272 result->current = result->first;
1273 result->last = result->first + queuesize - 1;
1274 result->tds = memalign(USB_DMA_MINALIGN,
1275 sizeof(struct qTD) * queuesize);
1276 if (!result->tds) {
1277 debug("ehci intr queue: out of memory\n");
1278 goto fail3;
1279 }
1280 memset(result->first, 0, sizeof(struct QH) * queuesize);
1281 memset(result->tds, 0, sizeof(struct qTD) * queuesize);
1282
1283 toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
1284
1285 for (i = 0; i < queuesize; i++) {
1286 struct QH *qh = result->first + i;
1287 struct qTD *td = result->tds + i;
1288 void **buf = &qh->buffer;
1289
1290 qh->qh_link = cpu_to_hc32((unsigned long)(qh+1) | QH_LINK_TYPE_QH);
1291 if (i == queuesize - 1)
1292 qh->qh_link = cpu_to_hc32(QH_LINK_TERMINATE);
1293
1294 qh->qh_overlay.qt_next = cpu_to_hc32((unsigned long)td);
1295 qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1296 qh->qh_endpt1 =
1297 cpu_to_hc32((0 << 28) | /* No NAK reload (ehci 4.9) */
1298 (usb_maxpacket(dev, pipe) << 16) | /* MPS */
1299 (1 << 14) |
1300 QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) |
1301 (usb_pipeendpoint(pipe) << 8) | /* Endpoint Number */
1302 (usb_pipedevice(pipe) << 0));
1303 qh->qh_endpt2 = cpu_to_hc32((1 << 30) | /* 1 Tx per mframe */
1304 (1 << 0)); /* S-mask: microframe 0 */
1305 if (dev->speed == USB_SPEED_LOW ||
1306 dev->speed == USB_SPEED_FULL) {
1307 /* C-mask: microframes 2-4 */
1308 qh->qh_endpt2 |= cpu_to_hc32((0x1c << 8));
1309 }
1310 ehci_update_endpt2_dev_n_port(dev, qh);
1311
1312 td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
1313 td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1314 debug("communication direction is '%s'\n",
1315 usb_pipein(pipe) ? "in" : "out");
1316 td->qt_token = cpu_to_hc32(
1317 QT_TOKEN_DT(toggle) |
1318 (elementsize << 16) |
1319 ((usb_pipein(pipe) ? 1 : 0) << 8) | /* IN/OUT token */
1320 0x80); /* active */
1321 td->qt_buffer[0] =
1322 cpu_to_hc32((unsigned long)buffer + i * elementsize);
1323 td->qt_buffer[1] =
1324 cpu_to_hc32((td->qt_buffer[0] + 0x1000) & ~0xfff);
1325 td->qt_buffer[2] =
1326 cpu_to_hc32((td->qt_buffer[0] + 0x2000) & ~0xfff);
1327 td->qt_buffer[3] =
1328 cpu_to_hc32((td->qt_buffer[0] + 0x3000) & ~0xfff);
1329 td->qt_buffer[4] =
1330 cpu_to_hc32((td->qt_buffer[0] + 0x4000) & ~0xfff);
1331
1332 *buf = buffer + i * elementsize;
1333 toggle ^= 1;
1334 }
1335
1336 flush_dcache_range((unsigned long)buffer,
1337 ALIGN_END_ADDR(char, buffer,
1338 queuesize * elementsize));
1339 flush_dcache_range((unsigned long)result->first,
1340 ALIGN_END_ADDR(struct QH, result->first,
1341 queuesize));
1342 flush_dcache_range((unsigned long)result->tds,
1343 ALIGN_END_ADDR(struct qTD, result->tds,
1344 queuesize));
1345
1346 if (ctrl->periodic_schedules > 0) {
1347 if (disable_periodic(ctrl) < 0) {
1348 debug("FATAL: periodic should never fail, but did");
1349 goto fail3;
1350 }
1351 }
1352
1353 /* hook up to periodic list */
1354 struct QH *list = &ctrl->periodic_queue;
1355 result->last->qh_link = list->qh_link;
1356 list->qh_link = cpu_to_hc32((unsigned long)result->first | QH_LINK_TYPE_QH);
1357
1358 flush_dcache_range((unsigned long)result->last,
1359 ALIGN_END_ADDR(struct QH, result->last, 1));
1360 flush_dcache_range((unsigned long)list,
1361 ALIGN_END_ADDR(struct QH, list, 1));
1362
1363 if (enable_periodic(ctrl) < 0) {
1364 debug("FATAL: periodic should never fail, but did");
1365 goto fail3;
1366 }
1367 ctrl->periodic_schedules++;
1368
1369 debug("Exit create_int_queue\n");
1370 return result;
1371 fail3:
1372 if (result->tds)
1373 free(result->tds);
1374 fail2:
1375 if (result->first)
1376 free(result->first);
1377 if (result)
1378 free(result);
1379 fail1:
1380 return NULL;
1381 }
1382
1383 static void *_ehci_poll_int_queue(struct usb_device *dev,
1384 struct int_queue *queue)
1385 {
1386 struct QH *cur = queue->current;
1387 struct qTD *cur_td;
1388 uint32_t token, toggle;
1389 unsigned long pipe = queue->pipe;
1390
1391 /* depleted queue */
1392 if (cur == NULL) {
1393 debug("Exit poll_int_queue with completed queue\n");
1394 return NULL;
1395 }
1396 /* still active */
1397 cur_td = &queue->tds[queue->current - queue->first];
1398 invalidate_dcache_range((unsigned long)cur_td,
1399 ALIGN_END_ADDR(struct qTD, cur_td, 1));
1400 token = hc32_to_cpu(cur_td->qt_token);
1401 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE) {
1402 debug("Exit poll_int_queue with no completed intr transfer. token is %x\n", token);
1403 return NULL;
1404 }
1405
1406 toggle = QT_TOKEN_GET_DT(token);
1407 usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), toggle);
1408
1409 if (!(cur->qh_link & QH_LINK_TERMINATE))
1410 queue->current++;
1411 else
1412 queue->current = NULL;
1413
1414 invalidate_dcache_range((unsigned long)cur->buffer,
1415 ALIGN_END_ADDR(char, cur->buffer,
1416 queue->elementsize));
1417
1418 debug("Exit poll_int_queue with completed intr transfer. token is %x at %p (first at %p)\n",
1419 token, cur, queue->first);
1420 return cur->buffer;
1421 }
1422
1423 /* Do not free buffers associated with QHs, they're owned by someone else */
1424 static int _ehci_destroy_int_queue(struct usb_device *dev,
1425 struct int_queue *queue)
1426 {
1427 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
1428 int result = -1;
1429 unsigned long timeout;
1430
1431 if (disable_periodic(ctrl) < 0) {
1432 debug("FATAL: periodic should never fail, but did");
1433 goto out;
1434 }
1435 ctrl->periodic_schedules--;
1436
1437 struct QH *cur = &ctrl->periodic_queue;
1438 timeout = get_timer(0) + 500; /* abort after 500ms */
1439 while (!(cur->qh_link & cpu_to_hc32(QH_LINK_TERMINATE))) {
1440 debug("considering %p, with qh_link %x\n", cur, cur->qh_link);
1441 if (NEXT_QH(cur) == queue->first) {
1442 debug("found candidate. removing from chain\n");
1443 cur->qh_link = queue->last->qh_link;
1444 flush_dcache_range((unsigned long)cur,
1445 ALIGN_END_ADDR(struct QH, cur, 1));
1446 result = 0;
1447 break;
1448 }
1449 cur = NEXT_QH(cur);
1450 if (get_timer(0) > timeout) {
1451 printf("Timeout destroying interrupt endpoint queue\n");
1452 result = -1;
1453 goto out;
1454 }
1455 }
1456
1457 if (ctrl->periodic_schedules > 0) {
1458 result = enable_periodic(ctrl);
1459 if (result < 0)
1460 debug("FATAL: periodic should never fail, but did");
1461 }
1462
1463 out:
1464 free(queue->tds);
1465 free(queue->first);
1466 free(queue);
1467
1468 return result;
1469 }
1470
1471 static int _ehci_submit_int_msg(struct usb_device *dev, unsigned long pipe,
1472 void *buffer, int length, int interval)
1473 {
1474 void *backbuffer;
1475 struct int_queue *queue;
1476 unsigned long timeout;
1477 int result = 0, ret;
1478
1479 debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d",
1480 dev, pipe, buffer, length, interval);
1481
1482 queue = _ehci_create_int_queue(dev, pipe, 1, length, buffer, interval);
1483 if (!queue)
1484 return -1;
1485
1486 timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
1487 while ((backbuffer = _ehci_poll_int_queue(dev, queue)) == NULL)
1488 if (get_timer(0) > timeout) {
1489 printf("Timeout poll on interrupt endpoint\n");
1490 result = -ETIMEDOUT;
1491 break;
1492 }
1493
1494 if (backbuffer != buffer) {
1495 debug("got wrong buffer back (%p instead of %p)\n",
1496 backbuffer, buffer);
1497 return -EINVAL;
1498 }
1499
1500 ret = _ehci_destroy_int_queue(dev, queue);
1501 if (ret < 0)
1502 return ret;
1503
1504 /* everything worked out fine */
1505 return result;
1506 }
1507
1508 #ifndef CONFIG_DM_USB
1509 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
1510 void *buffer, int length)
1511 {
1512 return _ehci_submit_bulk_msg(dev, pipe, buffer, length);
1513 }
1514
1515 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1516 int length, struct devrequest *setup)
1517 {
1518 return _ehci_submit_control_msg(dev, pipe, buffer, length, setup);
1519 }
1520
1521 int submit_int_msg(struct usb_device *dev, unsigned long pipe,
1522 void *buffer, int length, int interval)
1523 {
1524 return _ehci_submit_int_msg(dev, pipe, buffer, length, interval);
1525 }
1526
1527 struct int_queue *create_int_queue(struct usb_device *dev,
1528 unsigned long pipe, int queuesize, int elementsize,
1529 void *buffer, int interval)
1530 {
1531 return _ehci_create_int_queue(dev, pipe, queuesize, elementsize,
1532 buffer, interval);
1533 }
1534
1535 void *poll_int_queue(struct usb_device *dev, struct int_queue *queue)
1536 {
1537 return _ehci_poll_int_queue(dev, queue);
1538 }
1539
1540 int destroy_int_queue(struct usb_device *dev, struct int_queue *queue)
1541 {
1542 return _ehci_destroy_int_queue(dev, queue);
1543 }
1544 #endif
1545
1546 #ifdef CONFIG_DM_USB
1547 static int ehci_submit_control_msg(struct udevice *dev, struct usb_device *udev,
1548 unsigned long pipe, void *buffer, int length,
1549 struct devrequest *setup)
1550 {
1551 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
1552 dev->name, udev, udev->dev->name, udev->portnr);
1553
1554 return _ehci_submit_control_msg(udev, pipe, buffer, length, setup);
1555 }
1556
1557 static int ehci_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
1558 unsigned long pipe, void *buffer, int length)
1559 {
1560 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1561 return _ehci_submit_bulk_msg(udev, pipe, buffer, length);
1562 }
1563
1564 static int ehci_submit_int_msg(struct udevice *dev, struct usb_device *udev,
1565 unsigned long pipe, void *buffer, int length,
1566 int interval)
1567 {
1568 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1569 return _ehci_submit_int_msg(udev, pipe, buffer, length, interval);
1570 }
1571
1572 static struct int_queue *ehci_create_int_queue(struct udevice *dev,
1573 struct usb_device *udev, unsigned long pipe, int queuesize,
1574 int elementsize, void *buffer, int interval)
1575 {
1576 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1577 return _ehci_create_int_queue(udev, pipe, queuesize, elementsize,
1578 buffer, interval);
1579 }
1580
1581 static void *ehci_poll_int_queue(struct udevice *dev, struct usb_device *udev,
1582 struct int_queue *queue)
1583 {
1584 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1585 return _ehci_poll_int_queue(udev, queue);
1586 }
1587
1588 static int ehci_destroy_int_queue(struct udevice *dev, struct usb_device *udev,
1589 struct int_queue *queue)
1590 {
1591 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1592 return _ehci_destroy_int_queue(udev, queue);
1593 }
1594
1595 int ehci_register(struct udevice *dev, struct ehci_hccr *hccr,
1596 struct ehci_hcor *hcor, const struct ehci_ops *ops,
1597 uint tweaks, enum usb_init_type init)
1598 {
1599 struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
1600 struct ehci_ctrl *ctrl = dev_get_priv(dev);
1601 int ret;
1602
1603 debug("%s: dev='%s', ctrl=%p, hccr=%p, hcor=%p, init=%d\n", __func__,
1604 dev->name, ctrl, hccr, hcor, init);
1605
1606 priv->desc_before_addr = true;
1607
1608 ehci_setup_ops(ctrl, ops);
1609 ctrl->hccr = hccr;
1610 ctrl->hcor = hcor;
1611 ctrl->priv = ctrl;
1612
1613 ctrl->init = init;
1614 if (ctrl->init == USB_INIT_DEVICE)
1615 goto done;
1616
1617 ret = ehci_reset(ctrl);
1618 if (ret)
1619 goto err;
1620
1621 if (ctrl->ops.init_after_reset) {
1622 ret = ctrl->ops.init_after_reset(ctrl);
1623 if (ret)
1624 goto err;
1625 }
1626
1627 ret = ehci_common_init(ctrl, tweaks);
1628 if (ret)
1629 goto err;
1630 done:
1631 return 0;
1632 err:
1633 free(ctrl);
1634 debug("%s: failed, ret=%d\n", __func__, ret);
1635 return ret;
1636 }
1637
1638 int ehci_deregister(struct udevice *dev)
1639 {
1640 struct ehci_ctrl *ctrl = dev_get_priv(dev);
1641
1642 if (ctrl->init == USB_INIT_DEVICE)
1643 return 0;
1644
1645 ehci_shutdown(ctrl);
1646
1647 return 0;
1648 }
1649
1650 struct dm_usb_ops ehci_usb_ops = {
1651 .control = ehci_submit_control_msg,
1652 .bulk = ehci_submit_bulk_msg,
1653 .interrupt = ehci_submit_int_msg,
1654 .create_int_queue = ehci_create_int_queue,
1655 .poll_int_queue = ehci_poll_int_queue,
1656 .destroy_int_queue = ehci_destroy_int_queue,
1657 };
1658
1659 #endif
"Das U-Boot" Source Tree